Lines Matching +full:timeout +full:- +full:ulp +full:- +full:ms
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
53 #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
93 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
106 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
107 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
144 /* Half-duplex collision counts */
171 #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
172 #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
173 #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
174 #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
175 #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
177 /* enable ULP even if when phy powered down via lanphypc */
179 /* disable clear of sticky ULP on PERST */
192 /* Strapping Option Register - RO */
203 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
222 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */