355 		e_dbg("Failed to initialize PHY flow\n");  in e1000_init_phy_workarounds_pchlan()
377 			e_dbg("Failed to reconfigure K1 exit timeout\n");  in e1000_init_phy_workarounds_pchlan()
413 			e_dbg("Required LANPHYPC toggle blocked by ME\n");  in e1000_init_phy_workarounds_pchlan()
617 			e_dbg("Cannot determine PHY addr. Erroring out\n");  in e1000_init_phy_params_ich8lan()
703 			e_dbg("ERROR: Flash registers not mapped\n");  in e1000_init_nvm_params_ich8lan()
1107 			e_dbg("max_frame_size not set.\n");  in e1000_platform_pm_pch_lpt()
1113 			e_dbg("Speed not set.\n");  in e1000_platform_pm_pch_lpt()
1138 			e_dbg("Invalid LTR latency scale %d\n", scale);  in e1000_platform_pm_pch_lpt()
1257 		e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",  in e1000_enable_ulp_lpt_lp()
1268 		e_dbg("Failed to force SMBUS: %d\n", ret_val);  in e1000_enable_ulp_lpt_lp()
1335 		e_dbg("Error in ULP enable flow: %d\n", ret_val);  in e1000_enable_ulp_lpt_lp()
1402 			e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",  in e1000_disable_ulp_lpt_lp()
1499 		e_dbg("Error in ULP disable flow: %d\n", ret_val);  in e1000_disable_ulp_lpt_lp()
1769 		e_dbg("Error configuring flow control\n");  in e1000_check_for_copper_link_ich8lan()
1880 		e_dbg("contention for Phy access\n");  in e1000_acquire_swflag_ich8lan()
1894 		e_dbg("SW has already locked the resource.\n");  in e1000_acquire_swflag_ich8lan()
1914 		e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",  in e1000_acquire_swflag_ich8lan()
1946 		e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");  in e1000_release_swflag_ich8lan()
2045 		e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",  in e1000_rar_set_pch2lan()
2050 	e_dbg("Failed to write receive address at index %d\n", index);  in e1000_rar_set_pch2lan()
2160 	e_dbg("Failed to write receive address at index %d\n", index);  in e1000_rar_set_pch_lpt()
2216 			e_dbg("Unsupported SMB frequency in PHY\n");  in e1000_write_smbus_addr()
2985 		e_dbg("LAN_INIT_DONE not set, increase timeout\n");  in e1000_lan_init_done_ich8lan()
3342 		e_dbg("ERROR: No valid NVM bank present\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3356 		e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3385 		e_dbg("ERROR: No valid NVM bank present\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3413 		e_dbg("nvm parameter(s) out of bounds\n");  in e1000_read_nvm_spt()
3422 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_read_nvm_spt()
3478 		e_dbg("NVM read error: %d\n", ret_val);  in e1000_read_nvm_spt()
3504 		e_dbg("nvm parameter(s) out of bounds\n");  in e1000_read_nvm_ich8lan()
3513 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_read_nvm_ich8lan()
3538 		e_dbg("NVM read error: %d\n", ret_val);  in e1000_read_nvm_ich8lan()
3559 		e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");  in e1000_flash_cycle_init_ich8lan()
3615 			e_dbg("Flash controller busy, cannot get access\n");  in e1000_flash_cycle_init_ich8lan()
3793 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data_ich8lan()
3868 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data32_ich8lan()
3895 		e_dbg("nvm parameter(s) out of bounds\n");  in e1000_write_nvm_ich8lan()
3945 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_update_nvm_checksum_spt()
4011 		e_dbg("Flash commit failed.\n");  in e1000_update_nvm_checksum_spt()
4067 		e_dbg("NVM update error: %d\n", ret_val);  in e1000_update_nvm_checksum_spt()
4106 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_update_nvm_checksum_ich8lan()
4168 		e_dbg("Flash commit failed.\n");  in e1000_update_nvm_checksum_ich8lan()
4218 		e_dbg("NVM update error: %d\n", ret_val);  in e1000_update_nvm_checksum_ich8lan()
4267 		e_dbg("NVM Checksum valid bit not set\n");  in e1000_validate_nvm_checksum_ich8lan()
4409 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data_ich8lan()
4493 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data32_ich8lan()
4539 		e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);  in e1000_retry_write_flash_dword_ich8lan()
4571 		e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);  in e1000_retry_write_flash_byte_ich8lan()
4710 		e_dbg("NVM Read Error\n");  in e1000_valid_led_default_ich8lan()
4836 		e_dbg("PCI-E Master disable polling has failed.\n");  in e1000_reset_hw_ich8lan()
4838 	e_dbg("Masking off all interrupts\n");  in e1000_reset_hw_ich8lan()
4888 	e_dbg("Issuing a global reset to ich8lan\n");  in e1000_reset_hw_ich8lan()
4959 			e_dbg("Error failed to reconfigure K1 exit timeout\n");  in e1000_init_hw_ich8lan()
4968 		e_dbg("Error initializing identification LED\n");  in e1000_init_hw_ich8lan()
4974 	e_dbg("Zeroing the MTA\n");  in e1000_init_hw_ich8lan()
5151 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);  in e1000_setup_link_ich8lan()
5391 		e_dbg("Workaround applies to ICH8 only.\n");  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5627 		e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);  in e1000_resume_workarounds_pchlan()
5641 			e_dbg("Failed to setup iRST\n");  in e1000_resume_workarounds_pchlan()
5671 			e_dbg("Error %d in resume workarounds\n", ret_val);  in e1000_resume_workarounds_pchlan()
5836 			e_dbg("Auto Read Done did not complete\n");  in e1000_get_cfg_done_ich8lan()
5846 		e_dbg("PHY Reset Asserted not set - needs delay\n");  in e1000_get_cfg_done_ich8lan()
5857 			e_dbg("EEPROM not present\n");  in e1000_get_cfg_done_ich8lan()