Lines Matching +full:timeout +full:- +full:ulp +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
143 return readw(hw->flash_address + reg); in __er16flash()
148 return readl(hw->flash_address + reg); in __er32flash()
153 writew(val, hw->flash_address + reg); in __ew16flash()
158 writel(val, hw->flash_address + reg); in __ew32flash()
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
199 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
200 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
203 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
211 if (hw->mac.type < e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
212 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
216 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
222 if (hw->mac.type >= e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
275 if (hw->mac.type < e1000_pch_lpt) { in e1000_toggle_lanphypc_pch_lpt()
282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); in e1000_toggle_lanphypc_pch_lpt()
289 * e1000_reconfigure_k1_exit_timeout - reconfigure K1 exit timeout to
302 if (hw->mac.type < e1000_pch_mtp) in e1000_reconfigure_k1_exit_timeout()
314 /* Change K1 exit timeout */ in e1000_reconfigure_k1_exit_timeout()
328 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
336 struct e1000_adapter *adapter = hw->adapter; in e1000_init_phy_workarounds_pchlan()
341 * non-managed 82579 and newer adapters. in e1000_init_phy_workarounds_pchlan()
345 /* It is not possible to be certain of the current state of ULP in e1000_init_phy_workarounds_pchlan()
348 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; in e1000_init_phy_workarounds_pchlan()
351 e_warn("Failed to disable ULP\n"); in e1000_init_phy_workarounds_pchlan()
353 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
364 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is in e1000_init_phy_workarounds_pchlan()
368 switch (hw->mac.type) { in e1000_init_phy_workarounds_pchlan()
377 e_dbg("Failed to reconfigure K1 exit timeout\n"); in e1000_init_phy_workarounds_pchlan()
408 if ((hw->mac.type == e1000_pchlan) && in e1000_init_phy_workarounds_pchlan()
412 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
414 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
420 if (hw->mac.type >= e1000_pch_lpt) { in e1000_init_phy_workarounds_pchlan()
434 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
443 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
447 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
467 ret_val = hw->phy.ops.check_reset_block(hw); in e1000_init_phy_workarounds_pchlan()
473 if (hw->mac.type >= e1000_pch_mtp) { in e1000_init_phy_workarounds_pchlan()
474 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
476 e_err("Failed to reconfigure K1 exit timeout\n"); in e1000_init_phy_workarounds_pchlan()
480 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
485 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_init_phy_workarounds_pchlan()
486 if ((hw->mac.type == e1000_pch2lan) && in e1000_init_phy_workarounds_pchlan()
496 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
499 * Initialize family-specific PHY parameters and function pointers.
503 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_pchlan()
506 phy->addr = 1; in e1000_init_phy_params_pchlan()
507 phy->reset_delay_us = 100; in e1000_init_phy_params_pchlan()
509 phy->ops.set_page = e1000_set_page_igp; in e1000_init_phy_params_pchlan()
510 phy->ops.read_reg = e1000_read_phy_reg_hv; in e1000_init_phy_params_pchlan()
511 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
512 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
513 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
514 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
515 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
516 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
517 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
518 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_pchlan()
519 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_pchlan()
520 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_pchlan()
522 phy->id = e1000_phy_unknown; in e1000_init_phy_params_pchlan()
524 if (hw->mac.type == e1000_pch_mtp) { in e1000_init_phy_params_pchlan()
525 phy->retry_count = 2; in e1000_init_phy_params_pchlan()
533 if (phy->id == e1000_phy_unknown) in e1000_init_phy_params_pchlan()
534 switch (hw->mac.type) { in e1000_init_phy_params_pchlan()
539 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) in e1000_init_phy_params_pchlan()
563 phy->type = e1000e_get_phy_type_from_id(phy->id); in e1000_init_phy_params_pchlan()
565 switch (phy->type) { in e1000_init_phy_params_pchlan()
569 phy->ops.check_polarity = e1000_check_polarity_82577; in e1000_init_phy_params_pchlan()
570 phy->ops.force_speed_duplex = in e1000_init_phy_params_pchlan()
572 phy->ops.get_cable_length = e1000_get_cable_length_82577; in e1000_init_phy_params_pchlan()
573 phy->ops.get_info = e1000_get_phy_info_82577; in e1000_init_phy_params_pchlan()
574 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_pchlan()
577 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_pchlan()
578 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_pchlan()
579 phy->ops.get_cable_length = e1000e_get_cable_length_m88; in e1000_init_phy_params_pchlan()
580 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_pchlan()
583 ret_val = -E1000_ERR_PHY; in e1000_init_phy_params_pchlan()
591 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
594 * Initialize family-specific PHY parameters and function pointers.
598 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_ich8lan()
602 phy->addr = 1; in e1000_init_phy_params_ich8lan()
603 phy->reset_delay_us = 100; in e1000_init_phy_params_ich8lan()
605 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_ich8lan()
606 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_ich8lan()
608 /* We may need to do this twice - once for IGP and if that fails, in e1000_init_phy_params_ich8lan()
613 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
614 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
622 phy->id = 0; in e1000_init_phy_params_ich8lan()
623 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && in e1000_init_phy_params_ich8lan()
632 switch (phy->id) { in e1000_init_phy_params_ich8lan()
634 phy->type = e1000_phy_igp_3; in e1000_init_phy_params_ich8lan()
635 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
636 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
637 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
638 phy->ops.get_info = e1000e_get_phy_info_igp; in e1000_init_phy_params_ich8lan()
639 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_ich8lan()
640 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; in e1000_init_phy_params_ich8lan()
645 phy->type = e1000_phy_ife; in e1000_init_phy_params_ich8lan()
646 phy->autoneg_mask = E1000_ALL_NOT_GIG; in e1000_init_phy_params_ich8lan()
647 phy->ops.get_info = e1000_get_phy_info_ife; in e1000_init_phy_params_ich8lan()
648 phy->ops.check_polarity = e1000_check_polarity_ife; in e1000_init_phy_params_ich8lan()
649 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; in e1000_init_phy_params_ich8lan()
652 phy->type = e1000_phy_bm; in e1000_init_phy_params_ich8lan()
653 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
654 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
655 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
656 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_ich8lan()
657 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_ich8lan()
658 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_ich8lan()
659 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_ich8lan()
662 return -E1000_ERR_PHY; in e1000_init_phy_params_ich8lan()
669 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
672 * Initialize family-specific NVM parameters and function
677 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_ich8lan()
678 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_init_nvm_params_ich8lan()
683 nvm->type = e1000_nvm_flash_sw; in e1000_init_nvm_params_ich8lan()
685 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
692 nvm->flash_base_addr = 0; in e1000_init_nvm_params_ich8lan()
695 nvm->flash_bank_size = nvm_size / 2; in e1000_init_nvm_params_ich8lan()
697 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
699 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; in e1000_init_nvm_params_ich8lan()
702 if (!hw->flash_address) { in e1000_init_nvm_params_ich8lan()
704 return -E1000_ERR_CONFIG; in e1000_init_nvm_params_ich8lan()
709 /* sector_X_addr is a "sector"-aligned address (4096 bytes) in e1000_init_nvm_params_ich8lan()
716 /* flash_base_addr is byte-aligned */ in e1000_init_nvm_params_ich8lan()
717 nvm->flash_base_addr = sector_base_addr in e1000_init_nvm_params_ich8lan()
723 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) in e1000_init_nvm_params_ich8lan()
725 nvm->flash_bank_size /= 2; in e1000_init_nvm_params_ich8lan()
727 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
730 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; in e1000_init_nvm_params_ich8lan()
733 for (i = 0; i < nvm->word_size; i++) { in e1000_init_nvm_params_ich8lan()
734 dev_spec->shadow_ram[i].modified = false; in e1000_init_nvm_params_ich8lan()
735 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_init_nvm_params_ich8lan()
742 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
745 * Initialize family-specific MAC parameters and function
750 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_ich8lan()
753 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_ich8lan()
756 mac->mta_reg_count = 32; in e1000_init_mac_params_ich8lan()
758 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
759 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
760 mac->rar_entry_count--; in e1000_init_mac_params_ich8lan()
762 mac->has_fwsm = true; in e1000_init_mac_params_ich8lan()
764 mac->arc_subsystem_valid = false; in e1000_init_mac_params_ich8lan()
766 mac->adaptive_ifs = true; in e1000_init_mac_params_ich8lan()
769 switch (mac->type) { in e1000_init_mac_params_ich8lan()
774 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; in e1000_init_mac_params_ich8lan()
776 mac->ops.id_led_init = e1000e_id_led_init_generic; in e1000_init_mac_params_ich8lan()
778 mac->ops.blink_led = e1000e_blink_led_generic; in e1000_init_mac_params_ich8lan()
780 mac->ops.setup_led = e1000e_setup_led_generic; in e1000_init_mac_params_ich8lan()
782 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; in e1000_init_mac_params_ich8lan()
784 mac->ops.led_on = e1000_led_on_ich8lan; in e1000_init_mac_params_ich8lan()
785 mac->ops.led_off = e1000_led_off_ich8lan; in e1000_init_mac_params_ich8lan()
788 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
789 mac->ops.rar_set = e1000_rar_set_pch2lan; in e1000_init_mac_params_ich8lan()
802 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; in e1000_init_mac_params_ich8lan()
804 mac->ops.id_led_init = e1000_id_led_init_pchlan; in e1000_init_mac_params_ich8lan()
806 mac->ops.setup_led = e1000_setup_led_pchlan; in e1000_init_mac_params_ich8lan()
808 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; in e1000_init_mac_params_ich8lan()
810 mac->ops.led_on = e1000_led_on_pchlan; in e1000_init_mac_params_ich8lan()
811 mac->ops.led_off = e1000_led_off_pchlan; in e1000_init_mac_params_ich8lan()
817 if (mac->type >= e1000_pch_lpt) { in e1000_init_mac_params_ich8lan()
818 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
819 mac->ops.rar_set = e1000_rar_set_pch_lpt; in e1000_init_mac_params_ich8lan()
820 mac->ops.setup_physical_interface = in e1000_init_mac_params_ich8lan()
822 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; in e1000_init_mac_params_ich8lan()
825 /* Enable PCS Lock-loss workaround for ICH8 */ in e1000_init_mac_params_ich8lan()
826 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
833 * __e1000_access_emi_reg_locked - Read/write EMI register
859 * e1000_read_emi_reg_locked - Read Extended Management Interface register
872 * e1000_write_emi_reg_locked - Write Extended Management Interface register
885 * e1000_set_eee_pchlan - Enable/disable EEE support
900 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_eee_pchlan()
904 switch (hw->phy.type) { in e1000_set_eee_pchlan()
919 ret_val = hw->phy.ops.acquire(hw); in e1000_set_eee_pchlan()
931 if (!dev_spec->eee_disable) { in e1000_set_eee_pchlan()
934 &dev_spec->eee_lp_ability); in e1000_set_eee_pchlan()
946 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) in e1000_set_eee_pchlan()
949 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { in e1000_set_eee_pchlan()
955 * partner's EEE in 100 ability if full-duplex in e1000_set_eee_pchlan()
958 dev_spec->eee_lp_ability &= in e1000_set_eee_pchlan()
963 if (hw->phy.type == e1000_phy_82579) { in e1000_set_eee_pchlan()
974 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ in e1000_set_eee_pchlan()
981 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
987 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
993 * the de-assertion of the clock request when in 1Gpbs mode.
994 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1005 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_workaround_lpt_lp()
1032 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
1037 if ((hw->phy.revision > 5) || !link || in e1000_k1_workaround_lpt_lp()
1046 /* Clear link status transmit timeout */ in e1000_k1_workaround_lpt_lp()
1050 /* Set inband Tx timeout to 5x10us for 100Half */ in e1000_k1_workaround_lpt_lp()
1056 /* Set inband Tx timeout to 50x10us for 10Full/Half */ in e1000_k1_workaround_lpt_lp()
1076 * e1000_platform_pm_pch_lpt - Set platform power management values
1080 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1084 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1087 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1088 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1106 if (!hw->adapter->max_frame_size) { in e1000_platform_pm_pch_lpt()
1108 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1111 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in e1000_platform_pm_pch_lpt()
1114 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1123 * a 3-bit encoded scale (only 0-5 are valid) multiplied by in e1000_platform_pm_pch_lpt()
1124 * a 10-bit value (0-1023) to provide a range from 1 ns to in e1000_platform_pm_pch_lpt()
1125 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, in e1000_platform_pm_pch_lpt()
1129 value = (rxa > hw->adapter->max_frame_size) ? in e1000_platform_pm_pch_lpt()
1130 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : in e1000_platform_pm_pch_lpt()
1139 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1144 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, in e1000_platform_pm_pch_lpt()
1146 pci_read_config_word(hw->adapter->pdev, in e1000_platform_pm_pch_lpt()
1162 /* Set Snoop and No-Snoop latencies the same */ in e1000_platform_pm_pch_lpt()
1170 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode.
1210 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1214 * When link is down, configure ULP mode to significantly reduce the power
1216 * ME firmware to start the ULP configuration. If not on an ME enabled
1217 * system, configure the ULP mode by software.
1226 if ((hw->mac.type < e1000_pch_lpt) || in e1000_enable_ulp_lpt_lp()
1227 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_enable_ulp_lpt_lp()
1228 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_enable_ulp_lpt_lp()
1229 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_enable_ulp_lpt_lp()
1230 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_enable_ulp_lpt_lp()
1231 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) in e1000_enable_ulp_lpt_lp()
1235 /* Request ME configure ULP mode in the PHY */ in e1000_enable_ulp_lpt_lp()
1248 /* Bail if link is re-acquired */ in e1000_enable_ulp_lpt_lp()
1250 return -E1000_ERR_PHY; in e1000_enable_ulp_lpt_lp()
1262 ret_val = hw->phy.ops.acquire(hw); in e1000_enable_ulp_lpt_lp()
1272 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable in e1000_enable_ulp_lpt_lp()
1273 * LPLU and disable Gig speed when entering ULP in e1000_enable_ulp_lpt_lp()
1275 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { in e1000_enable_ulp_lpt_lp()
1291 /* Set Inband ULP Exit, Reset to SMBus mode and in e1000_enable_ulp_lpt_lp()
1319 /* Commit ULP changes in PHY by starting auto ULP configuration */ in e1000_enable_ulp_lpt_lp()
1323 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && in e1000_enable_ulp_lpt_lp()
1332 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1335 e_dbg("Error in ULP enable flow: %d\n", ret_val); in e1000_enable_ulp_lpt_lp()
1337 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; in e1000_enable_ulp_lpt_lp()
1343 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1345 * @force: boolean indicating whether or not to force disabling ULP
1347 * Un-configure ULP mode when link is up, the system is transitioned from
1349 * system, poll for an indication from ME that ULP has been un-configured.
1350 * If not on an ME enabled system, un-configure the ULP mode by software.
1353 * to disable ULP mode (force=false); otherwise, for example when unloading
1354 * the driver or during Sx->S0 transitions, this is called with force=true
1355 * to forcibly disable ULP.
1364 if ((hw->mac.type < e1000_pch_lpt) || in e1000_disable_ulp_lpt_lp()
1365 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_disable_ulp_lpt_lp()
1366 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_disable_ulp_lpt_lp()
1367 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_disable_ulp_lpt_lp()
1368 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_disable_ulp_lpt_lp()
1369 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) in e1000_disable_ulp_lpt_lp()
1373 struct e1000_adapter *adapter = hw->adapter; in e1000_disable_ulp_lpt_lp()
1377 /* Request ME un-configure ULP mode in the PHY */ in e1000_disable_ulp_lpt_lp()
1390 ret_val = -E1000_ERR_PHY; in e1000_disable_ulp_lpt_lp()
1410 /* Clear H2ME.ULP after ME ULP configuration */ in e1000_disable_ulp_lpt_lp()
1419 ret_val = hw->phy.ops.acquire(hw); in e1000_disable_ulp_lpt_lp()
1459 /* When ULP mode was previously entered, K1 was disabled by the in e1000_disable_ulp_lpt_lp()
1460 * hardware. Re-Enable K1 in the PHY when exiting ULP. in e1000_disable_ulp_lpt_lp()
1468 /* Clear ULP enabled configuration */ in e1000_disable_ulp_lpt_lp()
1482 /* Commit ULP changes by starting auto ULP configuration */ in e1000_disable_ulp_lpt_lp()
1492 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1499 e_dbg("Error in ULP disable flow: %d\n", ret_val); in e1000_disable_ulp_lpt_lp()
1501 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; in e1000_disable_ulp_lpt_lp()
1507 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1516 struct e1000_mac_info *mac = &hw->mac; in e1000_check_for_copper_link_ich8lan()
1522 /* We only want to go out to the PHY registers to see if Auto-Neg in e1000_check_for_copper_link_ich8lan()
1527 if (!mac->get_link_status) in e1000_check_for_copper_link_ich8lan()
1529 mac->get_link_status = false; in e1000_check_for_copper_link_ich8lan()
1539 if (hw->mac.type == e1000_pchlan) { in e1000_check_for_copper_link_ich8lan()
1545 /* When connected at 10Mbps half-duplex, some parts are excessively in e1000_check_for_copper_link_ich8lan()
1549 if ((hw->mac.type >= e1000_pch2lan) && link) { in e1000_check_for_copper_link_ich8lan()
1560 } else if (hw->mac.type >= e1000_pch_spt && in e1000_check_for_copper_link_ich8lan()
1573 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1577 if (hw->mac.type == e1000_pch2lan) in e1000_check_for_copper_link_ich8lan()
1583 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1595 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1600 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1604 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1609 if (hw->mac.type >= e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1614 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1622 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1635 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1639 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1646 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1659 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1668 /* Work-around I218 hang issue */ in e1000_check_for_copper_link_ich8lan()
1669 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || in e1000_check_for_copper_link_ich8lan()
1670 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || in e1000_check_for_copper_link_ich8lan()
1671 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || in e1000_check_for_copper_link_ich8lan()
1672 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { in e1000_check_for_copper_link_ich8lan()
1677 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1687 hw->dev_spec.ich8lan.eee_lp_ability = 0; in e1000_check_for_copper_link_ich8lan()
1689 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1692 if (hw->mac.type == e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1693 /* FEXTNVM6 K1-off workaround - for SPT only */ in e1000_check_for_copper_link_ich8lan()
1708 switch (hw->mac.type) { in e1000_check_for_copper_link_ich8lan()
1715 if (hw->phy.type == e1000_phy_82578) { in e1000_check_for_copper_link_ich8lan()
1721 /* Workaround for PCHx parts in half-duplex: in e1000_check_for_copper_link_ich8lan()
1739 * immediately after link-up in e1000_check_for_copper_link_ich8lan()
1744 if (hw->phy.type > e1000_phy_82579) { in e1000_check_for_copper_link_ich8lan()
1753 if (!mac->autoneg) in e1000_check_for_copper_link_ich8lan()
1754 return -E1000_ERR_CONFIG; in e1000_check_for_copper_link_ich8lan()
1756 /* Auto-Neg is enabled. Auto Speed Detection takes care in e1000_check_for_copper_link_ich8lan()
1760 mac->ops.config_collision_dist(hw); in e1000_check_for_copper_link_ich8lan()
1762 /* Configure Flow Control now that Auto-Neg has completed. in e1000_check_for_copper_link_ich8lan()
1764 * settings because we may have had to re-autoneg with a in e1000_check_for_copper_link_ich8lan()
1774 mac->get_link_status = true; in e1000_check_for_copper_link_ich8lan()
1780 struct e1000_hw *hw = &adapter->hw; in e1000_get_variants_ich8lan()
1791 switch (hw->mac.type) { in e1000_get_variants_ich8lan()
1819 if ((adapter->hw.phy.type == e1000_phy_ife) || in e1000_get_variants_ich8lan()
1820 ((adapter->hw.mac.type >= e1000_pch2lan) && in e1000_get_variants_ich8lan()
1822 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; in e1000_get_variants_ich8lan()
1823 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; in e1000_get_variants_ich8lan()
1825 hw->mac.ops.blink_led = NULL; in e1000_get_variants_ich8lan()
1828 if ((adapter->hw.mac.type == e1000_ich8lan) && in e1000_get_variants_ich8lan()
1829 (adapter->hw.phy.type != e1000_phy_ife)) in e1000_get_variants_ich8lan()
1830 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; in e1000_get_variants_ich8lan()
1833 if ((adapter->hw.mac.type == e1000_pch2lan) && in e1000_get_variants_ich8lan()
1835 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; in e1000_get_variants_ich8lan()
1843 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1856 * e1000_release_nvm_ich8lan - Release NVM mutex
1867 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1875 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; in e1000_acquire_swflag_ich8lan() local
1879 &hw->adapter->state)) { in e1000_acquire_swflag_ich8lan()
1881 return -E1000_ERR_PHY; in e1000_acquire_swflag_ich8lan()
1884 while (timeout) { in e1000_acquire_swflag_ich8lan()
1890 timeout--; in e1000_acquire_swflag_ich8lan()
1893 if (!timeout) { in e1000_acquire_swflag_ich8lan()
1895 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1899 timeout = SW_FLAG_TIMEOUT; in e1000_acquire_swflag_ich8lan()
1904 while (timeout) { in e1000_acquire_swflag_ich8lan()
1910 timeout--; in e1000_acquire_swflag_ich8lan()
1913 if (!timeout) { in e1000_acquire_swflag_ich8lan()
1918 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1924 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_acquire_swflag_ich8lan()
1930 * e1000_release_swflag_ich8lan - Release software control flag
1949 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_release_swflag_ich8lan()
1953 * e1000_check_mng_mode_ich8lan - Checks management mode
1971 * e1000_check_mng_mode_pchlan - Checks management mode
1988 * e1000_rar_set_pch2lan - Set receive address register
1995 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1996 * Use SHRA[0-3] in place of those reserved for ME.
2023 /* RAR[1-6] are owned by manageability. Skip those and program the in e1000_rar_set_pch2lan()
2026 if (index < (u32)(hw->mac.rar_entry_count)) { in e1000_rar_set_pch2lan()
2033 ew32(SHRAL(index - 1), rar_low); in e1000_rar_set_pch2lan()
2035 ew32(SHRAH(index - 1), rar_high); in e1000_rar_set_pch2lan()
2041 if ((er32(SHRAL(index - 1)) == rar_low) && in e1000_rar_set_pch2lan()
2042 (er32(SHRAH(index - 1)) == rar_high)) in e1000_rar_set_pch2lan()
2045 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", in e1000_rar_set_pch2lan()
2046 (index - 1), er32(FWSM)); in e1000_rar_set_pch2lan()
2051 return -E1000_ERR_CONFIG; in e1000_rar_set_pch2lan()
2055 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
2059 * program. SHRA[0-10] are the shared receive address registers
2075 num_entries = hw->mac.rar_entry_count; in e1000_rar_get_count_pch_lpt()
2082 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ in e1000_rar_get_count_pch_lpt()
2091 * e1000_rar_set_pch_lpt - Set receive address registers
2098 * contain the MAC address. SHRA[0-10] are the shared receive address
2127 * it is using - those registers are unavailable for use. in e1000_rar_set_pch_lpt()
2129 if (index < hw->mac.rar_entry_count) { in e1000_rar_set_pch_lpt()
2145 ew32(SHRAL_PCH_LPT(index - 1), rar_low); in e1000_rar_set_pch_lpt()
2147 ew32(SHRAH_PCH_LPT(index - 1), rar_high); in e1000_rar_set_pch_lpt()
2153 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && in e1000_rar_set_pch_lpt()
2154 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) in e1000_rar_set_pch_lpt()
2161 return -E1000_ERR_CONFIG; in e1000_rar_set_pch_lpt()
2165 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2184 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2207 if (hw->phy.type == e1000_phy_i217) { in e1000_write_smbus_addr()
2209 if (freq--) { in e1000_write_smbus_addr()
2214 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); in e1000_write_smbus_addr()
2224 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2232 struct e1000_phy_info *phy = &hw->phy; in e1000_sw_lcd_config_ich8lan()
2243 switch (hw->mac.type) { in e1000_sw_lcd_config_ich8lan()
2245 if (phy->type != e1000_phy_igp_3) in e1000_sw_lcd_config_ich8lan()
2248 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || in e1000_sw_lcd_config_ich8lan()
2249 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { in e1000_sw_lcd_config_ich8lan()
2271 ret_val = hw->phy.ops.acquire(hw); in e1000_sw_lcd_config_ich8lan()
2283 if ((hw->mac.type < e1000_pch2lan) && in e1000_sw_lcd_config_ich8lan()
2296 if (((hw->mac.type == e1000_pchlan) && in e1000_sw_lcd_config_ich8lan()
2298 (hw->mac.type > e1000_pchlan)) { in e1000_sw_lcd_config_ich8lan()
2345 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
2350 * e1000_k1_gig_workaround_hv - K1 Si workaround
2363 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; in e1000_k1_gig_workaround_hv()
2365 if (hw->mac.type != e1000_pchlan) in e1000_k1_gig_workaround_hv()
2369 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_gig_workaround_hv()
2375 if (hw->phy.type == e1000_phy_82578) { in e1000_k1_gig_workaround_hv()
2391 if (hw->phy.type == e1000_phy_82577) { in e1000_k1_gig_workaround_hv()
2421 hw->phy.ops.release(hw); in e1000_k1_gig_workaround_hv()
2427 * e1000_configure_k1_ich8lan - Configure K1 power state
2434 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2479 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2493 if (hw->mac.type < e1000_pchlan) in e1000_oem_bits_config_ich8lan()
2496 ret_val = hw->phy.ops.acquire(hw); in e1000_oem_bits_config_ich8lan()
2500 if (hw->mac.type == e1000_pchlan) { in e1000_oem_bits_config_ich8lan()
2534 /* Set Restart auto-neg to activate the bits */ in e1000_oem_bits_config_ich8lan()
2535 if ((d0_state || (hw->mac.type != e1000_pchlan)) && in e1000_oem_bits_config_ich8lan()
2536 !hw->phy.ops.check_reset_block(hw)) in e1000_oem_bits_config_ich8lan()
2542 hw->phy.ops.release(hw); in e1000_oem_bits_config_ich8lan()
2548 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2568 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2578 if (hw->mac.type != e1000_pchlan) in e1000_hv_phy_workarounds_ich8lan()
2582 if (hw->phy.type == e1000_phy_82577) { in e1000_hv_phy_workarounds_ich8lan()
2588 if (((hw->phy.type == e1000_phy_82577) && in e1000_hv_phy_workarounds_ich8lan()
2589 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || in e1000_hv_phy_workarounds_ich8lan()
2590 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { in e1000_hv_phy_workarounds_ich8lan()
2602 if (hw->phy.type == e1000_phy_82578) { in e1000_hv_phy_workarounds_ich8lan()
2606 if (hw->phy.revision < 2) { in e1000_hv_phy_workarounds_ich8lan()
2615 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2619 hw->phy.addr = 1; in e1000_hv_phy_workarounds_ich8lan()
2621 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2633 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2646 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2652 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2661 ret_val = hw->phy.ops.acquire(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2669 for (i = 0; i < (hw->mac.rar_entry_count); i++) { in e1000_copy_rx_addrs_to_phy_ich8lan()
2671 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2673 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2677 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2679 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2686 hw->phy.ops.release(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2690 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2702 if (hw->mac.type < e1000_pch2lan) in e1000_lv_jumbo_workaround_ich8lan()
2715 for (i = 0; i < hw->mac.rar_entry_count; i++) { in e1000_lv_jumbo_workaround_ich8lan()
2853 /* re-enable Rx path after enabling/disabling workaround */ in e1000_lv_jumbo_workaround_ich8lan()
2858 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2867 if (hw->mac.type != e1000_pch2lan) in e1000_lv_phy_workarounds_ich8lan()
2875 ret_val = hw->phy.ops.acquire(hw); in e1000_lv_phy_workarounds_ich8lan()
2885 hw->phy.ops.release(hw); in e1000_lv_phy_workarounds_ich8lan()
2891 * e1000_k1_workaround_lv - K1 Si workaround
2902 if (hw->mac.type != e1000_pch2lan) in e1000_k1_workaround_lv()
2938 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2949 if (hw->mac.type < e1000_pch2lan) in e1000_gate_hw_phy_config_ich8lan()
2963 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2978 } while ((!data) && --loop); in e1000_lan_init_done_ich8lan()
2985 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); in e1000_lan_init_done_ich8lan()
2994 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3002 if (hw->phy.ops.check_reset_block(hw)) in e1000_post_phy_reset_ich8lan()
3008 /* Perform any necessary post-reset workarounds */ in e1000_post_phy_reset_ich8lan()
3009 switch (hw->mac.type) { in e1000_post_phy_reset_ich8lan()
3025 if (hw->mac.type >= e1000_pchlan) { in e1000_post_phy_reset_ich8lan()
3039 if (hw->mac.type == e1000_pch2lan) { in e1000_post_phy_reset_ich8lan()
3040 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_post_phy_reset_ich8lan()
3047 ret_val = hw->phy.ops.acquire(hw); in e1000_post_phy_reset_ich8lan()
3053 hw->phy.ops.release(hw); in e1000_post_phy_reset_ich8lan()
3060 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3071 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ in e1000_phy_hw_reset_ich8lan()
3072 if ((hw->mac.type == e1000_pch2lan) && in e1000_phy_hw_reset_ich8lan()
3084 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3091 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3108 if (!hw->phy.ops.check_reset_block(hw)) in e1000_set_lplu_state_pchlan()
3115 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3129 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_ich8lan()
3134 if (phy->type == e1000_phy_ife) in e1000_set_d0_lplu_state_ich8lan()
3143 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3149 if (hw->mac.type == e1000_ich8lan) in e1000_set_d0_lplu_state_ich8lan()
3164 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3172 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state_ich8lan()
3183 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state_ich8lan()
3201 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3215 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_ich8lan()
3226 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3234 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d3_lplu_state_ich8lan()
3245 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d3_lplu_state_ich8lan()
3257 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in e1000_set_d3_lplu_state_ich8lan()
3258 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in e1000_set_d3_lplu_state_ich8lan()
3259 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in e1000_set_d3_lplu_state_ich8lan()
3263 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3269 if (hw->mac.type == e1000_ich8lan) in e1000_set_d3_lplu_state_ich8lan()
3285 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3295 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_valid_nvm_bank_detect_ich8lan()
3296 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); in e1000_valid_nvm_bank_detect_ich8lan()
3302 switch (hw->mac.type) { in e1000_valid_nvm_bank_detect_ich8lan()
3311 bank1_offset = nvm->flash_bank_size; in e1000_valid_nvm_bank_detect_ich8lan()
3343 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3356 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); in e1000_valid_nvm_bank_detect_ich8lan()
3386 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3391 * e1000_read_nvm_spt - NVM access for SPT
3402 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_spt()
3403 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_spt()
3411 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_spt()
3414 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_spt()
3418 nvm->ops.acquire(hw); in e1000_read_nvm_spt()
3426 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_spt()
3432 if (words - i == 1) { in e1000_read_nvm_spt()
3433 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_spt()
3435 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3437 offset_to_read = act_offset + i - in e1000_read_nvm_spt()
3452 if (!(dev_spec->shadow_ram[offset + i].modified) || in e1000_read_nvm_spt()
3453 !(dev_spec->shadow_ram[offset + i + 1].modified)) { in e1000_read_nvm_spt()
3461 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3463 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3466 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3468 dev_spec->shadow_ram[offset + i + 1].value; in e1000_read_nvm_spt()
3474 nvm->ops.release(hw); in e1000_read_nvm_spt()
3484 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3495 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_ich8lan()
3496 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_ich8lan()
3502 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_ich8lan()
3505 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_ich8lan()
3509 nvm->ops.acquire(hw); in e1000_read_nvm_ich8lan()
3517 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_ich8lan()
3522 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_ich8lan()
3523 data[i] = dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_ich8lan()
3534 nvm->ops.release(hw); in e1000_read_nvm_ich8lan()
3544 * e1000_flash_cycle_init_ich8lan - Initialize flash
3553 s32 ret_val = -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3560 return -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3566 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3585 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3605 /* Successful in waiting for previous cycle to timeout, in e1000_flash_cycle_init_ich8lan()
3609 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3623 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3625 * @timeout: maximum time to wait for completion
3629 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) in e1000_flash_cycle_ich8lan() argument
3636 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3642 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3653 } while (i++ < timeout); in e1000_flash_cycle_ich8lan()
3658 return -E1000_ERR_NVM; in e1000_flash_cycle_ich8lan()
3662 * e1000_read_flash_dword_ich8lan - Read dword from flash
3679 * e1000_read_flash_word_ich8lan - Read word from flash
3697 * e1000_read_flash_byte_ich8lan - Read byte from flash
3713 if (hw->mac.type >= e1000_pch_spt) in e1000_read_flash_byte_ich8lan()
3714 return -E1000_ERR_NVM; in e1000_read_flash_byte_ich8lan()
3727 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3742 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3746 return -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3749 hw->nvm.flash_base_addr); in e1000_read_flash_data_ich8lan()
3760 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_read_flash_data_ich8lan()
3793 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data_ich8lan()
3803 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3817 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3820 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) in e1000_read_flash_data32_ich8lan()
3821 return -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3823 hw->nvm.flash_base_addr); in e1000_read_flash_data32_ich8lan()
3837 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_read_flash_data32_ich8lan()
3868 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data32_ich8lan()
3878 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3889 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_write_nvm_ich8lan()
3890 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_write_nvm_ich8lan()
3893 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_write_nvm_ich8lan()
3896 return -E1000_ERR_NVM; in e1000_write_nvm_ich8lan()
3899 nvm->ops.acquire(hw); in e1000_write_nvm_ich8lan()
3902 dev_spec->shadow_ram[offset + i].modified = true; in e1000_write_nvm_ich8lan()
3903 dev_spec->shadow_ram[offset + i].value = data[i]; in e1000_write_nvm_ich8lan()
3906 nvm->ops.release(hw); in e1000_write_nvm_ich8lan()
3912 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3924 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_spt()
3925 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_spt()
3934 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_spt()
3937 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_spt()
3950 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3956 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3971 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_spt()
3973 dword |= (dev_spec->shadow_ram[i].value & 0xffff); in e1000_update_nvm_checksum_spt()
3975 if (dev_spec->shadow_ram[i + 1].modified) { in e1000_update_nvm_checksum_spt()
3977 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) in e1000_update_nvm_checksum_spt()
3990 if (i == E1000_ICH_NVM_SIG_WORD - 1) in e1000_update_nvm_checksum_spt()
4010 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_spt()
4023 --act_offset; in e1000_update_nvm_checksum_spt()
4036 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; in e1000_update_nvm_checksum_spt()
4050 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_spt()
4051 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_spt()
4055 nvm->ops.release(hw); in e1000_update_nvm_checksum_spt()
4061 nvm->ops.reload(hw); in e1000_update_nvm_checksum_spt()
4073 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4085 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_ich8lan()
4086 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_ich8lan()
4095 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_ich8lan()
4098 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_ich8lan()
4111 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4117 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4124 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_ich8lan()
4125 data = dev_spec->shadow_ram[i].value; in e1000_update_nvm_checksum_ich8lan()
4167 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_ich8lan()
4201 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_ich8lan()
4202 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_ich8lan()
4206 nvm->ops.release(hw); in e1000_update_nvm_checksum_ich8lan()
4212 nvm->ops.reload(hw); in e1000_update_nvm_checksum_ich8lan()
4224 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4243 switch (hw->mac.type) { in e1000_validate_nvm_checksum_ich8lan()
4269 if (hw->mac.type < e1000_pch_tgp) { in e1000_validate_nvm_checksum_ich8lan()
4284 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4287 * To prevent malicious write/erase of the NVM, set it to be read-only
4289 * the flash control registers. The shadow-ram copy of the NVM will
4295 struct e1000_nvm_info *nvm = &hw->nvm; in e1000e_write_protect_nvm_ich8lan()
4300 nvm->ops.acquire(hw); in e1000e_write_protect_nvm_ich8lan()
4304 /* Write-protect GbE Sector of NVM */ in e1000e_write_protect_nvm_ich8lan()
4312 * PR0 to prevent the write-protection from being lifted. in e1000e_write_protect_nvm_ich8lan()
4320 nvm->ops.release(hw); in e1000e_write_protect_nvm_ich8lan()
4324 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4342 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data_ich8lan()
4344 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4347 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4351 hw->nvm.flash_base_addr); in e1000_write_flash_data_ich8lan()
4362 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4368 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_write_flash_data_ich8lan()
4374 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4407 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data_ich8lan()
4416 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4432 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data32_ich8lan()
4434 return -E1000_ERR_NVM; in e1000_write_flash_data32_ich8lan()
4437 hw->nvm.flash_base_addr); in e1000_write_flash_data32_ich8lan()
4448 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4454 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_write_flash_data32_ich8lan()
4461 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4491 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data32_ich8lan()
4500 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4516 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4544 return -E1000_ERR_NVM; in e1000_retry_write_flash_dword_ich8lan()
4550 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4576 return -E1000_ERR_NVM; in e1000_retry_write_flash_byte_ich8lan()
4582 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4591 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_erase_flash_bank_ich8lan()
4595 /* bank size is in 16bit words - adjust to bytes */ in e1000_erase_flash_bank_ich8lan()
4596 u32 flash_bank_size = nvm->flash_bank_size * 2; in e1000_erase_flash_bank_ich8lan()
4634 return -E1000_ERR_NVM; in e1000_erase_flash_bank_ich8lan()
4638 flash_linear_addr = hw->nvm.flash_base_addr; in e1000_erase_flash_bank_ich8lan()
4643 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; in e1000_erase_flash_bank_ich8lan() local
4653 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4660 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4673 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); in e1000_erase_flash_bank_ich8lan()
4694 * e1000_valid_led_default_ich8lan - Set the default LED settings
4719 * e1000_id_led_init_pchlan - store LED configurations
4733 struct e1000_mac_info *mac = &hw->mac; in e1000_id_led_init_pchlan()
4740 ret_val = hw->nvm.ops.valid_led_default(hw, &data); in e1000_id_led_init_pchlan()
4744 mac->ledctl_default = er32(LEDCTL); in e1000_id_led_init_pchlan()
4745 mac->ledctl_mode1 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4746 mac->ledctl_mode2 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4755 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4756 mac->ledctl_mode1 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4761 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4762 mac->ledctl_mode1 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4772 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4773 mac->ledctl_mode2 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4778 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4779 mac->ledctl_mode2 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4791 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4799 struct e1000_bus_info *bus = &hw->bus; in e1000_get_bus_info_ich8lan()
4804 /* ICH devices are "PCI Express"-ish. They have in e1000_get_bus_info_ich8lan()
4809 if (bus->width == e1000_bus_width_unknown) in e1000_get_bus_info_ich8lan()
4810 bus->width = e1000_bus_width_pcie_x1; in e1000_get_bus_info_ich8lan()
4816 * e1000_reset_hw_ich8lan - Reset the hardware
4824 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_reset_hw_ich8lan()
4829 /* Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_ich8lan()
4834 e_dbg("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_ich8lan()
4850 if (hw->mac.type == e1000_ich8lan) { in e1000_reset_hw_ich8lan()
4857 if (hw->mac.type == e1000_pchlan) { in e1000_reset_hw_ich8lan()
4864 dev_spec->nvm_k1_enabled = true; in e1000_reset_hw_ich8lan()
4866 dev_spec->nvm_k1_enabled = false; in e1000_reset_hw_ich8lan()
4871 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_reset_hw_ich8lan()
4872 /* Full-chip reset requires MAC and PHY reset at the same in e1000_reset_hw_ich8lan()
4879 * non-managed 82579 in e1000_reset_hw_ich8lan()
4881 if ((hw->mac.type == e1000_pch2lan) && in e1000_reset_hw_ich8lan()
4892 if (hw->mac.type == e1000_pch2lan) { in e1000_reset_hw_ich8lan()
4900 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_reset_hw_ich8lan()
4903 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_reset_hw_ich8lan()
4916 if (hw->mac.type == e1000_pchlan) in e1000_reset_hw_ich8lan()
4930 * e1000_init_hw_ich8lan - Initialize the hardware
4934 * - initialize hardware bits
4935 * - initialize LED identification
4936 * - setup receive address registers
4937 * - setup flow control
4938 * - setup transmit descriptors
4939 * - clear statistics
4943 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_ich8lan()
4949 if (hw->mac.type >= e1000_pch_mtp) { in e1000_init_hw_ich8lan()
4950 ret_val = hw->phy.ops.acquire(hw); in e1000_init_hw_ich8lan()
4955 hw->phy.ops.release(hw); in e1000_init_hw_ich8lan()
4957 e_dbg("Error failed to reconfigure K1 exit timeout\n"); in e1000_init_hw_ich8lan()
4963 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_ich8lan()
4969 e1000e_init_rx_addrs(hw, mac->rar_entry_count); in e1000_init_hw_ich8lan()
4973 for (i = 0; i < mac->mta_reg_count; i++) in e1000_init_hw_ich8lan()
4980 if (hw->phy.type == e1000_phy_82578) { in e1000_init_hw_ich8lan()
4990 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_ich8lan()
4992 /* Set the transmit descriptor write-back policy for both queues */ in e1000_init_hw_ich8lan()
5009 if (mac->type == e1000_ich8lan) in e1000_init_hw_ich8lan()
5018 if (mac->type >= e1000_pch_tgp) { in e1000_init_hw_ich8lan()
5039 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5052 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ in e1000_initialize_hw_bits_ich8lan()
5053 if (hw->mac.type >= e1000_pchlan) in e1000_initialize_hw_bits_ich8lan()
5069 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5084 if (hw->mac.type == e1000_ich8lan) { in e1000_initialize_hw_bits_ich8lan()
5090 /* work-around descriptor data corruption issue during nfs v2 udp in e1000_initialize_hw_bits_ich8lan()
5099 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5104 if (hw->mac.type >= e1000_pch_lpt) { in e1000_initialize_hw_bits_ich8lan()
5116 * e1000_setup_link_ich8lan - Setup flow control and link settings
5120 * control. Calls the appropriate media-specific link configuration
5129 if (hw->phy.ops.check_reset_block(hw)) in e1000_setup_link_ich8lan()
5136 if (hw->fc.requested_mode == e1000_fc_default) { in e1000_setup_link_ich8lan()
5138 if (hw->mac.type == e1000_pchlan) in e1000_setup_link_ich8lan()
5139 hw->fc.requested_mode = e1000_fc_rx_pause; in e1000_setup_link_ich8lan()
5141 hw->fc.requested_mode = e1000_fc_full; in e1000_setup_link_ich8lan()
5147 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_ich8lan()
5149 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); in e1000_setup_link_ich8lan()
5152 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_ich8lan()
5156 ew32(FCTTV, hw->fc.pause_time); in e1000_setup_link_ich8lan()
5157 if ((hw->phy.type == e1000_phy_82578) || in e1000_setup_link_ich8lan()
5158 (hw->phy.type == e1000_phy_82579) || in e1000_setup_link_ich8lan()
5159 (hw->phy.type == e1000_phy_i217) || in e1000_setup_link_ich8lan()
5160 (hw->phy.type == e1000_phy_82577)) { in e1000_setup_link_ich8lan()
5161 ew32(FCRTV_PCH, hw->fc.refresh_time); in e1000_setup_link_ich8lan()
5164 hw->fc.pause_time); in e1000_setup_link_ich8lan()
5173 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5208 switch (hw->phy.type) { in e1000_setup_copper_link_ich8lan()
5233 switch (hw->phy.mdix) { in e1000_setup_copper_link_ich8lan()
5257 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5282 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5300 if ((hw->mac.type == e1000_ich8lan) && in e1000_get_link_up_info_ich8lan()
5301 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { in e1000_get_link_up_info_ich8lan()
5309 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5312 * Work-around for 82566 Kumeran PCS lock loss:
5314 * speed is gigabit-
5316 * 1) wait 1ms for Kumeran link to come up
5325 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_kmrn_lock_loss_workaround_ich8lan()
5331 if (!dev_spec->kmrn_lock_loss_workaround_enabled) in e1000_kmrn_lock_loss_workaround_ich8lan()
5372 return -E1000_ERR_PHY; in e1000_kmrn_lock_loss_workaround_ich8lan()
5376 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5380 * If ICH8, set the current Kumeran workaround state (enabled - true
5381 * /disabled - false).
5386 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5388 if (hw->mac.type != e1000_ich8lan) { in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5393 dev_spec->kmrn_lock_loss_workaround_enabled = state; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5397 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5400 * Workaround for 82566 power-down on D3 entry:
5402 * 2) write VR power-down enable
5412 if (hw->phy.type != e1000_phy_igp_3) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5426 if (hw->mac.type == e1000_ich8lan) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5429 /* Write VR power-down enable */ in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5448 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5453 * 1) Set Kumeran Near-end loopback
5454 * 2) Clear Kumeran Near-end loopback
5462 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) in e1000e_gig_downshift_workaround_ich8lan()
5479 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5494 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_suspend_workarounds_ich8lan()
5501 if (hw->phy.type == e1000_phy_i217) { in e1000_suspend_workarounds_ich8lan()
5502 u16 phy_reg, device_id = hw->adapter->pdev->device; in e1000_suspend_workarounds_ich8lan()
5508 (hw->mac.type >= e1000_pch_spt)) { in e1000_suspend_workarounds_ich8lan()
5514 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5518 if (!dev_spec->eee_disable) { in e1000_suspend_workarounds_ich8lan()
5534 (dev_spec->eee_lp_ability & in e1000_suspend_workarounds_ich8lan()
5536 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { in e1000_suspend_workarounds_ich8lan()
5583 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5588 if (hw->mac.type == e1000_ich8lan) in e1000_suspend_workarounds_ich8lan()
5591 if (hw->mac.type >= e1000_pchlan) { in e1000_suspend_workarounds_ich8lan()
5595 if (hw->mac.type == e1000_pchlan) in e1000_suspend_workarounds_ich8lan()
5598 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5602 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5607 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5610 * During Sx to S0 transitions on non-managed devices or managed devices
5620 if (hw->mac.type < e1000_pch2lan) in e1000_resume_workarounds_pchlan()
5634 if (hw->phy.type == e1000_phy_i217) { in e1000_resume_workarounds_pchlan()
5637 ret_val = hw->phy.ops.acquire(hw); in e1000_resume_workarounds_pchlan()
5670 hw->phy.ops.release(hw); in e1000_resume_workarounds_pchlan()
5675 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5682 if (hw->phy.type == e1000_phy_ife) in e1000_cleanup_led_ich8lan()
5685 ew32(LEDCTL, hw->mac.ledctl_default); in e1000_cleanup_led_ich8lan()
5690 * e1000_led_on_ich8lan - Turn LEDs on
5697 if (hw->phy.type == e1000_phy_ife) in e1000_led_on_ich8lan()
5701 ew32(LEDCTL, hw->mac.ledctl_mode2); in e1000_led_on_ich8lan()
5706 * e1000_led_off_ich8lan - Turn LEDs off
5713 if (hw->phy.type == e1000_phy_ife) in e1000_led_off_ich8lan()
5718 ew32(LEDCTL, hw->mac.ledctl_mode1); in e1000_led_off_ich8lan()
5723 * e1000_setup_led_pchlan - Configures SW controllable LED
5730 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); in e1000_setup_led_pchlan()
5734 * e1000_cleanup_led_pchlan - Restore the default LED operation
5741 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); in e1000_cleanup_led_pchlan()
5745 * e1000_led_on_pchlan - Turn LEDs on
5752 u16 data = (u16)hw->mac.ledctl_mode2; in e1000_led_on_pchlan()
5775 * e1000_led_off_pchlan - Turn LEDs off
5782 u16 data = (u16)hw->mac.ledctl_mode1; in e1000_led_off_pchlan()
5805 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5809 * and configure the PHY through s/w for EEPROM-less parts.
5811 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5813 * to return with error, EEPROM-less silicon would not be able to be reset
5825 if (hw->mac.type >= e1000_ich10lan) { in e1000_get_cfg_done_ich8lan()
5844 e_dbg("PHY Reset Asserted not set - needs delay\n"); in e1000_get_cfg_done_ich8lan()
5847 if (hw->mac.type <= e1000_ich9lan) { in e1000_get_cfg_done_ich8lan()
5849 (hw->phy.type == e1000_phy_igp_3)) { in e1000_get_cfg_done_ich8lan()
5856 ret_val = -E1000_ERR_CONFIG; in e1000_get_cfg_done_ich8lan()
5864 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5873 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_ich8lan()
5874 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_ich8lan()
5879 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5907 if ((hw->phy.type == e1000_phy_82578) || in e1000_clear_hw_cntrs_ich8lan()
5908 (hw->phy.type == e1000_phy_82579) || in e1000_clear_hw_cntrs_ich8lan()
5909 (hw->phy.type == e1000_phy_i217) || in e1000_clear_hw_cntrs_ich8lan()
5910 (hw->phy.type == e1000_phy_82577)) { in e1000_clear_hw_cntrs_ich8lan()
5911 ret_val = hw->phy.ops.acquire(hw); in e1000_clear_hw_cntrs_ich8lan()
5914 ret_val = hw->phy.ops.set_page(hw, in e1000_clear_hw_cntrs_ich8lan()
5918 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5919 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5920 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5921 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5922 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5923 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5924 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5925 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5926 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5927 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5928 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5929 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5930 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5931 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5933 hw->phy.ops.release(hw); in e1000_clear_hw_cntrs_ich8lan()