Lines Matching +full:lynx +full:- +full:28 +full:g
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
90 u32 limit:13; /* 16:28 Protected Range Limit */
143 return readw(hw->flash_address + reg); in __er16flash()
148 return readl(hw->flash_address + reg); in __er32flash()
153 writew(val, hw->flash_address + reg); in __ew16flash()
158 writel(val, hw->flash_address + reg); in __ew32flash()
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
199 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
200 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
203 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
211 if (hw->mac.type < e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
212 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
216 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
222 if (hw->mac.type >= e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
275 if (hw->mac.type < e1000_pch_lpt) { in e1000_toggle_lanphypc_pch_lpt()
282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); in e1000_toggle_lanphypc_pch_lpt()
289 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
297 struct e1000_adapter *adapter = hw->adapter; in e1000_init_phy_workarounds_pchlan()
302 * non-managed 82579 and newer adapters. in e1000_init_phy_workarounds_pchlan()
309 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; in e1000_init_phy_workarounds_pchlan()
314 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is in e1000_init_phy_workarounds_pchlan()
329 switch (hw->mac.type) { in e1000_init_phy_workarounds_pchlan()
362 if ((hw->mac.type == e1000_pchlan) && in e1000_init_phy_workarounds_pchlan()
366 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
368 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
374 if (hw->mac.type >= e1000_pch_lpt) { in e1000_init_phy_workarounds_pchlan()
388 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
397 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
401 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
421 ret_val = hw->phy.ops.check_reset_block(hw); in e1000_init_phy_workarounds_pchlan()
427 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_init_phy_workarounds_pchlan()
428 if ((hw->mac.type == e1000_pch2lan) && in e1000_init_phy_workarounds_pchlan()
438 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
441 * Initialize family-specific PHY parameters and function pointers.
445 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_pchlan()
448 phy->addr = 1; in e1000_init_phy_params_pchlan()
449 phy->reset_delay_us = 100; in e1000_init_phy_params_pchlan()
451 phy->ops.set_page = e1000_set_page_igp; in e1000_init_phy_params_pchlan()
452 phy->ops.read_reg = e1000_read_phy_reg_hv; in e1000_init_phy_params_pchlan()
453 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
454 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
455 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
456 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
457 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
458 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
459 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
460 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_pchlan()
461 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_pchlan()
462 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_pchlan()
464 phy->id = e1000_phy_unknown; in e1000_init_phy_params_pchlan()
466 if (hw->mac.type == e1000_pch_mtp) { in e1000_init_phy_params_pchlan()
467 phy->retry_count = 2; in e1000_init_phy_params_pchlan()
475 if (phy->id == e1000_phy_unknown) in e1000_init_phy_params_pchlan()
476 switch (hw->mac.type) { in e1000_init_phy_params_pchlan()
481 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) in e1000_init_phy_params_pchlan()
505 phy->type = e1000e_get_phy_type_from_id(phy->id); in e1000_init_phy_params_pchlan()
507 switch (phy->type) { in e1000_init_phy_params_pchlan()
511 phy->ops.check_polarity = e1000_check_polarity_82577; in e1000_init_phy_params_pchlan()
512 phy->ops.force_speed_duplex = in e1000_init_phy_params_pchlan()
514 phy->ops.get_cable_length = e1000_get_cable_length_82577; in e1000_init_phy_params_pchlan()
515 phy->ops.get_info = e1000_get_phy_info_82577; in e1000_init_phy_params_pchlan()
516 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_pchlan()
519 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_pchlan()
520 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_pchlan()
521 phy->ops.get_cable_length = e1000e_get_cable_length_m88; in e1000_init_phy_params_pchlan()
522 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_pchlan()
525 ret_val = -E1000_ERR_PHY; in e1000_init_phy_params_pchlan()
533 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
536 * Initialize family-specific PHY parameters and function pointers.
540 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_ich8lan()
544 phy->addr = 1; in e1000_init_phy_params_ich8lan()
545 phy->reset_delay_us = 100; in e1000_init_phy_params_ich8lan()
547 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_ich8lan()
548 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_ich8lan()
550 /* We may need to do this twice - once for IGP and if that fails, in e1000_init_phy_params_ich8lan()
555 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
556 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
564 phy->id = 0; in e1000_init_phy_params_ich8lan()
565 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && in e1000_init_phy_params_ich8lan()
574 switch (phy->id) { in e1000_init_phy_params_ich8lan()
576 phy->type = e1000_phy_igp_3; in e1000_init_phy_params_ich8lan()
577 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
578 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
579 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
580 phy->ops.get_info = e1000e_get_phy_info_igp; in e1000_init_phy_params_ich8lan()
581 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_ich8lan()
582 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; in e1000_init_phy_params_ich8lan()
587 phy->type = e1000_phy_ife; in e1000_init_phy_params_ich8lan()
588 phy->autoneg_mask = E1000_ALL_NOT_GIG; in e1000_init_phy_params_ich8lan()
589 phy->ops.get_info = e1000_get_phy_info_ife; in e1000_init_phy_params_ich8lan()
590 phy->ops.check_polarity = e1000_check_polarity_ife; in e1000_init_phy_params_ich8lan()
591 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; in e1000_init_phy_params_ich8lan()
594 phy->type = e1000_phy_bm; in e1000_init_phy_params_ich8lan()
595 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
596 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
597 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
598 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_ich8lan()
599 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_ich8lan()
600 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_ich8lan()
601 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_ich8lan()
604 return -E1000_ERR_PHY; in e1000_init_phy_params_ich8lan()
611 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
614 * Initialize family-specific NVM parameters and function
619 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_ich8lan()
620 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_init_nvm_params_ich8lan()
625 nvm->type = e1000_nvm_flash_sw; in e1000_init_nvm_params_ich8lan()
627 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
634 nvm->flash_base_addr = 0; in e1000_init_nvm_params_ich8lan()
637 nvm->flash_bank_size = nvm_size / 2; in e1000_init_nvm_params_ich8lan()
639 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
641 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; in e1000_init_nvm_params_ich8lan()
644 if (!hw->flash_address) { in e1000_init_nvm_params_ich8lan()
646 return -E1000_ERR_CONFIG; in e1000_init_nvm_params_ich8lan()
651 /* sector_X_addr is a "sector"-aligned address (4096 bytes) in e1000_init_nvm_params_ich8lan()
658 /* flash_base_addr is byte-aligned */ in e1000_init_nvm_params_ich8lan()
659 nvm->flash_base_addr = sector_base_addr in e1000_init_nvm_params_ich8lan()
665 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) in e1000_init_nvm_params_ich8lan()
667 nvm->flash_bank_size /= 2; in e1000_init_nvm_params_ich8lan()
669 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
672 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; in e1000_init_nvm_params_ich8lan()
675 for (i = 0; i < nvm->word_size; i++) { in e1000_init_nvm_params_ich8lan()
676 dev_spec->shadow_ram[i].modified = false; in e1000_init_nvm_params_ich8lan()
677 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_init_nvm_params_ich8lan()
684 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
687 * Initialize family-specific MAC parameters and function
692 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_ich8lan()
695 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_ich8lan()
698 mac->mta_reg_count = 32; in e1000_init_mac_params_ich8lan()
700 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
701 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
702 mac->rar_entry_count--; in e1000_init_mac_params_ich8lan()
704 mac->has_fwsm = true; in e1000_init_mac_params_ich8lan()
706 mac->arc_subsystem_valid = false; in e1000_init_mac_params_ich8lan()
708 mac->adaptive_ifs = true; in e1000_init_mac_params_ich8lan()
711 switch (mac->type) { in e1000_init_mac_params_ich8lan()
716 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; in e1000_init_mac_params_ich8lan()
718 mac->ops.id_led_init = e1000e_id_led_init_generic; in e1000_init_mac_params_ich8lan()
720 mac->ops.blink_led = e1000e_blink_led_generic; in e1000_init_mac_params_ich8lan()
722 mac->ops.setup_led = e1000e_setup_led_generic; in e1000_init_mac_params_ich8lan()
724 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; in e1000_init_mac_params_ich8lan()
726 mac->ops.led_on = e1000_led_on_ich8lan; in e1000_init_mac_params_ich8lan()
727 mac->ops.led_off = e1000_led_off_ich8lan; in e1000_init_mac_params_ich8lan()
730 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
731 mac->ops.rar_set = e1000_rar_set_pch2lan; in e1000_init_mac_params_ich8lan()
744 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; in e1000_init_mac_params_ich8lan()
746 mac->ops.id_led_init = e1000_id_led_init_pchlan; in e1000_init_mac_params_ich8lan()
748 mac->ops.setup_led = e1000_setup_led_pchlan; in e1000_init_mac_params_ich8lan()
750 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; in e1000_init_mac_params_ich8lan()
752 mac->ops.led_on = e1000_led_on_pchlan; in e1000_init_mac_params_ich8lan()
753 mac->ops.led_off = e1000_led_off_pchlan; in e1000_init_mac_params_ich8lan()
759 if (mac->type >= e1000_pch_lpt) { in e1000_init_mac_params_ich8lan()
760 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
761 mac->ops.rar_set = e1000_rar_set_pch_lpt; in e1000_init_mac_params_ich8lan()
762 mac->ops.setup_physical_interface = in e1000_init_mac_params_ich8lan()
764 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; in e1000_init_mac_params_ich8lan()
767 /* Enable PCS Lock-loss workaround for ICH8 */ in e1000_init_mac_params_ich8lan()
768 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
775 * __e1000_access_emi_reg_locked - Read/write EMI register
801 * e1000_read_emi_reg_locked - Read Extended Management Interface register
814 * e1000_write_emi_reg_locked - Write Extended Management Interface register
827 * e1000_set_eee_pchlan - Enable/disable EEE support
842 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_eee_pchlan()
846 switch (hw->phy.type) { in e1000_set_eee_pchlan()
861 ret_val = hw->phy.ops.acquire(hw); in e1000_set_eee_pchlan()
873 if (!dev_spec->eee_disable) { in e1000_set_eee_pchlan()
876 &dev_spec->eee_lp_ability); in e1000_set_eee_pchlan()
888 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) in e1000_set_eee_pchlan()
891 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { in e1000_set_eee_pchlan()
897 * partner's EEE in 100 ability if full-duplex in e1000_set_eee_pchlan()
900 dev_spec->eee_lp_ability &= in e1000_set_eee_pchlan()
905 if (hw->phy.type == e1000_phy_82579) { in e1000_set_eee_pchlan()
916 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ in e1000_set_eee_pchlan()
923 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
929 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
935 * the de-assertion of the clock request when in 1Gpbs mode.
936 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
947 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_workaround_lpt_lp()
974 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
979 if ((hw->phy.revision > 5) || !link || in e1000_k1_workaround_lpt_lp()
1018 * e1000_platform_pm_pch_lpt - Set platform power management values
1022 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1023 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1026 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1029 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1030 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1048 if (!hw->adapter->max_frame_size) { in e1000_platform_pm_pch_lpt()
1050 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1053 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in e1000_platform_pm_pch_lpt()
1056 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1065 * a 3-bit encoded scale (only 0-5 are valid) multiplied by in e1000_platform_pm_pch_lpt()
1066 * a 10-bit value (0-1023) to provide a range from 1 ns to in e1000_platform_pm_pch_lpt()
1067 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, in e1000_platform_pm_pch_lpt()
1071 value = (rxa > hw->adapter->max_frame_size) ? in e1000_platform_pm_pch_lpt()
1072 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : in e1000_platform_pm_pch_lpt()
1081 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1086 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, in e1000_platform_pm_pch_lpt()
1088 pci_read_config_word(hw->adapter->pdev, in e1000_platform_pm_pch_lpt()
1104 /* Set Snoop and No-Snoop latencies the same */ in e1000_platform_pm_pch_lpt()
1112 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode.
1152 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1168 if ((hw->mac.type < e1000_pch_lpt) || in e1000_enable_ulp_lpt_lp()
1169 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_enable_ulp_lpt_lp()
1170 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_enable_ulp_lpt_lp()
1171 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_enable_ulp_lpt_lp()
1172 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_enable_ulp_lpt_lp()
1173 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) in e1000_enable_ulp_lpt_lp()
1190 /* Bail if link is re-acquired */ in e1000_enable_ulp_lpt_lp()
1192 return -E1000_ERR_PHY; in e1000_enable_ulp_lpt_lp()
1204 ret_val = hw->phy.ops.acquire(hw); in e1000_enable_ulp_lpt_lp()
1217 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { in e1000_enable_ulp_lpt_lp()
1265 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && in e1000_enable_ulp_lpt_lp()
1274 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1279 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; in e1000_enable_ulp_lpt_lp()
1285 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1289 * Un-configure ULP mode when link is up, the system is transitioned from
1291 * system, poll for an indication from ME that ULP has been un-configured.
1292 * If not on an ME enabled system, un-configure the ULP mode by software.
1296 * the driver or during Sx->S0 transitions, this is called with force=true
1306 if ((hw->mac.type < e1000_pch_lpt) || in e1000_disable_ulp_lpt_lp()
1307 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_disable_ulp_lpt_lp()
1308 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_disable_ulp_lpt_lp()
1309 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_disable_ulp_lpt_lp()
1310 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_disable_ulp_lpt_lp()
1311 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) in e1000_disable_ulp_lpt_lp()
1315 struct e1000_adapter *adapter = hw->adapter; in e1000_disable_ulp_lpt_lp()
1319 /* Request ME un-configure ULP mode in the PHY */ in e1000_disable_ulp_lpt_lp()
1332 ret_val = -E1000_ERR_PHY; in e1000_disable_ulp_lpt_lp()
1361 ret_val = hw->phy.ops.acquire(hw); in e1000_disable_ulp_lpt_lp()
1402 * hardware. Re-Enable K1 in the PHY when exiting ULP. in e1000_disable_ulp_lpt_lp()
1434 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1443 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; in e1000_disable_ulp_lpt_lp()
1449 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1458 struct e1000_mac_info *mac = &hw->mac; in e1000_check_for_copper_link_ich8lan()
1464 /* We only want to go out to the PHY registers to see if Auto-Neg in e1000_check_for_copper_link_ich8lan()
1469 if (!mac->get_link_status) in e1000_check_for_copper_link_ich8lan()
1471 mac->get_link_status = false; in e1000_check_for_copper_link_ich8lan()
1481 if (hw->mac.type == e1000_pchlan) { in e1000_check_for_copper_link_ich8lan()
1487 /* When connected at 10Mbps half-duplex, some parts are excessively in e1000_check_for_copper_link_ich8lan()
1491 if ((hw->mac.type >= e1000_pch2lan) && link) { in e1000_check_for_copper_link_ich8lan()
1502 } else if (hw->mac.type >= e1000_pch_spt && in e1000_check_for_copper_link_ich8lan()
1515 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1519 if (hw->mac.type == e1000_pch2lan) in e1000_check_for_copper_link_ich8lan()
1525 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1537 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1542 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1546 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1551 if (hw->mac.type >= e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1556 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1564 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1577 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1581 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1588 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1601 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1610 /* Work-around I218 hang issue */ in e1000_check_for_copper_link_ich8lan()
1611 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || in e1000_check_for_copper_link_ich8lan()
1612 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || in e1000_check_for_copper_link_ich8lan()
1613 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || in e1000_check_for_copper_link_ich8lan()
1614 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { in e1000_check_for_copper_link_ich8lan()
1619 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1629 hw->dev_spec.ich8lan.eee_lp_ability = 0; in e1000_check_for_copper_link_ich8lan()
1631 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1634 if (hw->mac.type == e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1635 /* FEXTNVM6 K1-off workaround - for SPT only */ in e1000_check_for_copper_link_ich8lan()
1650 switch (hw->mac.type) { in e1000_check_for_copper_link_ich8lan()
1657 if (hw->phy.type == e1000_phy_82578) { in e1000_check_for_copper_link_ich8lan()
1663 /* Workaround for PCHx parts in half-duplex: in e1000_check_for_copper_link_ich8lan()
1681 * immediately after link-up in e1000_check_for_copper_link_ich8lan()
1686 if (hw->phy.type > e1000_phy_82579) { in e1000_check_for_copper_link_ich8lan()
1695 if (!mac->autoneg) in e1000_check_for_copper_link_ich8lan()
1696 return -E1000_ERR_CONFIG; in e1000_check_for_copper_link_ich8lan()
1698 /* Auto-Neg is enabled. Auto Speed Detection takes care in e1000_check_for_copper_link_ich8lan()
1702 mac->ops.config_collision_dist(hw); in e1000_check_for_copper_link_ich8lan()
1704 /* Configure Flow Control now that Auto-Neg has completed. in e1000_check_for_copper_link_ich8lan()
1706 * settings because we may have had to re-autoneg with a in e1000_check_for_copper_link_ich8lan()
1716 mac->get_link_status = true; in e1000_check_for_copper_link_ich8lan()
1722 struct e1000_hw *hw = &adapter->hw; in e1000_get_variants_ich8lan()
1733 switch (hw->mac.type) { in e1000_get_variants_ich8lan()
1761 if ((adapter->hw.phy.type == e1000_phy_ife) || in e1000_get_variants_ich8lan()
1762 ((adapter->hw.mac.type >= e1000_pch2lan) && in e1000_get_variants_ich8lan()
1764 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; in e1000_get_variants_ich8lan()
1765 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; in e1000_get_variants_ich8lan()
1767 hw->mac.ops.blink_led = NULL; in e1000_get_variants_ich8lan()
1770 if ((adapter->hw.mac.type == e1000_ich8lan) && in e1000_get_variants_ich8lan()
1771 (adapter->hw.phy.type != e1000_phy_ife)) in e1000_get_variants_ich8lan()
1772 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; in e1000_get_variants_ich8lan()
1775 if ((adapter->hw.mac.type == e1000_pch2lan) && in e1000_get_variants_ich8lan()
1777 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; in e1000_get_variants_ich8lan()
1785 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1798 * e1000_release_nvm_ich8lan - Release NVM mutex
1809 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1821 &hw->adapter->state)) { in e1000_acquire_swflag_ich8lan()
1823 return -E1000_ERR_PHY; in e1000_acquire_swflag_ich8lan()
1832 timeout--; in e1000_acquire_swflag_ich8lan()
1837 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1852 timeout--; in e1000_acquire_swflag_ich8lan()
1860 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1866 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_acquire_swflag_ich8lan()
1872 * e1000_release_swflag_ich8lan - Release software control flag
1891 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_release_swflag_ich8lan()
1895 * e1000_check_mng_mode_ich8lan - Checks management mode
1913 * e1000_check_mng_mode_pchlan - Checks management mode
1930 * e1000_rar_set_pch2lan - Set receive address register
1937 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1938 * Use SHRA[0-3] in place of those reserved for ME.
1965 /* RAR[1-6] are owned by manageability. Skip those and program the in e1000_rar_set_pch2lan()
1968 if (index < (u32)(hw->mac.rar_entry_count)) { in e1000_rar_set_pch2lan()
1975 ew32(SHRAL(index - 1), rar_low); in e1000_rar_set_pch2lan()
1977 ew32(SHRAH(index - 1), rar_high); in e1000_rar_set_pch2lan()
1983 if ((er32(SHRAL(index - 1)) == rar_low) && in e1000_rar_set_pch2lan()
1984 (er32(SHRAH(index - 1)) == rar_high)) in e1000_rar_set_pch2lan()
1987 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", in e1000_rar_set_pch2lan()
1988 (index - 1), er32(FWSM)); in e1000_rar_set_pch2lan()
1993 return -E1000_ERR_CONFIG; in e1000_rar_set_pch2lan()
1997 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
2001 * program. SHRA[0-10] are the shared receive address registers
2017 num_entries = hw->mac.rar_entry_count; in e1000_rar_get_count_pch_lpt()
2024 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ in e1000_rar_get_count_pch_lpt()
2033 * e1000_rar_set_pch_lpt - Set receive address registers
2040 * contain the MAC address. SHRA[0-10] are the shared receive address
2069 * it is using - those registers are unavailable for use. in e1000_rar_set_pch_lpt()
2071 if (index < hw->mac.rar_entry_count) { in e1000_rar_set_pch_lpt()
2087 ew32(SHRAL_PCH_LPT(index - 1), rar_low); in e1000_rar_set_pch_lpt()
2089 ew32(SHRAH_PCH_LPT(index - 1), rar_high); in e1000_rar_set_pch_lpt()
2095 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && in e1000_rar_set_pch_lpt()
2096 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) in e1000_rar_set_pch_lpt()
2103 return -E1000_ERR_CONFIG; in e1000_rar_set_pch_lpt()
2107 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2126 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2149 if (hw->phy.type == e1000_phy_i217) { in e1000_write_smbus_addr()
2151 if (freq--) { in e1000_write_smbus_addr()
2156 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); in e1000_write_smbus_addr()
2166 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2174 struct e1000_phy_info *phy = &hw->phy; in e1000_sw_lcd_config_ich8lan()
2185 switch (hw->mac.type) { in e1000_sw_lcd_config_ich8lan()
2187 if (phy->type != e1000_phy_igp_3) in e1000_sw_lcd_config_ich8lan()
2190 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || in e1000_sw_lcd_config_ich8lan()
2191 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { in e1000_sw_lcd_config_ich8lan()
2213 ret_val = hw->phy.ops.acquire(hw); in e1000_sw_lcd_config_ich8lan()
2225 if ((hw->mac.type < e1000_pch2lan) && in e1000_sw_lcd_config_ich8lan()
2238 if (((hw->mac.type == e1000_pchlan) && in e1000_sw_lcd_config_ich8lan()
2240 (hw->mac.type > e1000_pchlan)) { in e1000_sw_lcd_config_ich8lan()
2287 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
2292 * e1000_k1_gig_workaround_hv - K1 Si workaround
2305 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; in e1000_k1_gig_workaround_hv()
2307 if (hw->mac.type != e1000_pchlan) in e1000_k1_gig_workaround_hv()
2311 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_gig_workaround_hv()
2317 if (hw->phy.type == e1000_phy_82578) { in e1000_k1_gig_workaround_hv()
2333 if (hw->phy.type == e1000_phy_82577) { in e1000_k1_gig_workaround_hv()
2363 hw->phy.ops.release(hw); in e1000_k1_gig_workaround_hv()
2369 * e1000_configure_k1_ich8lan - Configure K1 power state
2376 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2421 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2435 if (hw->mac.type < e1000_pchlan) in e1000_oem_bits_config_ich8lan()
2438 ret_val = hw->phy.ops.acquire(hw); in e1000_oem_bits_config_ich8lan()
2442 if (hw->mac.type == e1000_pchlan) { in e1000_oem_bits_config_ich8lan()
2476 /* Set Restart auto-neg to activate the bits */ in e1000_oem_bits_config_ich8lan()
2477 if ((d0_state || (hw->mac.type != e1000_pchlan)) && in e1000_oem_bits_config_ich8lan()
2478 !hw->phy.ops.check_reset_block(hw)) in e1000_oem_bits_config_ich8lan()
2484 hw->phy.ops.release(hw); in e1000_oem_bits_config_ich8lan()
2490 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2510 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2520 if (hw->mac.type != e1000_pchlan) in e1000_hv_phy_workarounds_ich8lan()
2524 if (hw->phy.type == e1000_phy_82577) { in e1000_hv_phy_workarounds_ich8lan()
2530 if (((hw->phy.type == e1000_phy_82577) && in e1000_hv_phy_workarounds_ich8lan()
2531 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || in e1000_hv_phy_workarounds_ich8lan()
2532 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { in e1000_hv_phy_workarounds_ich8lan()
2544 if (hw->phy.type == e1000_phy_82578) { in e1000_hv_phy_workarounds_ich8lan()
2548 if (hw->phy.revision < 2) { in e1000_hv_phy_workarounds_ich8lan()
2557 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2561 hw->phy.addr = 1; in e1000_hv_phy_workarounds_ich8lan()
2563 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2575 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2588 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2594 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2603 ret_val = hw->phy.ops.acquire(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2611 for (i = 0; i < (hw->mac.rar_entry_count); i++) { in e1000_copy_rx_addrs_to_phy_ich8lan()
2613 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2615 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2619 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2621 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2628 hw->phy.ops.release(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2632 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2644 if (hw->mac.type < e1000_pch2lan) in e1000_lv_jumbo_workaround_ich8lan()
2657 for (i = 0; i < hw->mac.rar_entry_count; i++) { in e1000_lv_jumbo_workaround_ich8lan()
2795 /* re-enable Rx path after enabling/disabling workaround */ in e1000_lv_jumbo_workaround_ich8lan()
2800 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2809 if (hw->mac.type != e1000_pch2lan) in e1000_lv_phy_workarounds_ich8lan()
2817 ret_val = hw->phy.ops.acquire(hw); in e1000_lv_phy_workarounds_ich8lan()
2827 hw->phy.ops.release(hw); in e1000_lv_phy_workarounds_ich8lan()
2833 * e1000_k1_workaround_lv - K1 Si workaround
2844 if (hw->mac.type != e1000_pch2lan) in e1000_k1_workaround_lv()
2858 /* LV 1G/100 Packet drop issue wa */ in e1000_k1_workaround_lv()
2880 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2891 if (hw->mac.type < e1000_pch2lan) in e1000_gate_hw_phy_config_ich8lan()
2905 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2920 } while ((!data) && --loop); in e1000_lan_init_done_ich8lan()
2936 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2944 if (hw->phy.ops.check_reset_block(hw)) in e1000_post_phy_reset_ich8lan()
2950 /* Perform any necessary post-reset workarounds */ in e1000_post_phy_reset_ich8lan()
2951 switch (hw->mac.type) { in e1000_post_phy_reset_ich8lan()
2967 if (hw->mac.type >= e1000_pchlan) { in e1000_post_phy_reset_ich8lan()
2981 if (hw->mac.type == e1000_pch2lan) { in e1000_post_phy_reset_ich8lan()
2982 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_post_phy_reset_ich8lan()
2989 ret_val = hw->phy.ops.acquire(hw); in e1000_post_phy_reset_ich8lan()
2995 hw->phy.ops.release(hw); in e1000_post_phy_reset_ich8lan()
3002 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3013 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ in e1000_phy_hw_reset_ich8lan()
3014 if ((hw->mac.type == e1000_pch2lan) && in e1000_phy_hw_reset_ich8lan()
3026 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3033 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3050 if (!hw->phy.ops.check_reset_block(hw)) in e1000_set_lplu_state_pchlan()
3057 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3071 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_ich8lan()
3076 if (phy->type == e1000_phy_ife) in e1000_set_d0_lplu_state_ich8lan()
3085 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3091 if (hw->mac.type == e1000_ich8lan) in e1000_set_d0_lplu_state_ich8lan()
3106 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3114 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state_ich8lan()
3125 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state_ich8lan()
3143 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3157 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_ich8lan()
3168 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3176 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d3_lplu_state_ich8lan()
3187 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d3_lplu_state_ich8lan()
3199 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in e1000_set_d3_lplu_state_ich8lan()
3200 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in e1000_set_d3_lplu_state_ich8lan()
3201 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in e1000_set_d3_lplu_state_ich8lan()
3205 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3211 if (hw->mac.type == e1000_ich8lan) in e1000_set_d3_lplu_state_ich8lan()
3227 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3237 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_valid_nvm_bank_detect_ich8lan()
3238 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); in e1000_valid_nvm_bank_detect_ich8lan()
3244 switch (hw->mac.type) { in e1000_valid_nvm_bank_detect_ich8lan()
3253 bank1_offset = nvm->flash_bank_size; in e1000_valid_nvm_bank_detect_ich8lan()
3285 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3298 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); in e1000_valid_nvm_bank_detect_ich8lan()
3328 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3333 * e1000_read_nvm_spt - NVM access for SPT
3344 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_spt()
3345 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_spt()
3353 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_spt()
3356 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_spt()
3360 nvm->ops.acquire(hw); in e1000_read_nvm_spt()
3368 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_spt()
3374 if (words - i == 1) { in e1000_read_nvm_spt()
3375 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_spt()
3377 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3379 offset_to_read = act_offset + i - in e1000_read_nvm_spt()
3394 if (!(dev_spec->shadow_ram[offset + i].modified) || in e1000_read_nvm_spt()
3395 !(dev_spec->shadow_ram[offset + i + 1].modified)) { in e1000_read_nvm_spt()
3403 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3405 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3408 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3410 dev_spec->shadow_ram[offset + i + 1].value; in e1000_read_nvm_spt()
3416 nvm->ops.release(hw); in e1000_read_nvm_spt()
3426 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3437 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_ich8lan()
3438 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_ich8lan()
3444 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_ich8lan()
3447 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_ich8lan()
3451 nvm->ops.acquire(hw); in e1000_read_nvm_ich8lan()
3459 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_ich8lan()
3464 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_ich8lan()
3465 data[i] = dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_ich8lan()
3476 nvm->ops.release(hw); in e1000_read_nvm_ich8lan()
3486 * e1000_flash_cycle_init_ich8lan - Initialize flash
3495 s32 ret_val = -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3502 return -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3508 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3527 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3551 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3565 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3578 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3584 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3600 return -E1000_ERR_NVM; in e1000_flash_cycle_ich8lan()
3604 * e1000_read_flash_dword_ich8lan - Read dword from flash
3621 * e1000_read_flash_word_ich8lan - Read word from flash
3639 * e1000_read_flash_byte_ich8lan - Read byte from flash
3655 if (hw->mac.type >= e1000_pch_spt) in e1000_read_flash_byte_ich8lan()
3656 return -E1000_ERR_NVM; in e1000_read_flash_byte_ich8lan()
3669 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3684 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3688 return -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3691 hw->nvm.flash_base_addr); in e1000_read_flash_data_ich8lan()
3702 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_read_flash_data_ich8lan()
3735 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data_ich8lan()
3745 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3759 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3762 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) in e1000_read_flash_data32_ich8lan()
3763 return -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3765 hw->nvm.flash_base_addr); in e1000_read_flash_data32_ich8lan()
3779 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_read_flash_data32_ich8lan()
3810 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data32_ich8lan()
3820 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3831 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_write_nvm_ich8lan()
3832 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_write_nvm_ich8lan()
3835 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_write_nvm_ich8lan()
3838 return -E1000_ERR_NVM; in e1000_write_nvm_ich8lan()
3841 nvm->ops.acquire(hw); in e1000_write_nvm_ich8lan()
3844 dev_spec->shadow_ram[offset + i].modified = true; in e1000_write_nvm_ich8lan()
3845 dev_spec->shadow_ram[offset + i].value = data[i]; in e1000_write_nvm_ich8lan()
3848 nvm->ops.release(hw); in e1000_write_nvm_ich8lan()
3854 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3866 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_spt()
3867 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_spt()
3876 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_spt()
3879 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_spt()
3892 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3898 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3913 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_spt()
3915 dword |= (dev_spec->shadow_ram[i].value & 0xffff); in e1000_update_nvm_checksum_spt()
3917 if (dev_spec->shadow_ram[i + 1].modified) { in e1000_update_nvm_checksum_spt()
3919 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) in e1000_update_nvm_checksum_spt()
3932 if (i == E1000_ICH_NVM_SIG_WORD - 1) in e1000_update_nvm_checksum_spt()
3952 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_spt()
3965 --act_offset; in e1000_update_nvm_checksum_spt()
3978 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; in e1000_update_nvm_checksum_spt()
3992 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_spt()
3993 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_spt()
3997 nvm->ops.release(hw); in e1000_update_nvm_checksum_spt()
4003 nvm->ops.reload(hw); in e1000_update_nvm_checksum_spt()
4015 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4027 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_ich8lan()
4028 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_ich8lan()
4037 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_ich8lan()
4040 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_ich8lan()
4053 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4059 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4066 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_ich8lan()
4067 data = dev_spec->shadow_ram[i].value; in e1000_update_nvm_checksum_ich8lan()
4109 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_ich8lan()
4143 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_ich8lan()
4144 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_ich8lan()
4148 nvm->ops.release(hw); in e1000_update_nvm_checksum_ich8lan()
4154 nvm->ops.reload(hw); in e1000_update_nvm_checksum_ich8lan()
4166 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4185 switch (hw->mac.type) { in e1000_validate_nvm_checksum_ich8lan()
4211 if (hw->mac.type < e1000_pch_tgp) { in e1000_validate_nvm_checksum_ich8lan()
4226 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4229 * To prevent malicious write/erase of the NVM, set it to be read-only
4231 * the flash control registers. The shadow-ram copy of the NVM will
4237 struct e1000_nvm_info *nvm = &hw->nvm; in e1000e_write_protect_nvm_ich8lan()
4242 nvm->ops.acquire(hw); in e1000e_write_protect_nvm_ich8lan()
4246 /* Write-protect GbE Sector of NVM */ in e1000e_write_protect_nvm_ich8lan()
4253 /* Lock down a subset of GbE Flash Control Registers, e.g. in e1000e_write_protect_nvm_ich8lan()
4254 * PR0 to prevent the write-protection from being lifted. in e1000e_write_protect_nvm_ich8lan()
4262 nvm->ops.release(hw); in e1000e_write_protect_nvm_ich8lan()
4266 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4284 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data_ich8lan()
4286 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4289 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4293 hw->nvm.flash_base_addr); in e1000_write_flash_data_ich8lan()
4304 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4310 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_write_flash_data_ich8lan()
4316 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4349 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data_ich8lan()
4358 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4374 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data32_ich8lan()
4376 return -E1000_ERR_NVM; in e1000_write_flash_data32_ich8lan()
4379 hw->nvm.flash_base_addr); in e1000_write_flash_data32_ich8lan()
4390 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4396 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_write_flash_data32_ich8lan()
4403 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4433 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data32_ich8lan()
4442 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4458 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4486 return -E1000_ERR_NVM; in e1000_retry_write_flash_dword_ich8lan()
4492 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4518 return -E1000_ERR_NVM; in e1000_retry_write_flash_byte_ich8lan()
4524 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4533 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_erase_flash_bank_ich8lan()
4537 /* bank size is in 16bit words - adjust to bytes */ in e1000_erase_flash_bank_ich8lan()
4538 u32 flash_bank_size = nvm->flash_bank_size * 2; in e1000_erase_flash_bank_ich8lan()
4576 return -E1000_ERR_NVM; in e1000_erase_flash_bank_ich8lan()
4580 flash_linear_addr = hw->nvm.flash_base_addr; in e1000_erase_flash_bank_ich8lan()
4595 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4602 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4636 * e1000_valid_led_default_ich8lan - Set the default LED settings
4661 * e1000_id_led_init_pchlan - store LED configurations
4675 struct e1000_mac_info *mac = &hw->mac; in e1000_id_led_init_pchlan()
4682 ret_val = hw->nvm.ops.valid_led_default(hw, &data); in e1000_id_led_init_pchlan()
4686 mac->ledctl_default = er32(LEDCTL); in e1000_id_led_init_pchlan()
4687 mac->ledctl_mode1 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4688 mac->ledctl_mode2 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4697 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4698 mac->ledctl_mode1 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4703 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4704 mac->ledctl_mode1 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4714 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4715 mac->ledctl_mode2 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4720 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4721 mac->ledctl_mode2 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4733 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4741 struct e1000_bus_info *bus = &hw->bus; in e1000_get_bus_info_ich8lan()
4746 /* ICH devices are "PCI Express"-ish. They have in e1000_get_bus_info_ich8lan()
4751 if (bus->width == e1000_bus_width_unknown) in e1000_get_bus_info_ich8lan()
4752 bus->width = e1000_bus_width_pcie_x1; in e1000_get_bus_info_ich8lan()
4758 * e1000_reset_hw_ich8lan - Reset the hardware
4766 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_reset_hw_ich8lan()
4771 /* Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_ich8lan()
4776 e_dbg("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_ich8lan()
4792 if (hw->mac.type == e1000_ich8lan) { in e1000_reset_hw_ich8lan()
4799 if (hw->mac.type == e1000_pchlan) { in e1000_reset_hw_ich8lan()
4806 dev_spec->nvm_k1_enabled = true; in e1000_reset_hw_ich8lan()
4808 dev_spec->nvm_k1_enabled = false; in e1000_reset_hw_ich8lan()
4813 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_reset_hw_ich8lan()
4814 /* Full-chip reset requires MAC and PHY reset at the same in e1000_reset_hw_ich8lan()
4821 * non-managed 82579 in e1000_reset_hw_ich8lan()
4823 if ((hw->mac.type == e1000_pch2lan) && in e1000_reset_hw_ich8lan()
4834 if (hw->mac.type == e1000_pch2lan) { in e1000_reset_hw_ich8lan()
4842 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_reset_hw_ich8lan()
4845 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_reset_hw_ich8lan()
4858 if (hw->mac.type == e1000_pchlan) in e1000_reset_hw_ich8lan()
4872 * e1000_init_hw_ich8lan - Initialize the hardware
4876 * - initialize hardware bits
4877 * - initialize LED identification
4878 * - setup receive address registers
4879 * - setup flow control
4880 * - setup transmit descriptors
4881 * - clear statistics
4885 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_ich8lan()
4893 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_ich8lan()
4899 e1000e_init_rx_addrs(hw, mac->rar_entry_count); in e1000_init_hw_ich8lan()
4903 for (i = 0; i < mac->mta_reg_count; i++) in e1000_init_hw_ich8lan()
4910 if (hw->phy.type == e1000_phy_82578) { in e1000_init_hw_ich8lan()
4920 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_ich8lan()
4922 /* Set the transmit descriptor write-back policy for both queues */ in e1000_init_hw_ich8lan()
4939 if (mac->type == e1000_ich8lan) in e1000_init_hw_ich8lan()
4948 if (mac->type >= e1000_pch_tgp) { in e1000_init_hw_ich8lan()
4969 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4982 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ in e1000_initialize_hw_bits_ich8lan()
4983 if (hw->mac.type >= e1000_pchlan) in e1000_initialize_hw_bits_ich8lan()
4999 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5000 reg |= BIT(28) | BIT(29); in e1000_initialize_hw_bits_ich8lan()
5007 reg &= ~BIT(28); in e1000_initialize_hw_bits_ich8lan()
5009 reg |= BIT(28); in e1000_initialize_hw_bits_ich8lan()
5014 if (hw->mac.type == e1000_ich8lan) { in e1000_initialize_hw_bits_ich8lan()
5020 /* work-around descriptor data corruption issue during nfs v2 udp in e1000_initialize_hw_bits_ich8lan()
5029 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5034 if (hw->mac.type >= e1000_pch_lpt) { in e1000_initialize_hw_bits_ich8lan()
5046 * e1000_setup_link_ich8lan - Setup flow control and link settings
5050 * control. Calls the appropriate media-specific link configuration
5059 if (hw->phy.ops.check_reset_block(hw)) in e1000_setup_link_ich8lan()
5066 if (hw->fc.requested_mode == e1000_fc_default) { in e1000_setup_link_ich8lan()
5068 if (hw->mac.type == e1000_pchlan) in e1000_setup_link_ich8lan()
5069 hw->fc.requested_mode = e1000_fc_rx_pause; in e1000_setup_link_ich8lan()
5071 hw->fc.requested_mode = e1000_fc_full; in e1000_setup_link_ich8lan()
5077 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_ich8lan()
5079 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); in e1000_setup_link_ich8lan()
5082 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_ich8lan()
5086 ew32(FCTTV, hw->fc.pause_time); in e1000_setup_link_ich8lan()
5087 if ((hw->phy.type == e1000_phy_82578) || in e1000_setup_link_ich8lan()
5088 (hw->phy.type == e1000_phy_82579) || in e1000_setup_link_ich8lan()
5089 (hw->phy.type == e1000_phy_i217) || in e1000_setup_link_ich8lan()
5090 (hw->phy.type == e1000_phy_82577)) { in e1000_setup_link_ich8lan()
5091 ew32(FCRTV_PCH, hw->fc.refresh_time); in e1000_setup_link_ich8lan()
5094 hw->fc.pause_time); in e1000_setup_link_ich8lan()
5103 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5138 switch (hw->phy.type) { in e1000_setup_copper_link_ich8lan()
5163 switch (hw->phy.mdix) { in e1000_setup_copper_link_ich8lan()
5187 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5212 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5230 if ((hw->mac.type == e1000_ich8lan) && in e1000_get_link_up_info_ich8lan()
5231 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { in e1000_get_link_up_info_ich8lan()
5239 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5242 * Work-around for 82566 Kumeran PCS lock loss:
5244 * speed is gigabit-
5255 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_kmrn_lock_loss_workaround_ich8lan()
5261 if (!dev_spec->kmrn_lock_loss_workaround_enabled) in e1000_kmrn_lock_loss_workaround_ich8lan()
5302 return -E1000_ERR_PHY; in e1000_kmrn_lock_loss_workaround_ich8lan()
5306 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5310 * If ICH8, set the current Kumeran workaround state (enabled - true
5311 * /disabled - false).
5316 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5318 if (hw->mac.type != e1000_ich8lan) { in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5323 dev_spec->kmrn_lock_loss_workaround_enabled = state; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5327 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5330 * Workaround for 82566 power-down on D3 entry:
5332 * 2) write VR power-down enable
5342 if (hw->phy.type != e1000_phy_igp_3) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5356 if (hw->mac.type == e1000_ich8lan) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5359 /* Write VR power-down enable */ in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5378 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5383 * 1) Set Kumeran Near-end loopback
5384 * 2) Clear Kumeran Near-end loopback
5385 * Should only be called for ICH8[m] devices with any 1G Phy.
5392 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) in e1000e_gig_downshift_workaround_ich8lan()
5409 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5424 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_suspend_workarounds_ich8lan()
5431 if (hw->phy.type == e1000_phy_i217) { in e1000_suspend_workarounds_ich8lan()
5432 u16 phy_reg, device_id = hw->adapter->pdev->device; in e1000_suspend_workarounds_ich8lan()
5438 (hw->mac.type >= e1000_pch_spt)) { in e1000_suspend_workarounds_ich8lan()
5444 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5448 if (!dev_spec->eee_disable) { in e1000_suspend_workarounds_ich8lan()
5464 (dev_spec->eee_lp_ability & in e1000_suspend_workarounds_ich8lan()
5466 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { in e1000_suspend_workarounds_ich8lan()
5513 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5518 if (hw->mac.type == e1000_ich8lan) in e1000_suspend_workarounds_ich8lan()
5521 if (hw->mac.type >= e1000_pchlan) { in e1000_suspend_workarounds_ich8lan()
5525 if (hw->mac.type == e1000_pchlan) in e1000_suspend_workarounds_ich8lan()
5528 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5532 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5537 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5540 * During Sx to S0 transitions on non-managed devices or managed devices
5550 if (hw->mac.type < e1000_pch2lan) in e1000_resume_workarounds_pchlan()
5564 if (hw->phy.type == e1000_phy_i217) { in e1000_resume_workarounds_pchlan()
5567 ret_val = hw->phy.ops.acquire(hw); in e1000_resume_workarounds_pchlan()
5600 hw->phy.ops.release(hw); in e1000_resume_workarounds_pchlan()
5605 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5612 if (hw->phy.type == e1000_phy_ife) in e1000_cleanup_led_ich8lan()
5615 ew32(LEDCTL, hw->mac.ledctl_default); in e1000_cleanup_led_ich8lan()
5620 * e1000_led_on_ich8lan - Turn LEDs on
5627 if (hw->phy.type == e1000_phy_ife) in e1000_led_on_ich8lan()
5631 ew32(LEDCTL, hw->mac.ledctl_mode2); in e1000_led_on_ich8lan()
5636 * e1000_led_off_ich8lan - Turn LEDs off
5643 if (hw->phy.type == e1000_phy_ife) in e1000_led_off_ich8lan()
5648 ew32(LEDCTL, hw->mac.ledctl_mode1); in e1000_led_off_ich8lan()
5653 * e1000_setup_led_pchlan - Configures SW controllable LED
5660 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); in e1000_setup_led_pchlan()
5664 * e1000_cleanup_led_pchlan - Restore the default LED operation
5671 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); in e1000_cleanup_led_pchlan()
5675 * e1000_led_on_pchlan - Turn LEDs on
5682 u16 data = (u16)hw->mac.ledctl_mode2; in e1000_led_on_pchlan()
5705 * e1000_led_off_pchlan - Turn LEDs off
5712 u16 data = (u16)hw->mac.ledctl_mode1; in e1000_led_off_pchlan()
5735 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5739 * and configure the PHY through s/w for EEPROM-less parts.
5741 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5743 * to return with error, EEPROM-less silicon would not be able to be reset
5755 if (hw->mac.type >= e1000_ich10lan) { in e1000_get_cfg_done_ich8lan()
5774 e_dbg("PHY Reset Asserted not set - needs delay\n"); in e1000_get_cfg_done_ich8lan()
5777 if (hw->mac.type <= e1000_ich9lan) { in e1000_get_cfg_done_ich8lan()
5779 (hw->phy.type == e1000_phy_igp_3)) { in e1000_get_cfg_done_ich8lan()
5786 ret_val = -E1000_ERR_CONFIG; in e1000_get_cfg_done_ich8lan()
5794 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5803 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_ich8lan()
5804 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_ich8lan()
5809 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5837 if ((hw->phy.type == e1000_phy_82578) || in e1000_clear_hw_cntrs_ich8lan()
5838 (hw->phy.type == e1000_phy_82579) || in e1000_clear_hw_cntrs_ich8lan()
5839 (hw->phy.type == e1000_phy_i217) || in e1000_clear_hw_cntrs_ich8lan()
5840 (hw->phy.type == e1000_phy_82577)) { in e1000_clear_hw_cntrs_ich8lan()
5841 ret_val = hw->phy.ops.acquire(hw); in e1000_clear_hw_cntrs_ich8lan()
5844 ret_val = hw->phy.ops.set_page(hw, in e1000_clear_hw_cntrs_ich8lan()
5848 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5849 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5850 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5851 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5852 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5853 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5854 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5855 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5856 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5857 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5858 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5859 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5860 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5861 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5863 hw->phy.ops.release(hw); in e1000_clear_hw_cntrs_ich8lan()