Lines Matching +full:wakeup +full:- +full:counter
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
11 /* Definitions for power management and wakeup registers */
16 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
20 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
21 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
22 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
23 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
24 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
25 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
238 /* 1000/H is not supported, nor spec-compliant. */
292 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
402 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
403 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
405 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
528 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
650 /* NVM Commands - SPI */
654 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
682 /* PCI/PCI-X/PCI-EX Config space */
686 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
723 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
733 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
763 * 15-5: page
764 * 4-0: register offset
787 /* Page 193 - Port Control Registers */
793 /* Page 194 - KMRN Registers */