Lines Matching +full:no +full:- +full:insert +full:- +full:detect

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
46 #define E1000_CTRL_EXT_IAME		0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
121 #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
183 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
212 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
238 /* 1000/H is not supported, nor spec-compliant. */
267 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
268 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
270 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
271 #define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
292 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
528 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
650 /* NVM Commands - SPI */
654 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
682 /* PCI/PCI-X/PCI-EX Config space */
686 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
723 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
733 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
763  * 15-5: page
764  * 4-0: register offset
787 /* Page 193 - Port Control Registers */
793 /* Page 194 - KMRN Registers */