Lines Matching +full:0 +full:xc80
11 #define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
12 #define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
13 #define HINIC_CSR_FUNC_ATTR2_ADDR 0x8
14 #define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
15 #define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
17 #define HINIC_DMA_ATTR_BASE 0xC80
18 #define HINIC_ELECTION_BASE 0x4200
20 #define HINIC_DMA_ATTR_STRIDE 0x4
24 #define HINIC_PPF_ELECTION_STRIDE 0x4
30 #define HINIC_CSR_API_CMD_BASE 0xF000
32 #define HINIC_CSR_API_CMD_STRIDE 0x100
35 (HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
38 (HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
41 (HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
44 (HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
47 (HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
50 (HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
53 (HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
56 (HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
59 (HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
62 #define HINIC_CSR_MSIX_CTRL_BASE 0x2000
63 #define HINIC_CSR_MSIX_CNT_BASE 0x2004
65 #define HINIC_CSR_MSIX_STRIDE 0x8
74 #define HINIC_AEQ_MTT_OFF_BASE_ADDR 0x200
75 #define HINIC_CEQ_MTT_OFF_BASE_ADDR 0x400
77 #define HINIC_EQ_MTT_OFF_STRIDE 0x40
103 #define HINIC_AEQ_CTRL_0_ADDR_BASE 0xE00
104 #define HINIC_AEQ_CTRL_1_ADDR_BASE 0xE04
105 #define HINIC_AEQ_CONS_IDX_ADDR_BASE 0xE08
106 #define HINIC_AEQ_PROD_IDX_ADDR_BASE 0xE0C
108 #define HINIC_CEQ_CTRL_0_ADDR_BASE 0x1000
109 #define HINIC_CEQ_CTRL_1_ADDR_BASE 0x1004
110 #define HINIC_CEQ_CONS_IDX_ADDR_BASE 0x1008
111 #define HINIC_CEQ_PROD_IDX_ADDR_BASE 0x100C
113 #define HINIC_EQ_OFF_STRIDE 0x80