Lines Matching +full:hardware +full:- +full:fifo

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
58 #define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
59 #define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
60 #define FEC_R_FSTART		0x150 /* FIFO receive start reg */
70 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
71 #define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
72 #define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
73 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
119 #define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
145 #define IEEE_R_MACERR		0x2d8 /* Receive FIFO overflow count */
163 #define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
164 #define FEC_R_FSTART		0x090 /* FIFO receive start reg */
165 #define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
166 #define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
183 #define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
353 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
354 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
410 /* Controller is ENET-MAC */
420 /* Controller has hardware checksum support */
422 /* Controller has hardware vlan support */
430  * frames not being transmitted until there is a 0-to-1 transition on
437  * - Two class indicators on receive with configurable priority
438  * - Two class indicators and line speed timer on transmit allowing
440  * - Additional DMA registers provisioned to allow managing up to 3
445  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
453  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
455  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
472  * those FIFO receive registers are resolved in other platforms.
476 /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
483  * frequency when the RNCTL register is cleared by hardware reset.
511 /* Not all FEC hardware block MDIOs support accesses in C45 mode.
581 	/* rx queue number, in the range 0-7 */
600 	/* Hardware registers of the FEC device */
617 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */