Lines Matching +full:0 +full:xf000000

10 #define NPS_ENET_NAPI_POLL_WEIGHT		0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH		0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR	0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG		0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG		0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN		0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN		0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH		0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN		0x3FFC
20 #define NPS_ENET_DISABLE			0
23 #define NPS_ENET_REG_TX_CTL		0x800
24 #define NPS_ENET_REG_TX_BUF		0x808
25 #define NPS_ENET_REG_RX_CTL		0x810
26 #define NPS_ENET_REG_RX_BUF		0x818
27 #define NPS_ENET_REG_BUF_INT_ENABLE	0x8C0
28 #define NPS_ENET_REG_GE_MAC_CFG_0	0x1000
29 #define NPS_ENET_REG_GE_MAC_CFG_1	0x1004
30 #define NPS_ENET_REG_GE_MAC_CFG_2	0x1008
31 #define NPS_ENET_REG_GE_MAC_CFG_3	0x100C
32 #define NPS_ENET_REG_GE_RST		0x1400
33 #define NPS_ENET_REG_PHASE_FIFO_CTL	0x1404
36 #define TX_CTL_NT_MASK 0x7FF
37 #define TX_CTL_NT_SHIFT 0
38 #define TX_CTL_ET_MASK 0x4000
40 #define TX_CTL_CT_MASK 0x8000
44 #define RX_CTL_NR_MASK 0x7FF
45 #define RX_CTL_NR_SHIFT 0
46 #define RX_CTL_CRC_MASK 0x2000
48 #define RX_CTL_ER_MASK 0x4000
50 #define RX_CTL_CR_MASK 0x8000
54 #define RX_RDY_MASK 0x1
55 #define RX_RDY_SHIFT 0
56 #define TX_DONE_MASK 0x2
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
60 #define CFG_0_RX_EN_MASK 0x1
61 #define CFG_0_RX_EN_SHIFT 0
62 #define CFG_0_TX_EN_MASK 0x2
64 #define CFG_0_TX_FC_EN_MASK 0x4
66 #define CFG_0_TX_PAD_EN_MASK 0x8
68 #define CFG_0_TX_CRC_EN_MASK 0x10
70 #define CFG_0_RX_FC_EN_MASK 0x20
72 #define CFG_0_RX_CRC_STRIP_MASK 0x40
74 #define CFG_0_RX_CRC_IGNORE_MASK 0x80
76 #define CFG_0_RX_LENGTH_CHECK_EN_MASK 0x100
78 #define CFG_0_TX_FC_RETR_MASK 0xE00
80 #define CFG_0_RX_IFG_MASK 0xF000
82 #define CFG_0_TX_IFG_MASK 0x3F0000
84 #define CFG_0_RX_PR_CHECK_EN_MASK 0x400000
86 #define CFG_0_NIB_MODE_MASK 0x800000
88 #define CFG_0_TX_IFG_NIB_MASK 0xF000000
90 #define CFG_0_TX_PR_LEN_MASK 0xF0000000
94 #define CFG_1_OCTET_0_MASK 0x000000FF
95 #define CFG_1_OCTET_0_SHIFT 0
96 #define CFG_1_OCTET_1_MASK 0x0000FF00
98 #define CFG_1_OCTET_2_MASK 0x00FF0000
100 #define CFG_1_OCTET_3_MASK 0xFF000000
104 #define CFG_2_OCTET_4_MASK 0x000000FF
105 #define CFG_2_OCTET_4_SHIFT 0
106 #define CFG_2_OCTET_5_MASK 0x0000FF00
108 #define CFG_2_DISK_MC_MASK 0x00100000
110 #define CFG_2_DISK_BC_MASK 0x00200000
112 #define CFG_2_DISK_DA_MASK 0x00400000
114 #define CFG_2_STAT_EN_MASK 0x3000000
116 #define CFG_2_TRANSMIT_FLUSH_EN_MASK 0x80000000
120 #define CFG_3_TM_HD_MODE_MASK 0x1
121 #define CFG_3_TM_HD_MODE_SHIFT 0
122 #define CFG_3_RX_CBFC_EN_MASK 0x2
124 #define CFG_3_RX_CBFC_REDIR_EN_MASK 0x4
126 #define CFG_3_REDIRECT_CBFC_SEL_MASK 0x18
128 #define CFG_3_CF_DROP_MASK 0x20
130 #define CFG_3_CF_TIMEOUT_MASK 0x3C0
132 #define CFG_3_RX_IFG_TH_MASK 0x7C00
134 #define CFG_3_TX_CBFC_EN_MASK 0x8000
136 #define CFG_3_MAX_LEN_MASK 0x3FFF0000
138 #define CFG_3_EXT_OOB_CBFC_SEL_MASK 0xC0000000
142 #define RST_SPCS_MASK 0x1
143 #define RST_SPCS_SHIFT 0
144 #define RST_GMAC_0_MASK 0x100
148 #define PHASE_FIFO_CTL_RST_MASK 0x1
149 #define PHASE_FIFO_CTL_RST_SHIFT 0
150 #define PHASE_FIFO_CTL_INIT_MASK 0x2