245 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)  in ethoc_write()  function
265 	ethoc_write(dev, offset + 0, bd->stat);  in ethoc_write_bd()
266 	ethoc_write(dev, offset + 4, bd->addr);  in ethoc_write_bd()
273 	ethoc_write(dev, INT_MASK, imask);  in ethoc_enable_irq()
280 	ethoc_write(dev, INT_MASK, imask);  in ethoc_disable_irq()
285 	ethoc_write(dev, INT_SOURCE, mask);  in ethoc_ack_irq()
292 	ethoc_write(dev, MODER, mode);  in ethoc_enable_rx_and_tx()
299 	ethoc_write(dev, MODER, mode);  in ethoc_disable_rx_and_tx()
312 	ethoc_write(dev, TX_BD_NUM, dev->num_tx);  in ethoc_init_ring()
359 	ethoc_write(dev, MODER, mode);  in ethoc_reset()
364 	ethoc_write(dev, MODER, mode);  in ethoc_reset()
365 	ethoc_write(dev, IPGT, 0x15);  in ethoc_reset()
630 	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));  in ethoc_mdio_read()
631 	ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);  in ethoc_mdio_read()
638 			ethoc_write(priv, MIICOMMAND, 0);  in ethoc_mdio_read()
652 	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));  in ethoc_mdio_write()
653 	ethoc_write(priv, MIITX_DATA, val);  in ethoc_mdio_write()
654 	ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);  in ethoc_mdio_write()
660 			ethoc_write(priv, MIICOMMAND, 0);  in ethoc_mdio_write()
694 	ethoc_write(priv, MODER, mode);  in ethoc_mdio_poll()
808 	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |  in ethoc_do_set_mac_address()
810 	ethoc_write(priv, MAC_ADDR1, (mac[0] <<  8) | (mac[1] <<  0));  in ethoc_do_set_mac_address()
849 	ethoc_write(priv, MODER, mode);  in ethoc_set_multicast_list()
863 	ethoc_write(priv, ETH_HASH0, hash[0]);  in ethoc_set_multicast_list()
864 	ethoc_write(priv, ETH_HASH1, hash[1]);  in ethoc_set_multicast_list()
1189 		ethoc_write(priv, MIIMODER,  in ethoc_probe()