35 #define uw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
243 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);  in srom_clk_write()
245 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);  in srom_clk_write()
247 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);  in srom_clk_write()
374 		uw32(DCR0, 0x10000);	//Diagnosis mode  in uli526x_init_one()
375 		uw32(DCR13, 0x1c0);	//Reset dianostic pointer port  in uli526x_init_one()
376 		uw32(DCR14, 0);		//Clear reset port  in uli526x_init_one()
377 		uw32(DCR14, 0x10);	//Reset ID Table pointer  in uli526x_init_one()
378 		uw32(DCR14, 0);		//Clear reset port  in uli526x_init_one()
379 		uw32(DCR13, 0);		//Clear CR13  in uli526x_init_one()
380 		uw32(DCR13, 0x1b0);	//Select ID Table access port  in uli526x_init_one()
385 		uw32(DCR13, 0);		//Clear CR13  in uli526x_init_one()
386 		uw32(DCR0, 0);		//Clear CR0  in uli526x_init_one()
513 	uw32(DCR0, ULI526X_RESET);	/* RESET MAC */  in uli526x_init()
515 	uw32(DCR0, db->cr0_data);  in uli526x_init()
566 	uw32(DCR7, db->cr7_data);  in uli526x_init()
569 	uw32(DCR15, db->cr15_data);  in uli526x_init()
612 	uw32(DCR7, 0);  in uli526x_start_xmit()
626 		uw32(DCR1, 0x1);			/* Issue Tx polling */  in uli526x_start_xmit()
636 	uw32(DCR7, db->cr7_data);  in uli526x_start_xmit()
662 	uw32(DCR0, ULI526X_RESET);  in uli526x_stop()
689 	uw32(DCR7, 0);  in uli526x_interrupt()
693 	uw32(DCR5, db->cr5_data);  in uli526x_interrupt()
696 		uw32(DCR7, db->cr7_data);  in uli526x_interrupt()
724 	uw32(DCR7, db->cr7_data);  in uli526x_interrupt()
1040 		uw32(DCR1, 0x1);   // Tx polling again  in uli526x_timer()
1136 	uw32(DCR7, 0);				/* Disable Interrupt */  in uli526x_reset_prepare()
1137 	uw32(DCR5, ur32(DCR5));  in uli526x_reset_prepare()
1277 	uw32(DCR4, db->first_tx_desc_dma);	/* TX DESC address */  in uli526x_descriptor_init()
1284 	uw32(DCR3, db->first_rx_desc_dma);	/* RX DESC address */  in uli526x_descriptor_init()
1327 	uw32(DCR6, cr6_data);  in update_cr6()
1393 		uw32(DCR1, 0x1);	/* Issue Tx polling */  in send_filter_frame()
1441 	uw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1442 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1455 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1458 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);  in read_srom_word()
1462 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1466 	uw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1673 	uw32(DCR10, cr10_value);  in phy_readby_cr10()
1691 	uw32(DCR10, cr10_value);  in phy_writeby_cr10()
1702 	uw32(DCR9, data);		/* MII Clock Low */  in phy_write_1bit()
1704 	uw32(DCR9, data | MDCLKH);	/* MII Clock High */  in phy_write_1bit()
1706 	uw32(DCR9, data);		/* MII Clock Low */  in phy_write_1bit()
1720 	uw32(DCR9, 0x50000);  in phy_read_1bit()
1723 	uw32(DCR9, 0x40000);  in phy_read_1bit()