Lines Matching +full:0 +full:xb00

11 #define FPGA_PCIX_ADDR_VERSION               0xA08
12 #define FPGA_PCIX_ADDR_STAT                  0xA0C
15 #define FPGA_PCIX_INTERRUPT_SGE_ERROR        0x1
16 #define FPGA_PCIX_INTERRUPT_SGE_DATA         0x2
17 #define FPGA_PCIX_INTERRUPT_TP               0x4
18 #define FPGA_PCIX_INTERRUPT_MC3              0x8
19 #define FPGA_PCIX_INTERRUPT_GMAC             0x10
20 #define FPGA_PCIX_INTERRUPT_PCIX             0x20
23 #define FPGA_TP_ADDR_INTERRUPT_ENABLE        0xA10
24 #define FPGA_TP_ADDR_INTERRUPT_CAUSE         0xA14
25 #define FPGA_TP_ADDR_VERSION                 0xA18
28 #define FPGA_TP_INTERRUPT_MC4                0x1
29 #define FPGA_TP_INTERRUPT_MC5                0x2
34 #define FPGA_MC3_REG_INTRENABLE              0xA20
35 #define FPGA_MC3_REG_INTRCAUSE               0xA24
36 #define FPGA_MC3_REG_VERSION                 0xA28
41 #define FPGA_GMAC_ADDR_INTERRUPT_ENABLE      0xA30
42 #define FPGA_GMAC_ADDR_INTERRUPT_CAUSE       0xA34
43 #define FPGA_GMAC_ADDR_VERSION               0xA38
46 #define FPGA_GMAC_INTERRUPT_PORT0            0x1
47 #define FPGA_GMAC_INTERRUPT_PORT1            0x2
48 #define FPGA_GMAC_INTERRUPT_PORT2            0x4
49 #define FPGA_GMAC_INTERRUPT_PORT3            0x8
52 #define A_MI0_CLK 0xb00
54 #define S_MI0_CLK_DIV    0
55 #define M_MI0_CLK_DIV    0xff
60 #define M_MI0_CLK_CNT    0xff
64 #define A_MI0_CSR 0xb04
66 #define S_MI0_CSR_POLL    0
86 #define A_MI0_ADDR 0xb08
88 #define S_MI0_PHY_REG_ADDR    0
89 #define M_MI0_PHY_REG_ADDR    0x1f
94 #define M_MI0_PHY_ADDR    0x1f
98 #define A_MI0_DATA_EXT 0xb0c
99 #define A_MI0_DATA_INT 0xb10
102 #define A_GMAC_MACID_LO	0x28
103 #define A_GMAC_MACID_HI	0x2c
104 #define A_GMAC_CSR	0x30
106 #define S_INTERFACE    0
107 #define M_INTERFACE    0x3
124 #define M_MAC_SPEED    0x3
180 #define A_GMAC_IFS 0x34
182 #define S_MAC_IFS2    0
183 #define M_MAC_IFS2    0x3f
188 #define M_MAC_IFS1    0x7f
192 #define A_GMAC_JUMBO_FRAME_LEN 0x38
193 #define A_GMAC_LNK_DLY 0x3c
194 #define A_GMAC_PAUSETIME 0x40
195 #define A_GMAC_MCAST_LO 0x44
196 #define A_GMAC_MCAST_HI 0x48
197 #define A_GMAC_MCAST_MASK_LO 0x4c
198 #define A_GMAC_MCAST_MASK_HI 0x50
199 #define A_GMAC_RMT_CNT 0x54
200 #define A_GMAC_RMT_DATA 0x58
201 #define A_GMAC_BACKOFF_SEED 0x5c
202 #define A_GMAC_TXF_THRES 0x60
204 #define S_TXF_READ_THRESHOLD    0
205 #define M_TXF_READ_THRESHOLD    0xff
210 #define M_TXF_WRITE_THRESHOLD    0xff
214 #define MAC_REG_BASE 0x600