1 // SPDX-License-Identifier: GPL-2.0-only
67 	u64  cfg;  in xcv_init_hw()  local
70 	cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_init_hw()
71 	cfg &= ~DLL_RESET;  in xcv_init_hw()
72 	writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_init_hw()
75 	cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_init_hw()
76 	cfg &= ~CLK_RESET;  in xcv_init_hw()
77 	writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_init_hw()
81 	/* Configure DLL - enable or bypass  in xcv_init_hw()
84 	cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL);  in xcv_init_hw()
85 	cfg &= ~0xFF03;  in xcv_init_hw()
86 	cfg |= CLKRX_BYP;  in xcv_init_hw()
87 	writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL);  in xcv_init_hw()
92 	cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_init_hw()
93 	cfg |= COMP_EN;  in xcv_init_hw()
94 	writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_init_hw()
95 	readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_init_hw()
100 	cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_init_hw()
101 	cfg |= PORT_EN;  in xcv_init_hw()
102 	writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_init_hw()
104 	cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_init_hw()
105 	cfg |= CLK_RESET;  in xcv_init_hw()
106 	writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_init_hw()
112 	u64  cfg;  in xcv_setup_link()  local
127 		cfg = readq_relaxed(xcv->reg_base + XCV_CTL);  in xcv_setup_link()
128 		cfg &= ~0x03;  in xcv_setup_link()
129 		cfg |= speed;  in xcv_setup_link()
130 		writeq_relaxed(cfg, xcv->reg_base + XCV_CTL);  in xcv_setup_link()
133 		cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_setup_link()
134 		cfg |= TX_DATA_RESET | RX_DATA_RESET;  in xcv_setup_link()
135 		writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_setup_link()
138 		cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_setup_link()
139 		cfg |= TX_PKT_RESET | RX_PKT_RESET;  in xcv_setup_link()
140 		writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_setup_link()
143 		writeq_relaxed(0x01, xcv->reg_base + XCV_BATCH_CRD_RET);  in xcv_setup_link()
146 		cfg = readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_setup_link()
147 		cfg &= ~(TX_PKT_RESET | RX_PKT_RESET);  in xcv_setup_link()
148 		writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);  in xcv_setup_link()
149 		readq_relaxed(xcv->reg_base + XCV_RESET);  in xcv_setup_link()
157 	struct device *dev = &pdev->dev;  in xcv_probe()
161 		return -ENOMEM;  in xcv_probe()
162 	xcv->pdev = pdev;  in xcv_probe()
179 	xcv->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);  in xcv_probe()
180 	if (!xcv->reg_base) {  in xcv_probe()
182 		err = -ENOMEM;  in xcv_probe()
200 	struct device *dev = &pdev->dev;  in xcv_remove()