Lines Matching +full:0 +full:x658
10 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
11 #define PCI_DEVICE_ID_THUNDER_RGX 0xA054
14 #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126
15 #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226
16 #define PCI_SUBSYS_DEVID_81XX_RGX 0xA254
17 #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326
27 #define DEFAULT_PAUSE_TIME 0xFFFF
29 #define BGX_ID_MASK 0x3
30 #define LMAC_ID_MASK 0x3
35 #define BGX_CMRX_CFG 0x00
39 #define BGX_CMR_GLOBAL_CFG 0x08
41 #define BGX_CMRX_RX_ID_MAP 0x60
42 #define BGX_CMRX_RX_STAT0 0x70
43 #define BGX_CMRX_RX_STAT1 0x78
44 #define BGX_CMRX_RX_STAT2 0x80
45 #define BGX_CMRX_RX_STAT3 0x88
46 #define BGX_CMRX_RX_STAT4 0x90
47 #define BGX_CMRX_RX_STAT5 0x98
48 #define BGX_CMRX_RX_STAT6 0xA0
49 #define BGX_CMRX_RX_STAT7 0xA8
50 #define BGX_CMRX_RX_STAT8 0xB0
51 #define BGX_CMRX_RX_STAT9 0xB8
52 #define BGX_CMRX_RX_STAT10 0xC0
53 #define BGX_CMRX_RX_BP_DROP 0xC8
54 #define BGX_CMRX_RX_DMAC_CTL 0x0E8
55 #define BGX_CMRX_RX_FIFO_LEN 0x108
56 #define BGX_CMR_RX_DMACX_CAM 0x200
60 #define BGX_CMR_RX_STEERING 0x300
62 #define BGX_CMR_CHAN_MSK_AND 0x450
63 #define BGX_CMR_BIST_STATUS 0x460
64 #define BGX_CMR_RX_LMACS 0x468
65 #define BGX_CMRX_TX_FIFO_LEN 0x518
66 #define BGX_CMRX_TX_STAT0 0x600
67 #define BGX_CMRX_TX_STAT1 0x608
68 #define BGX_CMRX_TX_STAT2 0x610
69 #define BGX_CMRX_TX_STAT3 0x618
70 #define BGX_CMRX_TX_STAT4 0x620
71 #define BGX_CMRX_TX_STAT5 0x628
72 #define BGX_CMRX_TX_STAT6 0x630
73 #define BGX_CMRX_TX_STAT7 0x638
74 #define BGX_CMRX_TX_STAT8 0x640
75 #define BGX_CMRX_TX_STAT9 0x648
76 #define BGX_CMRX_TX_STAT10 0x650
77 #define BGX_CMRX_TX_STAT11 0x658
78 #define BGX_CMRX_TX_STAT12 0x660
79 #define BGX_CMRX_TX_STAT13 0x668
80 #define BGX_CMRX_TX_STAT14 0x670
81 #define BGX_CMRX_TX_STAT15 0x678
82 #define BGX_CMRX_TX_STAT16 0x680
83 #define BGX_CMRX_TX_STAT17 0x688
84 #define BGX_CMR_TX_LMACS 0x1000
86 #define BGX_SPUX_CONTROL1 0x10000
90 #define BGX_SPUX_STATUS1 0x10008
92 #define BGX_SPUX_STATUS2 0x10020
94 #define BGX_SPUX_BX_STATUS 0x10028
96 #define BGX_SPUX_BR_STATUS1 0x10030
97 #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0)
99 #define BGX_SPUX_BR_PMD_CRTL 0x10068
101 #define BGX_SPUX_BR_PMD_LP_CUP 0x10078
102 #define BGX_SPUX_BR_PMD_LD_CUP 0x10088
103 #define BGX_SPUX_BR_PMD_LD_REP 0x10090
104 #define BGX_SPUX_FEC_CONTROL 0x100A0
105 #define SPU_FEC_CTL_FEC_EN BIT_ULL(0)
107 #define BGX_SPUX_AN_CONTROL 0x100C8
110 #define BGX_SPUX_AN_ADV 0x100D8
111 #define BGX_SPUX_MISC_CONTROL 0x10218
114 #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */
115 #define BGX_SPUX_INT_W1S 0x10228
116 #define BGX_SPUX_INT_ENA_W1C 0x10230
117 #define BGX_SPUX_INT_ENA_W1S 0x10238
118 #define BGX_SPU_DBG_CONTROL 0x10300
122 #define BGX_SMUX_RX_INT 0x20000
123 #define BGX_SMUX_RX_FRM_CTL 0x20020
125 #define BGX_SMUX_RX_JABBER 0x20030
126 #define BGX_SMUX_RX_CTL 0x20048
127 #define SMU_RX_CTL_STATUS (3ull << 0)
128 #define BGX_SMUX_TX_APPEND 0x20100
130 #define BGX_SMUX_TX_PAUSE_PKT_TIME 0x20110
131 #define BGX_SMUX_TX_MIN_PKT 0x20118
132 #define BGX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120
133 #define BGX_SMUX_TX_PAUSE_ZERO 0x20138
134 #define BGX_SMUX_TX_INT 0x20140
135 #define BGX_SMUX_TX_CTL 0x20178
136 #define SMU_TX_CTL_DIC_EN BIT_ULL(0)
139 #define BGX_SMUX_TX_THRESH 0x20180
140 #define BGX_SMUX_CTL 0x20200
141 #define SMU_CTL_RX_IDLE BIT_ULL(0)
143 #define BGX_SMUX_CBFC_CTL 0x20218
144 #define RX_EN BIT_ULL(0)
149 #define BGX_GMP_PCS_MRX_CTL 0x30000
155 #define BGX_GMP_PCS_MRX_STATUS 0x30008
158 #define BGX_GMP_PCS_ANX_ADV 0x30010
159 #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020
160 #define BGX_GMP_PCS_LINKX_TIMER 0x30040
161 #define PCS_LINKX_TIMER_COUNT 0x1E84
162 #define BGX_GMP_PCS_SGM_AN_ADV 0x30068
163 #define BGX_GMP_PCS_MISCX_CTL 0x30078
167 #define PCS_MISC_CTL_SAMP_PT_MASK 0x7Full
168 #define BGX_GMP_GMI_PRTX_CFG 0x38020
175 #define BGX_GMP_GMI_RXX_FRM_CTL 0x38028
176 #define BGX_GMP_GMI_RXX_JABBER 0x38038
177 #define BGX_GMP_GMI_TXX_THRESH 0x38210
178 #define BGX_GMP_GMI_TXX_APPEND 0x38218
179 #define BGX_GMP_GMI_TXX_SLOT 0x38220
180 #define BGX_GMP_GMI_TXX_BURST 0x38228
181 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240
182 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300
183 #define BGX_GMP_GMI_TXX_INT 0x38500
184 #define BGX_GMP_GMI_TXX_INT_W1S 0x38508
185 #define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510
186 #define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518
191 #define GMI_TXX_INT_UNDFLW BIT_ULL(0)
193 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */
194 #define BGX_MSIX_VEC_0_29_CTL 0x400008
195 #define BGX_MSIX_PBA_0 0x4F0000
202 #define CMRX_INT 0
212 #define LMAC_INTR_LINK_UP BIT(0)
215 #define BGX_XCAST_BCAST_ACCEPT BIT(0)
248 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */