Lines Matching +full:128 +full:k
14 #define MAX_QUEUE_SET 128
34 #define RBDR_SIZE0 0ULL /* 8K entries */
35 #define RBDR_SIZE1 1ULL /* 16K entries */
36 #define RBDR_SIZE2 2ULL /* 32K entries */
37 #define RBDR_SIZE3 3ULL /* 64K entries */
38 #define RBDR_SIZE4 4ULL /* 126K entries */
39 #define RBDR_SIZE5 5ULL /* 256K entries */
40 #define RBDR_SIZE6 6ULL /* 512K entries */
42 #define SND_QUEUE_SIZE0 0ULL /* 1K entries */
43 #define SND_QUEUE_SIZE1 1ULL /* 2K entries */
44 #define SND_QUEUE_SIZE2 2ULL /* 4K entries */
45 #define SND_QUEUE_SIZE3 3ULL /* 8K entries */
46 #define SND_QUEUE_SIZE4 4ULL /* 16K entries */
47 #define SND_QUEUE_SIZE5 5ULL /* 32K entries */
48 #define SND_QUEUE_SIZE6 6ULL /* 64K entries */
50 #define CMP_QUEUE_SIZE0 0ULL /* 1K entries */
51 #define CMP_QUEUE_SIZE1 1ULL /* 2K entries */
52 #define CMP_QUEUE_SIZE2 2ULL /* 4K entries */
53 #define CMP_QUEUE_SIZE3 3ULL /* 8K entries */
54 #define CMP_QUEUE_SIZE4 4ULL /* 16K entries */
55 #define CMP_QUEUE_SIZE5 5ULL /* 32K entries */
56 #define CMP_QUEUE_SIZE6 6ULL /* 64K entries */
89 #define DMA_BUFFER_LEN 1536 /* In multiples of 128bytes */
98 * eg: For CQ of size 4K, and for pass/drop levels of 160/144
108 * eg: For RBDR of size 8K, and for pass/drop levels of 4/0
124 #define NICVF_SQ_BASE_ALIGN_BYTES 128 /* 7 bits */