Lines Matching +full:mask +full:- +full:reset
7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
33 dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n"); in lio_cn6xxx_soft_reset()
45 dev_err(&oct->pci_dev->dev, "Soft reset failed\n"); in lio_cn6xxx_soft_reset()
49 dev_dbg(&oct->pci_dev->dev, "Reset completed\n"); in lio_cn6xxx_soft_reset()
59 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_enable_error_reporting()
61 dev_err(&oct->pci_dev->dev, "PCI-E Link error detected: 0x%08x\n", in lio_cn6xxx_enable_error_reporting()
67 dev_dbg(&oct->pci_dev->dev, "Enabling PCI-E error reporting..\n"); in lio_cn6xxx_enable_error_reporting()
68 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_enable_error_reporting()
78 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mps()
85 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_setup_pcie_mps()
89 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
91 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
101 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mrrs()
108 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_setup_pcie_mrrs()
112 r64 = octeon_read_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
114 octeon_write_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port), r64); in lio_cn6xxx_setup_pcie_mrrs()
117 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
119 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
157 /* Select Round-Robin Arb, ES, RO, NS for Input Queues */ in lio_cn6xxx_setup_global_input_regs()
161 /* Instruction Read Size - Max 4 instructions per PCIE Read */ in lio_cn6xxx_setup_global_input_regs()
167 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_input_regs()
174 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn66xx_setup_pkt_ctl_regs()
179 if (CFG_GET_OQ_MAX_Q(cn6xxx->conf) <= 4) in lio_cn66xx_setup_pkt_ctl_regs()
185 if (CFG_GET_IS_SLI_BP_ON(cn6xxx->conf)) in lio_cn66xx_setup_pkt_ctl_regs()
188 /* Disable per-port backpressure. */ in lio_cn66xx_setup_pkt_ctl_regs()
196 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_setup_global_output_regs()
198 /* / Select PCI-E Port for all Output queues */ in lio_cn6xxx_setup_global_output_regs()
200 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_output_regs()
202 if (CFG_GET_IS_SLI_BP_ON(cn6xxx->conf)) { in lio_cn6xxx_setup_global_output_regs()
217 /* No Relaxed Ordering, No Snoop, 64-bit swap for Output in lio_cn6xxx_setup_global_output_regs()
223 /* / ENDIAN_SPECIFIC CHANGES - 0 works for LE. */ in lio_cn6xxx_setup_global_output_regs()
231 /* / No Relaxed Ordering, No Snoop, 64-bit swap for Output Queue Data */ in lio_cn6xxx_setup_global_output_regs()
239 (u32)CFG_GET_OQ_INTR_PKT(cn6xxx->conf)); in lio_cn6xxx_setup_global_output_regs()
242 CFG_GET_OQ_INTR_TIME(cn6xxx->conf)); in lio_cn6xxx_setup_global_output_regs()
266 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in lio_cn6xxx_setup_iq_regs()
272 iq->base_addr_dma); in lio_cn6xxx_setup_iq_regs()
273 octeon_write_csr(oct, CN6XXX_SLI_IQ_SIZE(iq_no), iq->max_count); in lio_cn6xxx_setup_iq_regs()
278 iq->doorbell_reg = oct->mmio[0].hw_addr + CN6XXX_SLI_IQ_DOORBELL(iq_no); in lio_cn6xxx_setup_iq_regs()
279 iq->inst_cnt_reg = oct->mmio[0].hw_addr in lio_cn6xxx_setup_iq_regs()
281 dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n", in lio_cn6xxx_setup_iq_regs()
282 iq_no, iq->doorbell_reg, iq->inst_cnt_reg); in lio_cn6xxx_setup_iq_regs()
287 iq->reset_instr_cnt = readl(iq->inst_cnt_reg); in lio_cn6xxx_setup_iq_regs()
294 /* Backpressure for this queue - WMARK set to all F's. This effectively in lio_cn66xx_setup_iq_regs()
304 struct octeon_droq *droq = oct->droq[oq_no]; in lio_cn6xxx_setup_oq_regs()
307 droq->desc_ring_dma); in lio_cn6xxx_setup_oq_regs()
308 octeon_write_csr(oct, CN6XXX_SLI_OQ_SIZE(oq_no), droq->max_count); in lio_cn6xxx_setup_oq_regs()
311 droq->buffer_size); in lio_cn6xxx_setup_oq_regs()
314 droq->pkts_sent_reg = in lio_cn6xxx_setup_oq_regs()
315 oct->mmio[0].hw_addr + CN6XXX_SLI_OQ_PKTS_SENT(oq_no); in lio_cn6xxx_setup_oq_regs()
316 droq->pkts_credit_reg = in lio_cn6xxx_setup_oq_regs()
317 oct->mmio[0].hw_addr + CN6XXX_SLI_OQ_PKTS_CREDIT(oq_no); in lio_cn6xxx_setup_oq_regs()
332 u32 mask; in lio_cn6xxx_enable_io_queues() local
334 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE); in lio_cn6xxx_enable_io_queues()
335 mask |= oct->io_qmask.iq64B; in lio_cn6xxx_enable_io_queues()
336 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE, mask); in lio_cn6xxx_enable_io_queues()
338 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_enable_io_queues()
339 mask |= oct->io_qmask.iq; in lio_cn6xxx_enable_io_queues()
340 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); in lio_cn6xxx_enable_io_queues()
342 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_enable_io_queues()
343 mask |= oct->io_qmask.oq; in lio_cn6xxx_enable_io_queues()
344 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); in lio_cn6xxx_enable_io_queues()
352 u32 mask, loop = HZ; in lio_cn6xxx_disable_io_queues() local
355 /* Reset the Enable bits for Input Queues. */ in lio_cn6xxx_disable_io_queues()
356 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_disable_io_queues()
357 mask ^= oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
358 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); in lio_cn6xxx_disable_io_queues()
360 /* Wait until hardware indicates that the queues are out of reset. */ in lio_cn6xxx_disable_io_queues()
361 mask = (u32)oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
363 while (((d32 & mask) != mask) && loop--) { in lio_cn6xxx_disable_io_queues()
368 /* Reset the doorbell register for each Input queue. */ in lio_cn6xxx_disable_io_queues()
370 if (!(oct->io_qmask.iq & BIT_ULL(i))) in lio_cn6xxx_disable_io_queues()
376 /* Reset the Enable bits for Output Queues. */ in lio_cn6xxx_disable_io_queues()
377 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_disable_io_queues()
378 mask ^= oct->io_qmask.oq; in lio_cn6xxx_disable_io_queues()
379 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); in lio_cn6xxx_disable_io_queues()
381 /* Wait until hardware indicates that the queues are out of reset. */ in lio_cn6xxx_disable_io_queues()
383 mask = (u32)oct->io_qmask.oq; in lio_cn6xxx_disable_io_queues()
385 while (((d32 & mask) != mask) && loop--) { in lio_cn6xxx_disable_io_queues()
391 /* Reset the doorbell register for each Output queue. */ in lio_cn6xxx_disable_io_queues()
393 if (!(oct->io_qmask.oq & BIT_ULL(i))) in lio_cn6xxx_disable_io_queues()
420 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
422 CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
423 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
431 CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
433 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
438 u32 mask) in lio_cn6xxx_bar1_idx_write() argument
440 lio_pci_writeq(oct, mask, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_write()
445 return (u32)lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_read()
451 u32 new_idx = readl(iq->inst_cnt_reg); in lio_cn6xxx_update_read_index()
453 /* The new instr cnt reg is a 32-bit counter that can roll over. We have in lio_cn6xxx_update_read_index()
457 if (iq->reset_instr_cnt < new_idx) in lio_cn6xxx_update_read_index()
458 new_idx -= iq->reset_instr_cnt; in lio_cn6xxx_update_read_index()
460 new_idx += (0xffffffff - iq->reset_instr_cnt) + 1; in lio_cn6xxx_update_read_index()
465 new_idx %= iq->max_count; in lio_cn6xxx_update_read_index()
473 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_enable_interrupt()
474 u64 mask = cn6xxx->intr_mask64 | CN6XXX_INTR_DMA0_FORCE; in lio_cn6xxx_enable_interrupt() local
477 writeq(mask, cn6xxx->intr_enb_reg64); in lio_cn6xxx_enable_interrupt()
483 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_disable_interrupt()
486 writeq(0, cn6xxx->intr_enb_reg64); in lio_cn6xxx_disable_interrupt()
494 oct->pcie_port = octeon_read_csr(oct, CN6XXX_SLI_MAC_NUMBER) & 0xff; in lio_cn6xxx_get_pcie_qlmport()
496 dev_dbg(&oct->pci_dev->dev, "Using PCIE Port %d\n", oct->pcie_port); in lio_cn6xxx_get_pcie_qlmport()
502 dev_err(&oct->pci_dev->dev, "Error Intr: 0x%016llx\n", in lio_cn6xxx_process_pcie_error_intr()
521 droq_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
523 oct->droq_intr = 0; in lio_cn6xxx_process_droq_intr_regs()
529 droq = oct->droq[oq_no]; in lio_cn6xxx_process_droq_intr_regs()
532 oct->droq_intr |= BIT_ULL(oq_no); in lio_cn6xxx_process_droq_intr_regs()
533 if (droq->ops.poll_mode) { in lio_cn6xxx_process_droq_intr_regs()
538 (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_process_droq_intr_regs()
542 (&cn6xxx->lock_for_droq_int_enb_reg); in lio_cn6xxx_process_droq_intr_regs()
552 spin_unlock(&cn6xxx->lock_for_droq_int_enb_reg); in lio_cn6xxx_process_droq_intr_regs()
557 droq_time_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
558 droq_cnt_mask &= oct->io_qmask.oq; in lio_cn6xxx_process_droq_intr_regs()
560 /* Reset the PKT_CNT/TIME_INT registers. */ in lio_cn6xxx_process_droq_intr_regs()
564 if (droq_cnt_mask) /* reset PKT_CNT register:66xx */ in lio_cn6xxx_process_droq_intr_regs()
573 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_process_interrupt_regs()
576 intr64 = readq(cn6xxx->intr_sum_reg64); in lio_cn6xxx_process_interrupt_regs()
585 oct->int_status = 0; in lio_cn6xxx_process_interrupt_regs()
592 oct->int_status |= OCT_DEV_INTR_PKT_DATA; in lio_cn6xxx_process_interrupt_regs()
596 oct->int_status |= OCT_DEV_INTR_DMA0_FORCE; in lio_cn6xxx_process_interrupt_regs()
599 oct->int_status |= OCT_DEV_INTR_DMA1_FORCE; in lio_cn6xxx_process_interrupt_regs()
602 writeq(intr64, cn6xxx->intr_sum_reg64); in lio_cn6xxx_process_interrupt_regs()
611 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr; in lio_cn6xxx_setup_reg_address()
614 reg_list->pci_win_wr_addr_hi = in lio_cn6xxx_setup_reg_address()
616 reg_list->pci_win_wr_addr_lo = in lio_cn6xxx_setup_reg_address()
618 reg_list->pci_win_wr_addr = in lio_cn6xxx_setup_reg_address()
621 reg_list->pci_win_rd_addr_hi = in lio_cn6xxx_setup_reg_address()
623 reg_list->pci_win_rd_addr_lo = in lio_cn6xxx_setup_reg_address()
625 reg_list->pci_win_rd_addr = in lio_cn6xxx_setup_reg_address()
628 reg_list->pci_win_wr_data_hi = in lio_cn6xxx_setup_reg_address()
630 reg_list->pci_win_wr_data_lo = in lio_cn6xxx_setup_reg_address()
632 reg_list->pci_win_wr_data = in lio_cn6xxx_setup_reg_address()
635 reg_list->pci_win_rd_data_hi = in lio_cn6xxx_setup_reg_address()
637 reg_list->pci_win_rd_data_lo = in lio_cn6xxx_setup_reg_address()
639 reg_list->pci_win_rd_data = in lio_cn6xxx_setup_reg_address()
644 cn6xxx->intr_sum_reg64 = bar0_pciaddr + CN6XXX_SLI_INT_SUM64; in lio_cn6xxx_setup_reg_address()
645 cn6xxx->intr_mask64 = CN6XXX_INTR_MASK; in lio_cn6xxx_setup_reg_address()
646 cn6xxx->intr_enb_reg64 = in lio_cn6xxx_setup_reg_address()
647 bar0_pciaddr + CN6XXX_SLI_INT_ENB64(oct->pcie_port); in lio_cn6xxx_setup_reg_address()
652 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_setup_cn66xx_octeon_device()
658 dev_err(&oct->pci_dev->dev, "%s CN66XX BAR1 map failed\n", in lio_setup_cn66xx_octeon_device()
664 spin_lock_init(&cn6xxx->lock_for_droq_int_enb_reg); in lio_setup_cn66xx_octeon_device()
666 oct->fn_list.setup_iq_regs = lio_cn66xx_setup_iq_regs; in lio_setup_cn66xx_octeon_device()
667 oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs; in lio_setup_cn66xx_octeon_device()
669 oct->fn_list.soft_reset = lio_cn6xxx_soft_reset; in lio_setup_cn66xx_octeon_device()
670 oct->fn_list.setup_device_regs = lio_cn6xxx_setup_device_regs; in lio_setup_cn66xx_octeon_device()
671 oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index; in lio_setup_cn66xx_octeon_device()
673 oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup; in lio_setup_cn66xx_octeon_device()
674 oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write; in lio_setup_cn66xx_octeon_device()
675 oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read; in lio_setup_cn66xx_octeon_device()
677 oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs; in lio_setup_cn66xx_octeon_device()
678 oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt; in lio_setup_cn66xx_octeon_device()
679 oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt; in lio_setup_cn66xx_octeon_device()
681 oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues; in lio_setup_cn66xx_octeon_device()
682 oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues; in lio_setup_cn66xx_octeon_device()
684 lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list); in lio_setup_cn66xx_octeon_device()
686 cn6xxx->conf = (struct octeon_config *) in lio_setup_cn66xx_octeon_device()
688 if (!cn6xxx->conf) { in lio_setup_cn66xx_octeon_device()
689 dev_err(&oct->pci_dev->dev, "%s No Config found for CN66XX\n", in lio_setup_cn66xx_octeon_device()
696 oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct); in lio_setup_cn66xx_octeon_device()
706 dev_err(&oct->pci_dev->dev, "%s: Num IQ (%d) exceeds Max (%d)\n", in lio_validate_cn6xxx_config_info()
713 dev_err(&oct->pci_dev->dev, "%s: Num OQ (%d) exceeds Max (%d)\n", in lio_validate_cn6xxx_config_info()
721 dev_err(&oct->pci_dev->dev, "%s: Invalid instr type for IQ\n", in lio_validate_cn6xxx_config_info()
726 dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n", in lio_validate_cn6xxx_config_info()
732 dev_err(&oct->pci_dev->dev, "%s: No Time Interrupt for OQ\n", in lio_validate_cn6xxx_config_info()