14481 	u32 nvcfg1;  in tg3_get_nvram_info()  local
14483 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_nvram_info()
14484 	if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {  in tg3_get_nvram_info()
14487 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_nvram_info()
14488 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_nvram_info()
14493 		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {  in tg3_get_nvram_info()
14559 	u32 nvcfg1;  in tg3_get_5752_nvram_info()  local
14561 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5752_nvram_info()
14564 	if (nvcfg1 & (1 << 27))  in tg3_get_5752_nvram_info()
14567 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5752_nvram_info()
14588 		tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5752_nvram_info()
14593 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5752_nvram_info()
14594 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5752_nvram_info()
14600 	u32 nvcfg1, protect = 0;  in tg3_get_5755_nvram_info()  local
14602 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5755_nvram_info()
14605 	if (nvcfg1 & (1 << 27)) {  in tg3_get_5755_nvram_info()
14610 	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5755_nvram_info()
14611 	switch (nvcfg1) {  in tg3_get_5755_nvram_info()
14620 		if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||  in tg3_get_5755_nvram_info()
14621 		    nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)  in tg3_get_5755_nvram_info()
14624 		else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)  in tg3_get_5755_nvram_info()
14638 		if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)  in tg3_get_5755_nvram_info()
14642 		else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)  in tg3_get_5755_nvram_info()
14656 	u32 nvcfg1;  in tg3_get_5787_nvram_info()  local
14658 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5787_nvram_info()
14660 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5787_nvram_info()
14669 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5787_nvram_info()
14670 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5787_nvram_info()
14694 	u32 nvcfg1, protect = 0;  in tg3_get_5761_nvram_info()  local
14696 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5761_nvram_info()
14699 	if (nvcfg1 & (1 << 27)) {  in tg3_get_5761_nvram_info()
14704 	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5761_nvram_info()
14705 	switch (nvcfg1) {  in tg3_get_5761_nvram_info()
14738 		switch (nvcfg1) {  in tg3_get_5761_nvram_info()
14776 	u32 nvcfg1;  in tg3_get_57780_nvram_info()  local
14778 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_57780_nvram_info()
14780 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14787 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_57780_nvram_info()
14788 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_57780_nvram_info()
14801 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14824 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14841 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_57780_nvram_info()
14849 	u32 nvcfg1;  in tg3_get_5717_nvram_info()  local
14851 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5717_nvram_info()
14853 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14860 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5717_nvram_info()
14861 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5717_nvram_info()
14874 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14901 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14920 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5717_nvram_info()
14927 	u32 nvcfg1, nvmpinstrp, nv_status;  in tg3_get_5720_nvram_info()  local
14929 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5720_nvram_info()
14930 	nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5720_nvram_info()
14933 		if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {  in tg3_get_5720_nvram_info()
14977 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5720_nvram_info()
14978 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5720_nvram_info()
15073 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5720_nvram_info()