Lines Matching +full:hb +full:- +full:pll +full:- +full:clock
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
124 * and dev->tx_timeout() should be called to fix the problem
147 /* Do not place this n-ring entries value into the tp struct itself,
151 * replace things like '% foo' with '& (foo - 1)'.
155 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
162 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
165 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
198 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
202 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
208 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
473 writel(val, tp->regs + off); in tg3_write32()
478 return readl(tp->regs + off); in tg3_read32()
483 writel(val, tp->aperegs + off); in tg3_ape_write32()
488 return readl(tp->aperegs + off); in tg3_ape_read32()
495 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
498 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
503 writel(val, tp->regs + off); in tg3_write_flush_reg32()
504 readl(tp->regs + off); in tg3_write_flush_reg32()
512 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
515 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
534 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
537 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
554 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
557 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
569 /* Non-posted methods */ in _tw32_flush()
570 tp->write32(tp, off, val); in _tw32_flush()
576 tp->read32(tp, off); in _tw32_flush()
587 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
591 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
596 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
607 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
612 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
624 #define tr32(reg) tp->read32(tp, reg)
634 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
648 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
661 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
675 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
698 if (!tp->pci_fn) in tg3_ape_lock_init()
701 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
724 if (!tp->pci_fn) in tg3_ape_lock()
727 bit = 1 << tp->pci_fn; in tg3_ape_lock()
736 return -EINVAL; in tg3_ape_lock()
756 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
765 ret = -EBUSY; in tg3_ape_lock()
785 if (!tp->pci_fn) in tg3_ape_unlock()
788 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
814 return -EBUSY; in tg3_ape_event_lock()
823 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
826 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
857 return -ENODEV; in tg3_ape_scratchpad_read()
861 return -EAGAIN; in tg3_ape_scratchpad_read()
873 len -= length; in tg3_ape_scratchpad_read()
877 return -EAGAIN; in tg3_ape_scratchpad_read()
898 return -EAGAIN; in tg3_ape_scratchpad_read()
900 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
918 return -EAGAIN; in tg3_ape_send_event()
922 return -EAGAIN; in tg3_ape_send_event()
948 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
965 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
989 /* Check if hb interval has exceeded */ in tg3_send_ape_heartbeat()
991 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
994 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
995 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1003 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1004 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1005 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1012 tp->irq_sync = 0; in tg3_enable_ints()
1016 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1018 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1019 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1020 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1022 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1024 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1026 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1031 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1032 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1034 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1036 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1041 struct tg3 *tp = tnapi->tp; in tg3_has_work()
1042 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1047 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1052 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1056 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1057 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1070 struct tg3 *tp = tnapi->tp; in tg3_int_reenable()
1072 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1079 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1080 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1097 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1125 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1127 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1131 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1153 loops -= 1; in __tg3_readphy()
1156 ret = -EBUSY; in __tg3_readphy()
1162 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1163 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1167 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1174 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1184 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1188 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1190 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1194 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1214 loops -= 1; in __tg3_writephy()
1217 ret = -EBUSY; in __tg3_writephy()
1221 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1222 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1226 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1233 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1363 return -EBUSY; in tg3_bmcr_reset()
1366 while (limit--) { in tg3_bmcr_reset()
1369 return -EBUSY; in tg3_bmcr_reset()
1378 return -EBUSY; in tg3_bmcr_reset()
1385 struct tg3 *tp = bp->priv; in tg3_mdio_read()
1388 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1391 val = -EIO; in tg3_mdio_read()
1393 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1400 struct tg3 *tp = bp->priv; in tg3_mdio_write()
1403 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1406 ret = -EIO; in tg3_mdio_write()
1408 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1418 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1419 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1437 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1496 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1497 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1514 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1522 tp->phy_addr += 7; in tg3_mdio_init()
1526 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1529 tp->phy_addr = addr; in tg3_mdio_init()
1531 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1538 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1539 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1540 return -ENOMEM; in tg3_mdio_init()
1542 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1543 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev)); in tg3_mdio_init()
1544 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1545 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1546 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1547 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1548 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1558 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1560 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1561 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1565 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1567 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1568 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1569 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1570 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1571 return -ENODEV; in tg3_mdio_init()
1574 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1576 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1577 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1581 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1587 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1591 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1592 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1593 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1609 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1610 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1614 /* tp->lock is held. */
1623 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1628 /* tp->lock is held. */
1636 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1637 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1651 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1658 /* tp->lock is held. */
1678 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1693 /* tp->lock is held. */
1715 /* tp->lock is held. */
1731 /* tp->lock is held. */
1760 /* tp->lock is held. */
1781 /* tp->lock is held. */
1825 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1826 return -ENODEV; in tg3_poll_fw()
1830 return -ENODEV; in tg3_poll_fw()
1838 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1841 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1858 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1873 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1874 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1877 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1878 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1880 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1882 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1885 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1891 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1892 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1893 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1898 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1965 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1966 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1969 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1971 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1974 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1979 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1981 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1984 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1986 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1988 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1989 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1992 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1994 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1996 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1997 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2005 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2007 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2009 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2012 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2014 if (phydev->link) { in tg3_adjust_link()
2018 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2020 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2026 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2030 tp->link_config.flowctrl); in tg3_adjust_link()
2032 if (phydev->pause) in tg3_adjust_link()
2034 if (phydev->asym_pause) in tg3_adjust_link()
2042 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2043 tp->mac_mode = mac_mode; in tg3_adjust_link()
2044 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2049 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2057 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2068 if (phydev->link != tp->old_link || in tg3_adjust_link()
2069 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2070 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2071 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2074 tp->old_link = phydev->link; in tg3_adjust_link()
2075 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2076 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2078 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2088 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2094 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2097 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2098 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2100 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2105 switch (phydev->interface) { in tg3_phy_init()
2108 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2119 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2120 return -EINVAL; in tg3_phy_init()
2123 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2134 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2137 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2139 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2140 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2141 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2142 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2143 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2145 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2155 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2158 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2163 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2164 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2165 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2174 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2177 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2178 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2225 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2228 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2255 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2258 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2296 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2309 if (!tp->phy_otp) in tg3_phy_apply_otp()
2312 otp = tp->phy_otp; in tg3_phy_apply_otp()
2345 struct ethtool_keee *dest = &tp->eee; in tg3_eee_pull_config()
2347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2359 dest->eee_active = 1; in tg3_eee_pull_config()
2361 dest->eee_active = 0; in tg3_eee_pull_config()
2366 mii_eee_cap1_mod_linkmode_t(dest->lp_advertised, val); in tg3_eee_pull_config()
2371 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2372 mii_eee_cap1_mod_linkmode_t(dest->advertised, val); in tg3_eee_pull_config()
2376 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2379 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2386 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2389 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2391 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2393 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2394 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2395 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2398 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2406 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2407 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2410 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2426 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2445 while (limit--) { in tg3_wait_macro_done()
2454 return -EBUSY; in tg3_wait_macro_done()
2483 return -EBUSY; in tg3_phy_write_and_check_testpat()
2491 return -EBUSY; in tg3_phy_write_and_check_testpat()
2497 return -EBUSY; in tg3_phy_write_and_check_testpat()
2507 return -EBUSY; in tg3_phy_write_and_check_testpat()
2517 return -EBUSY; in tg3_phy_write_and_check_testpat()
2539 return -EBUSY; in tg3_phy_reset_chanpat()
2567 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2588 } while (--retries); in tg3_phy_reset_5703_4_5()
2615 netif_carrier_off(tp->dev); in tg3_carrier_off()
2616 tp->link_up = false; in tg3_carrier_off()
2622 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2623 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2627 * link unless the FORCE argument is non-zero.
2642 return -EBUSY; in tg3_phy_reset()
2644 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2645 netif_carrier_off(tp->dev); in tg3_phy_reset()
2690 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2695 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2701 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2708 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2713 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2720 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2723 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2736 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2737 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2740 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2796 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2818 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2822 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2827 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2843 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2865 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2872 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2873 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2874 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2880 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2898 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2904 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2917 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2923 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2929 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2976 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2979 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3006 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3008 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3024 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3028 if (!tp->pci_fn) in tg3_phy_power_bug()
3033 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3034 !tp->pci_fn) in tg3_phy_power_bug()
3047 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3048 !tp->pci_fn) in tg3_phy_led_bug()
3060 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3063 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3082 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3130 /* tp->lock is held. */
3136 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3145 return -ENODEV; in tg3_nvram_lock()
3148 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3153 /* tp->lock is held. */
3157 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3158 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3159 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3164 /* tp->lock is held. */
3174 /* tp->lock is held. */
3191 return -EINVAL; in tg3_nvram_read_using_eeprom()
3211 return -EBUSY; in tg3_nvram_read_using_eeprom()
3240 return -EBUSY; in tg3_nvram_exec_cmd()
3251 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3253 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3255 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3266 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3269 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3270 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3279 * machine, the 32-bit value will be byteswapped.
3291 return -EINVAL; in tg3_nvram_read()
3364 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3377 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3378 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3384 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3406 len -= size; in tg3_nvram_write_block_unbuffered()
3410 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3452 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3484 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3492 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3495 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3505 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3532 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3569 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3581 /* tp->lock is held. */
3592 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3593 return -EBUSY; in tg3_pause_cpu()
3596 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3599 /* tp->lock is held. */
3611 /* tp->lock is held. */
3617 /* tp->lock is held. */
3624 /* tp->lock is held. */
3630 /* tp->lock is held. */
3657 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3659 return -ENODEV; in tg3_halt_cpu()
3677 * tp->fw->size minus headers. in tg3_fw_data_len()
3687 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3688 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3690 fw_len = tp->fw->size; in tg3_fw_data_len()
3692 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3695 /* tp->lock is held. */
3702 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3705 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3708 return -EINVAL; in tg3_load_firmware_cpu()
3736 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3744 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3748 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3752 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3761 /* tp->lock is held. */
3779 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3782 /* tp->lock is held. */
3788 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3792 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3810 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3812 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3815 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3816 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3841 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3842 return -EBUSY; in tg3_validate_rxcpu_state()
3847 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3849 return -EEXIST; in tg3_validate_rxcpu_state()
3855 /* tp->lock is held. */
3866 if (!tp->fw) in tg3_load_57766_firmware()
3871 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3883 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3884 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3896 /* tp->lock is held. */
3906 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3910 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3914 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3933 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3935 netdev_err(tp->dev, in tg3_load_tso_firmware()
3938 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3939 return -ENODEV; in tg3_load_tso_firmware()
3946 /* tp->lock is held. */
3960 index -= 4; in __tg3_set_one_mac_addr()
3966 /* tp->lock is held. */
3975 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3981 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3984 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3989 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
4000 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4001 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4010 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4015 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4032 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4039 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4044 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4045 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4050 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4052 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4054 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4055 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4056 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4058 &tp->link_config.advertising, in tg3_power_down_prepare()
4059 phydev->advertising); in tg3_power_down_prepare()
4083 linkmode_copy(phydev->advertising, advertising); in tg3_power_down_prepare()
4086 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4098 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4099 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4101 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4130 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4132 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4141 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4143 else if (tp->phy_flags & in tg3_power_down_prepare()
4145 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4152 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4166 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4190 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4217 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4220 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4236 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4245 /* Workaround for unstable PLL clock */ in tg3_power_down_prepare()
4272 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4273 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4310 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4336 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4348 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4358 if (!tp->eee.eee_enabled) in tg3_phy_autoneg_cfg()
4363 mii_eee_cap1_mod_linkmode_t(tp->eee.advertised, val); in tg3_phy_autoneg_cfg()
4398 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4399 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4402 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4403 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4409 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4410 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4418 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4419 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4423 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4428 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4429 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4443 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4444 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4455 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4469 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4503 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4504 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4507 err = -EIO; in tg3_phy_pull_config()
4511 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4514 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4517 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4520 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4523 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4524 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4533 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4535 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4537 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4543 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4544 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4547 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4555 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4557 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4559 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4562 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4565 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4577 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4583 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4613 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4618 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4619 if (!linkmode_equal(tp->eee.advertised, eee.advertised) || in tg3_phy_eee_config_ok()
4620 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4621 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4636 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4640 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4641 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4651 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4680 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4693 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4700 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4702 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4704 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4705 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4706 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4743 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4753 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4757 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4775 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4777 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4783 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4789 tp->link_up) { in tg3_setup_copper_phy()
4798 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4819 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4822 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4843 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4845 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4850 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4860 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4861 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4863 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4912 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4913 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4915 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4929 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4936 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4937 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4943 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4946 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4955 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4962 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4970 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4971 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4976 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4980 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4982 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4983 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4984 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4986 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4987 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4999 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5001 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5004 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5012 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5013 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5014 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5018 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5019 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5021 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5027 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5029 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5030 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5034 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5049 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5063 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5064 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5065 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5068 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5137 #define ANEG_FAILED -1
5149 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5150 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5151 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5152 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5153 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5154 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5155 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5156 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5157 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5159 ap->cur_time++; in tg3_fiber_aneg_smachine()
5164 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5165 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5166 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5167 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5169 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5170 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5171 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5175 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5177 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5179 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5181 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5182 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5183 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5184 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5185 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5190 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5193 switch (ap->state) { in tg3_fiber_aneg_smachine()
5195 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5196 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5200 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5201 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5202 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5203 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5204 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5205 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5206 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5207 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5208 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5210 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5212 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5217 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5218 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5219 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5221 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5222 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5226 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5230 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5232 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5242 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5243 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5244 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5246 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5248 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5249 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5250 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5251 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5254 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5258 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5259 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5263 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5264 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5265 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5266 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5269 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5273 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5274 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5275 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5276 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5278 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5280 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5281 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5282 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5287 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5291 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5300 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5301 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5302 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5303 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5304 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5305 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5306 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5307 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5308 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5309 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5310 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5311 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5312 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5313 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5315 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5317 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5318 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5319 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5320 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5321 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5322 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5324 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5329 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5330 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5331 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5334 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5336 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5337 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5339 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5340 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5350 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5351 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5352 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5355 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5360 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5361 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5362 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5365 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5368 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5373 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5403 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5407 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5423 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5424 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5448 /* Set PLL lock range. */ in tg3_init_bcm8002()
5462 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5507 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5508 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5514 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5535 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5538 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5545 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5546 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5550 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5561 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5562 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5582 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5587 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5588 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5590 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5591 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5607 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5615 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5617 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5624 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5625 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5639 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5656 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5686 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5689 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5706 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5707 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5708 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5711 tp->link_up && in tg3_setup_fiber_phy()
5728 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5729 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5730 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5733 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5740 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5748 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5750 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5765 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5766 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5767 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5770 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5775 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5776 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5777 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5781 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5782 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5789 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5791 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5792 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5816 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5819 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5824 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5827 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5839 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5847 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5848 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5856 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5869 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5870 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5872 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5881 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5882 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5890 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5891 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5901 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5911 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5935 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5963 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5977 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5978 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5979 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5981 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5986 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5987 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
5995 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
5997 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6001 if (!tp->link_up && in tg3_serdes_parallel_detect()
6002 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6028 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6031 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6032 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6033 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6047 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6058 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6060 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6089 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6090 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6098 if (tp->link_up) { in tg3_setup_phy()
6100 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6108 if (!tp->link_up) in tg3_setup_phy()
6110 tp->pwrmgmt_thresh; in tg3_setup_phy()
6119 /* tp->lock must be held */
6132 /* tp->lock must be held */
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; in tg3_get_ts_info()
6152 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6157 if (tp->ptp_clock) in tg3_get_ts_info()
6158 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6160 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6162 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6202 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6216 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6234 tp->ptp_adjust = 0; in tg3_ptp_settime()
6247 switch (rq->type) { in tg3_ptp_enable()
6250 if (rq->perout.flags) in tg3_ptp_enable()
6251 return -EOPNOTSUPP; in tg3_ptp_enable()
6253 if (rq->perout.index != 0) in tg3_ptp_enable()
6254 return -EINVAL; in tg3_ptp_enable()
6263 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6264 rq->perout.start.nsec; in tg3_ptp_enable()
6266 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6267 netdev_warn(tp->dev, in tg3_ptp_enable()
6268 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6269 rval = -EINVAL; in tg3_ptp_enable()
6274 netdev_warn(tp->dev, in tg3_ptp_enable()
6276 rval = -EINVAL; in tg3_ptp_enable()
6300 return -EOPNOTSUPP; in tg3_ptp_enable()
6307 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6308 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6323 if (tp->ptp_txts_retrycnt > 2) in tg3_ptp_ts_aux_work()
6328 if (hwclock != tp->pre_tx_ts) { in tg3_ptp_ts_aux_work()
6330 skb_tstamp_tx(tp->tx_tstamp_skb, ×tamp); in tg3_ptp_ts_aux_work()
6333 tp->ptp_txts_retrycnt++; in tg3_ptp_ts_aux_work()
6336 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_ts_aux_work()
6337 tp->tx_tstamp_skb = NULL; in tg3_ptp_ts_aux_work()
6338 tp->ptp_txts_retrycnt = 0; in tg3_ptp_ts_aux_work()
6339 tp->pre_tx_ts = 0; in tg3_ptp_ts_aux_work()
6340 return -1; in tg3_ptp_ts_aux_work()
6345 .name = "tg3 clock",
6360 /* tp->lock must be held */
6366 /* Initialize the hardware clock to the system time. */ in tg3_ptp_init()
6368 tp->ptp_adjust = 0; in tg3_ptp_init()
6369 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6372 /* tp->lock must be held */
6378 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6379 tp->ptp_adjust = 0; in tg3_ptp_resume()
6384 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6387 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6388 tp->ptp_clock = NULL; in tg3_ptp_fini()
6389 tp->ptp_adjust = 0; in tg3_ptp_fini()
6390 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_fini()
6391 tp->tx_tstamp_skb = NULL; in tg3_ptp_fini()
6396 return tp->irq_sync; in tg3_irq_sync()
6466 if (tp->pdev->error_state != pci_channel_io_normal) { in tg3_dump_state()
6467 netdev_err(tp->dev, "PCI channel ERROR!\n"); in tg3_dump_state()
6487 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6494 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6495 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6498 netdev_err(tp->dev, in tg3_dump_state()
6501 tnapi->hw_status->status, in tg3_dump_state()
6502 tnapi->hw_status->status_tag, in tg3_dump_state()
6503 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6504 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6505 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6506 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6507 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6509 netdev_err(tp->dev, in tg3_dump_state()
6512 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6513 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6514 tnapi->rx_rcb_ptr, in tg3_dump_state()
6515 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6516 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6517 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6518 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6522 /* This is called whenever we suspect that the system chipset is re-
6531 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6533 netdev_warn(tp->dev, in tg3_tx_recover()
6534 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6546 return tnapi->tx_pending - in tg3_tx_avail()
6547 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6556 struct tg3 *tp = tnapi->tp; in tg3_tx()
6557 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6558 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6560 int index = tnapi - tp->napi; in tg3_tx()
6564 index--; in tg3_tx()
6566 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6569 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6571 struct sk_buff *skb = ri->skb; in tg3_tx()
6579 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6584 if (hwclock != tp->pre_tx_ts) { in tg3_tx()
6587 tp->pre_tx_ts = 0; in tg3_tx()
6589 tp->tx_tstamp_skb = skb; in tg3_tx()
6594 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6597 ri->skb = NULL; in tg3_tx()
6599 while (ri->fragmented) { in tg3_tx()
6600 ri->fragmented = false; in tg3_tx()
6602 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6607 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6608 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6609 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6612 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6614 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6617 while (ri->fragmented) { in tg3_tx()
6618 ri->fragmented = false; in tg3_tx()
6620 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6627 bytes_compl += skb->len; in tg3_tx()
6632 ptp_schedule_worker(tp->ptp_clock, 0); in tg3_tx()
6642 tnapi->tx_cons = sw_idx; in tg3_tx()
6674 if (!ri->data) in tg3_rx_data_free()
6677 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6679 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6680 ri->data = NULL; in tg3_rx_data_free()
6707 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6708 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6709 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6710 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6714 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6715 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6716 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6721 return -EINVAL; in tg3_alloc_rx_data()
6740 return -ENOMEM; in tg3_alloc_rx_data()
6742 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6744 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6746 return -EIO; in tg3_alloc_rx_data()
6749 map->data = data; in tg3_alloc_rx_data()
6752 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6753 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6767 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx()
6770 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6775 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6776 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6777 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6778 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6779 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6783 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6784 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6785 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6786 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6787 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6794 dest_map->data = src_map->data; in tg3_recycle_rx()
6797 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6798 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6805 src_map->data = NULL; in tg3_recycle_rx()
6820 * it is first placed into the on-chip ram. When the packet's length
6828 * rings, then cache lines never move beyond shared-modified state.
6834 struct tg3 *tp = tnapi->tp; in tg3_rx()
6837 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6840 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6842 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6850 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6851 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6854 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6862 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6863 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6865 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6867 data = ri->data; in tg3_rx()
6871 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6873 data = ri->data; in tg3_rx()
6880 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6886 tnapi->rx_dropped++; in tg3_rx()
6891 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6894 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6896 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6911 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6919 ri->data = NULL; in tg3_rx()
6934 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6940 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6942 memcpy(skb->data, in tg3_rx()
6945 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6954 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6955 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6956 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6958 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6962 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6964 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6965 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6966 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6971 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6972 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6974 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6976 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6979 budget--; in tg3_rx()
6984 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6985 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6986 tp->rx_std_ring_mask; in tg3_rx()
6988 tpr->rx_std_prod_idx); in tg3_rx()
6994 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6998 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
7004 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
7005 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
7013 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
7014 tp->rx_std_ring_mask; in tg3_rx()
7016 tpr->rx_std_prod_idx); in tg3_rx()
7019 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
7020 tp->rx_jmb_ring_mask; in tg3_rx()
7022 tpr->rx_jmb_prod_idx); in tg3_rx()
7030 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7031 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7033 if (tnapi != &tp->napi[1]) { in tg3_rx()
7034 tp->rx_refill = true; in tg3_rx()
7035 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7046 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7048 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7049 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7050 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7051 spin_lock(&tp->lock); in tg3_poll_link()
7061 spin_unlock(&tp->lock); in tg3_poll_link()
7074 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7081 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7084 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7085 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7087 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7088 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7091 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7093 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7094 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7097 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7098 cpycnt = i - di; in tg3_rx_prodring_xfer()
7099 err = -ENOSPC; in tg3_rx_prodring_xfer()
7113 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7114 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7119 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7120 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7121 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7122 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7125 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7126 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7127 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7128 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7132 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7139 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7142 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7143 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7145 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7146 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7149 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7151 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7152 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7155 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7156 cpycnt = i - di; in tg3_rx_prodring_xfer()
7157 err = -ENOSPC; in tg3_rx_prodring_xfer()
7171 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7172 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7177 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7178 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7179 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7180 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7183 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7184 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7185 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7186 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7194 struct tg3 *tp = tnapi->tp; in tg3_poll_work()
7197 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7203 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7208 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7210 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7211 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7213 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7214 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7216 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7217 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7219 tp->rx_refill = false; in tg3_poll_work()
7220 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7222 &tp->napi[i].prodring); in tg3_poll_work()
7226 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7228 dpr->rx_std_prod_idx); in tg3_poll_work()
7230 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7232 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7235 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7243 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7244 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7249 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7250 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7257 struct tg3 *tp = tnapi->tp; in tg3_poll_msix()
7259 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7270 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7274 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7275 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7279 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7280 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7285 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7290 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7295 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7296 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7298 tnapi->coal_now); in tg3_poll_msix()
7325 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7330 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7335 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7351 struct tg3 *tp = tnapi->tp; in tg3_poll()
7353 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7356 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7370 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7374 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7375 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7378 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7399 int txq_idx = tp->txq_cnt - 1; in tg3_napi_disable()
7400 int rxq_idx = tp->rxq_cnt - 1; in tg3_napi_disable()
7404 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_napi_disable()
7405 tnapi = &tp->napi[i]; in tg3_napi_disable()
7406 if (tnapi->tx_buffers) { in tg3_napi_disable()
7407 netif_queue_set_napi(tp->dev, txq_idx, in tg3_napi_disable()
7409 txq_idx--; in tg3_napi_disable()
7411 if (tnapi->rx_rcb) { in tg3_napi_disable()
7412 netif_queue_set_napi(tp->dev, rxq_idx, in tg3_napi_disable()
7414 rxq_idx--; in tg3_napi_disable()
7416 napi_disable(&tnapi->napi); in tg3_napi_disable()
7426 for (i = 0; i < tp->irq_cnt; i++) { in tg3_napi_enable()
7427 tnapi = &tp->napi[i]; in tg3_napi_enable()
7428 napi_enable_locked(&tnapi->napi); in tg3_napi_enable()
7429 if (tnapi->tx_buffers) { in tg3_napi_enable()
7430 netif_queue_set_napi(tp->dev, txq_idx, in tg3_napi_enable()
7432 &tnapi->napi); in tg3_napi_enable()
7435 if (tnapi->rx_rcb) { in tg3_napi_enable()
7436 netif_queue_set_napi(tp->dev, rxq_idx, in tg3_napi_enable()
7438 &tnapi->napi); in tg3_napi_enable()
7448 for (i = 0; i < tp->irq_cnt; i++) { in tg3_napi_init()
7449 netif_napi_add_locked(tp->dev, &tp->napi[i].napi, in tg3_napi_init()
7451 netif_napi_set_irq_locked(&tp->napi[i].napi, in tg3_napi_init()
7452 tp->napi[i].irq_vec); in tg3_napi_init()
7460 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7461 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7466 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7468 netif_carrier_off(tp->dev); in tg3_netif_stop()
7469 netif_tx_disable(tp->dev); in tg3_netif_stop()
7472 /* tp->lock must be held */
7481 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7483 if (tp->link_up) in tg3_netif_start()
7484 netif_carrier_on(tp->dev); in tg3_netif_start()
7487 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7492 __releases(tp->lock) in tg3_irq_quiesce()
7493 __acquires(tp->lock) in tg3_irq_quiesce()
7497 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7499 tp->irq_sync = 1; in tg3_irq_quiesce()
7502 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7504 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7505 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7507 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7511 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7517 spin_lock_bh(&tp->lock); in tg3_full_lock()
7524 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7527 /* One-shot MSI handler - Chip automatically disables interrupt
7533 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot()
7535 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7536 if (tnapi->rx_rcb) in tg3_msi_1shot()
7537 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7540 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7545 /* MSI ISR - No need to check for interrupt sharing and no need to
7552 struct tg3 *tp = tnapi->tp; in tg3_msi()
7554 prefetch(tnapi->hw_status); in tg3_msi()
7555 if (tnapi->rx_rcb) in tg3_msi()
7556 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7558 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7559 * chip-internal interrupt pending events. in tg3_msi()
7560 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7561 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7564 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7566 napi_schedule(&tnapi->napi); in tg3_msi()
7574 struct tg3 *tp = tnapi->tp; in tg3_interrupt()
7575 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7583 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7592 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7593 * chip-internal interrupt pending events. in tg3_interrupt()
7594 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7595 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7598 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7605 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7607 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7608 napi_schedule(&tnapi->napi); in tg3_interrupt()
7610 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7623 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged()
7624 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7632 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7641 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7642 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7643 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7644 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7647 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7659 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7664 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7666 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7676 struct tg3 *tp = tnapi->tp; in tg3_test_isr()
7677 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7679 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7696 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7697 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7735 /* Test for DMA addresses > 40-bit */
7752 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7753 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7754 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7755 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7762 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set()
7777 if (tp->dma_limit) { in tg3_tx_frag_set()
7780 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7781 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7782 len -= tp->dma_limit; in tg3_tx_frag_set()
7786 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7787 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7790 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7792 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7794 *budget -= 1; in tg3_tx_frag_set()
7803 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7805 *budget -= 1; in tg3_tx_frag_set()
7809 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7813 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7825 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7827 skb = txb->skb; in tg3_tx_skb_unmap()
7828 txb->skb = NULL; in tg3_tx_skb_unmap()
7830 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7833 while (txb->fragmented) { in tg3_tx_skb_unmap()
7834 txb->fragmented = false; in tg3_tx_skb_unmap()
7836 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7840 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7843 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7845 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7849 while (txb->fragmented) { in tg3_tx_skb_unmap()
7850 txb->fragmented = false; in tg3_tx_skb_unmap()
7852 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7857 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7863 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround()
7871 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7879 ret = -1; in tigon3_dma_hwbug_workaround()
7882 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7883 new_skb->len, DMA_TO_DEVICE); in tigon3_dma_hwbug_workaround()
7885 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7887 ret = -1; in tigon3_dma_hwbug_workaround()
7893 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7894 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7898 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7900 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7902 ret = -1; in tigon3_dma_hwbug_workaround()
7917 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7928 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7947 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7950 tnapi->tx_dropped++; in tg3_tso_bug()
7956 __tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7971 int i = -1, would_hit_hwbug; in __tg3_start_xmit()
7982 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in __tg3_start_xmit()
7989 * and TX reclaim runs via tp->napi.poll inside of a software in __tg3_start_xmit()
7993 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in __tg3_start_xmit()
8004 entry = tnapi->tx_prod; in __tg3_start_xmit()
8007 mss = skb_shinfo(skb)->gso_size; in __tg3_start_xmit()
8017 hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN; in __tg3_start_xmit()
8022 if (skb->protocol == htons(ETH_P_8021Q) || in __tg3_start_xmit()
8023 skb->protocol == htons(ETH_P_8021AD)) { in __tg3_start_xmit()
8036 ip_csum = iph->check; in __tg3_start_xmit()
8037 ip_tot_len = iph->tot_len; in __tg3_start_xmit()
8038 iph->check = 0; in __tg3_start_xmit()
8039 iph->tot_len = htons(mss + hdr_len); in __tg3_start_xmit()
8046 tcp_csum = tcph->check; in __tg3_start_xmit()
8051 tcph->check = 0; in __tg3_start_xmit()
8054 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in __tg3_start_xmit()
8067 if (tcp_opt_len || iph->ihl > 5) { in __tg3_start_xmit()
8070 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in __tg3_start_xmit()
8074 if (tcp_opt_len || iph->ihl > 5) { in __tg3_start_xmit()
8077 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in __tg3_start_xmit()
8081 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in __tg3_start_xmit()
8085 if (skb->protocol == htons(ETH_P_8021Q) || in __tg3_start_xmit()
8086 skb->protocol == htons(ETH_P_8021AD)) { in __tg3_start_xmit()
8095 !mss && skb->len > VLAN_ETH_FRAME_LEN) in __tg3_start_xmit()
8103 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in __tg3_start_xmit()
8106 if (!tp->pre_tx_ts) { in __tg3_start_xmit()
8107 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in __tg3_start_xmit()
8109 tg3_read_tx_tstamp(tp, &tp->pre_tx_ts); in __tg3_start_xmit()
8116 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in __tg3_start_xmit()
8118 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8122 tnapi->tx_buffers[entry].skb = skb; in __tg3_start_xmit()
8123 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in __tg3_start_xmit()
8131 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in __tg3_start_xmit()
8134 } else if (skb_shinfo(skb)->nr_frags > 0) { in __tg3_start_xmit()
8145 last = skb_shinfo(skb)->nr_frags - 1; in __tg3_start_xmit()
8147 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in __tg3_start_xmit()
8150 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in __tg3_start_xmit()
8153 tnapi->tx_buffers[entry].skb = NULL; in __tg3_start_xmit()
8154 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in __tg3_start_xmit()
8156 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8171 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in __tg3_start_xmit()
8178 iph->check = ip_csum; in __tg3_start_xmit()
8179 iph->tot_len = ip_tot_len; in __tg3_start_xmit()
8181 tcph->check = tcp_csum; in __tg3_start_xmit()
8188 entry = tnapi->tx_prod; in __tg3_start_xmit()
8196 netdev_tx_sent_queue(txq, skb->len); in __tg3_start_xmit()
8201 tnapi->tx_prod = entry; in __tg3_start_xmit()
8218 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in __tg3_start_xmit()
8219 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in __tg3_start_xmit()
8223 tnapi->tx_dropped++; in __tg3_start_xmit()
8252 tnapi = &tp->napi[skb_queue_mapping]; in tg3_start_xmit()
8257 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_start_xmit()
8266 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8269 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8272 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8274 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8275 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8277 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8279 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8282 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8284 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8287 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8299 return -EIO; in tg3_phy_lpbk_set()
8310 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8320 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8336 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8341 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8352 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8356 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8359 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8367 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8389 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8392 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8394 netif_carrier_on(tp->dev); in tg3_set_loopback()
8395 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8398 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8401 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8405 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8415 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8423 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8436 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8437 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8438 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8439 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8440 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8443 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8444 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8445 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8446 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8454 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8455 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8456 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8459 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8460 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8469 * end up in the driver. tp->{tx,}lock are held and thus
8477 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8478 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8479 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8480 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8482 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8483 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8485 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8486 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8492 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8496 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8498 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8504 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8507 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8508 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8509 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8510 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8515 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8520 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8523 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8526 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8534 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8539 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8542 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8543 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8544 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8546 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8550 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8555 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8558 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8561 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8571 return -ENOMEM; in tg3_rx_prodring_alloc()
8577 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8578 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8579 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8580 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8581 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8582 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8583 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8584 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8586 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8587 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8588 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8589 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8596 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8598 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8599 return -ENOMEM; in tg3_rx_prodring_init()
8601 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8603 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8605 if (!tpr->rx_std) in tg3_rx_prodring_init()
8609 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8611 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8614 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8616 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8618 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8626 return -ENOMEM; in tg3_rx_prodring_init()
8633 * end up in the driver. tp->{tx,}lock is not held and we are not
8640 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8641 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8643 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8645 if (!tnapi->tx_buffers) in tg3_free_rings()
8649 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8655 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8659 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8667 * end up in the driver. tp->{tx,}lock are held and thus
8677 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8678 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8680 tnapi->last_tag = 0; in tg3_init_rings()
8681 tnapi->last_irq_tag = 0; in tg3_init_rings()
8682 tnapi->hw_status->status = 0; in tg3_init_rings()
8683 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8684 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8686 tnapi->tx_prod = 0; in tg3_init_rings()
8687 tnapi->tx_cons = 0; in tg3_init_rings()
8688 if (tnapi->tx_ring) in tg3_init_rings()
8689 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8691 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8692 if (tnapi->rx_rcb) in tg3_init_rings()
8693 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8695 if (tnapi->prodring.rx_std && in tg3_init_rings()
8696 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8698 return -ENOMEM; in tg3_init_rings()
8709 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8710 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8712 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8713 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8714 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8715 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8718 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8719 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8726 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8734 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8735 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8738 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8741 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8743 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8745 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8753 return -ENOMEM; in tg3_mem_tx_acquire()
8760 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8761 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8763 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8765 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8768 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8770 tnapi->rx_rcb, in tg3_mem_rx_release()
8771 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8772 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8780 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8789 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8791 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8801 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8803 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8805 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8813 return -ENOMEM; in tg3_mem_rx_acquire()
8824 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8825 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8827 if (tnapi->hw_status) { in tg3_free_consistent()
8828 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8829 tnapi->hw_status, in tg3_free_consistent()
8830 tnapi->status_mapping); in tg3_free_consistent()
8831 tnapi->hw_status = NULL; in tg3_free_consistent()
8838 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8840 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8842 if (tp->hw_stats) { in tg3_free_consistent()
8843 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8844 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8845 tp->hw_stats = NULL; in tg3_free_consistent()
8857 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8859 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8860 if (!tp->hw_stats) in tg3_alloc_consistent()
8863 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8864 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8867 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8869 &tnapi->status_mapping, in tg3_alloc_consistent()
8871 if (!tnapi->hw_status) in tg3_alloc_consistent()
8874 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8887 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8890 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8893 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8896 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8899 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8901 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8912 return -ENOMEM; in tg3_alloc_consistent()
8918 * clears. tp->lock is held.
8947 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8948 dev_err(&tp->pdev->dev, in tg3_stop_block()
8952 return -ENODEV; in tg3_stop_block()
8962 dev_err(&tp->pdev->dev, in tg3_stop_block()
8965 return -ENODEV; in tg3_stop_block()
8971 /* tp->lock is held. */
8978 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8979 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8980 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8981 err = -ENODEV; in tg3_abort_hw()
8985 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8986 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
9004 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
9005 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
9008 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
9009 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
9017 dev_err(&tp->pdev->dev, in tg3_abort_hw()
9020 err |= -ENODEV; in tg3_abort_hw()
9034 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
9035 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
9036 if (tnapi->hw_status) in tg3_abort_hw()
9037 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
9046 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
9054 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
9055 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
9056 tp->misc_host_ctrl); in tg3_restore_pci_state()
9068 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
9070 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
9073 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
9074 tp->pci_cacheline_sz); in tg3_restore_pci_state()
9075 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
9076 tp->pci_lat_timer); in tg3_restore_pci_state()
9079 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
9083 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9086 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9098 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9099 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9101 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9102 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9153 /* tp->lock is held. */
9155 __releases(tp->lock) in tg3_chip_reset()
9156 __acquires(tp->lock) in tg3_chip_reset()
9162 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9163 return -ENODEV; in tg3_chip_reset()
9172 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9174 /* GRC_MISC_CFG core clock reset will clear the memory in tg3_chip_reset()
9190 write_op = tp->write32; in tg3_chip_reset()
9192 tp->write32 = tg3_write32; in tg3_chip_reset()
9201 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9202 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9203 if (tnapi->hw_status) { in tg3_chip_reset()
9204 tnapi->hw_status->status = 0; in tg3_chip_reset()
9205 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9207 tnapi->last_tag = 0; in tg3_chip_reset()
9208 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9214 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9215 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9247 /* Set the clock to the highest frequency to avoid timeouts. With link in tg3_chip_reset()
9248 * aware mode, the clock speed could be slow and bootcode does not in tg3_chip_reset()
9249 * complete within the expected time. Override the clock to allow the in tg3_chip_reset()
9261 tp->write32 = write_op; in tg3_chip_reset()
9284 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9288 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9299 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9300 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9312 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9315 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9351 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9359 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9361 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9363 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9364 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9367 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9368 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9369 val = tp->mac_mode; in tg3_chip_reset()
9370 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9371 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9372 val = tp->mac_mode; in tg3_chip_reset()
9394 /* Increase the core clock speed to fix tx timeout issue for 5762 in tg3_chip_reset()
9405 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9416 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9422 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9424 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9435 /* tp->lock is held. */
9452 if (tp->hw_stats) { in tg3_halt()
9454 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9455 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9458 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9461 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_halt()
9463 tnapi->rx_dropped = 0; in tg3_halt()
9464 tnapi->tx_dropped = 0; in tg3_halt()
9478 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9479 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9481 eth_hw_addr_set(dev, addr->sa_data); in tg3_set_mac_addr()
9499 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9502 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9507 /* tp->lock is held. */
9534 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9535 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9536 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9542 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9546 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9548 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9550 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9554 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9564 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9567 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9568 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9569 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9570 limit--; in tg3_coal_rx_init()
9581 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9583 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9585 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9588 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9601 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9603 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9604 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9606 if (!tp->link_up) in __tg3_set_coalesce()
9613 /* tp->lock is held. */
9635 /* tp->lock is held. */
9644 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9645 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9647 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9650 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9656 /* tp->lock is held. */
9679 /* tp->lock is held. */
9688 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9689 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9691 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9694 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9695 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9700 /* tp->lock is held. */
9705 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9712 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9713 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9714 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9715 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9719 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9720 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9721 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9723 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9724 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9725 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9726 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9727 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9728 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9731 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9733 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9734 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9735 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9736 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9739 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9747 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9751 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9753 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9757 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9758 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9764 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9787 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9788 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9801 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9829 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9840 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9843 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9858 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9873 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9879 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9885 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9886 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9897 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9907 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9908 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9914 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9919 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9928 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9932 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9947 /* tp->lock is held. */
9952 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9963 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9964 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9967 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9971 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
10085 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10086 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10132 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10138 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10141 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10145 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10147 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10148 * the offload processors, so make the chip do the pseudo- in tg3_reset_hw()
10150 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10153 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10156 if (tp->rxptpctl) in tg3_reset_hw()
10158 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10163 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10169 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10170 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10175 /* Setup the timer prescalar register. Clock is always 66Mhz. */ in tg3_reset_hw()
10195 fw_len = tp->fw_len; in tg3_reset_hw()
10196 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10200 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10203 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10205 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10207 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10209 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10212 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10214 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10216 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10219 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10221 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10238 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10239 return -ENODEV; in tg3_reset_hw()
10265 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10267 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10285 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10287 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10313 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10314 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10316 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10317 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10318 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10327 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10381 tp->dma_limit = 0; in tg3_reset_hw()
10382 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10384 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10470 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10478 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10480 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10494 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10501 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10502 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10508 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10512 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10514 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10516 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10517 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10520 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10540 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10541 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10545 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10548 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10554 if (tp->irq_cnt > 1) in tg3_reset_hw()
10597 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10606 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10673 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10677 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10682 tp->tx_mode &= ~val; in tg3_reset_hw()
10683 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10686 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10700 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10702 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10705 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10708 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10715 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10718 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10721 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10725 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10728 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10730 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10732 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10752 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10753 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10757 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10763 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10764 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10765 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10769 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10770 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10776 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10777 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10789 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10802 limit -= 4; in tg3_reset_hw()
10862 * packet processing. Invoked with tp->lock held.
10889 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10890 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10903 spin_lock_bh(&tp->lock); in tg3_show_temp()
10904 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10906 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10928 if (tp->hwmon_dev) { in tg3_hwmon_close()
10929 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10930 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10938 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10954 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10956 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10957 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10958 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10969 (PSTAT)->low += __val; \
10970 if ((PSTAT)->low < __val) \
10971 (PSTAT)->high += 1; \
10976 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10978 if (!tp->link_up) in tg3_periodic_fetch_stats()
10981 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10982 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10983 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10984 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10985 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10986 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10987 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10988 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10989 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10990 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10991 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10992 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10993 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10995 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10996 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
11005 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
11006 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
11007 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
11008 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
11009 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
11010 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
11011 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
11012 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
11013 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
11014 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
11015 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
11016 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
11017 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
11018 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
11020 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
11025 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
11031 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
11032 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
11033 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
11035 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
11037 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
11044 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
11045 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
11048 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
11049 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
11050 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
11051 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
11057 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
11058 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
11059 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
11067 spin_lock(&tp->lock); in tg3_timer()
11069 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
11070 spin_unlock(&tp->lock); in tg3_timer()
11084 /* All of this garbage is because when using non-tagged in tg3_timer()
11088 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11090 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11092 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11097 spin_unlock(&tp->lock); in tg3_timer()
11104 if (!--tp->timer_counter) { in tg3_timer()
11108 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11118 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11130 if (tp->link_up && in tg3_timer()
11134 if (!tp->link_up && in tg3_timer()
11140 if (!tp->serdes_counter) { in tg3_timer()
11142 (tp->mac_mode & in tg3_timer()
11145 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11150 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11158 if (link_up != tp->link_up) in tg3_timer()
11162 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11182 if (!--tp->asf_counter) { in tg3_timer()
11194 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11200 spin_unlock(&tp->lock); in tg3_timer()
11203 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11204 add_timer(&tp->timer); in tg3_timer()
11212 tp->timer_offset = HZ; in tg3_timer_init()
11214 tp->timer_offset = HZ / 10; in tg3_timer_init()
11216 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11218 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11219 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11222 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11227 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11228 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11230 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11231 add_timer(&tp->timer); in tg3_timer_start()
11236 timer_delete_sync(&tp->timer); in tg3_timer_stop()
11239 /* Restart hardware after configuration changes, self-test, etc.
11240 * Invoked with tp->lock held.
11243 __releases(tp->lock) in tg3_restart_hw()
11244 __acquires(tp->lock) in tg3_restart_hw()
11245 __releases(tp->dev->lock) in tg3_restart_hw()
11246 __acquires(tp->dev->lock) in tg3_restart_hw()
11252 netdev_err(tp->dev, in tg3_restart_hw()
11253 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11257 tp->irq_sync = 0; in tg3_restart_hw()
11259 netdev_unlock(tp->dev); in tg3_restart_hw()
11260 dev_close(tp->dev); in tg3_restart_hw()
11261 netdev_lock(tp->dev); in tg3_restart_hw()
11275 if (tp->pcierr_recovery || !netif_running(tp->dev) || in tg3_reset_task()
11276 tp->pdev->error_state != pci_channel_io_normal) { in tg3_reset_task()
11289 netdev_lock(tp->dev); in tg3_reset_task()
11293 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11294 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11303 tp->irq_sync = 0; in tg3_reset_task()
11309 netdev_unlock(tp->dev); in tg3_reset_task()
11310 dev_close(tp->dev); in tg3_reset_task()
11316 netdev_unlock(tp->dev); in tg3_reset_task()
11328 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11330 if (tp->irq_cnt == 1) in tg3_request_irq()
11331 name = tp->dev->name; in tg3_request_irq()
11333 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11334 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11335 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11336 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11337 else if (tnapi->tx_buffers) in tg3_request_irq()
11338 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11339 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11340 else if (tnapi->rx_rcb) in tg3_request_irq()
11341 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11342 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11344 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11345 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11360 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11365 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11366 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11371 return -ENODEV; in tg3_test_interrupt()
11375 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11386 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11387 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11391 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11394 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11395 tnapi->coal_now); in tg3_test_interrupt()
11400 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11410 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11411 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11418 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11434 return -EIO; in tg3_test_interrupt()
11451 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11452 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11457 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11463 if (err != -EIO) in tg3_test_msi()
11467 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11471 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11473 pci_disable_msi(tp->pdev); in tg3_test_msi()
11476 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11493 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11502 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11503 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11504 tp->fw_needed); in tg3_request_firmware()
11505 return -ENOENT; in tg3_request_firmware()
11508 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11515 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11516 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11517 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11518 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11519 release_firmware(tp->fw); in tg3_request_firmware()
11520 tp->fw = NULL; in tg3_request_firmware()
11521 return -EINVAL; in tg3_request_firmware()
11525 tp->fw_needed = NULL; in tg3_request_firmware()
11531 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11535 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11539 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11550 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11551 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11552 if (!tp->rxq_cnt) in tg3_enable_msix()
11553 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11554 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11555 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11557 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11561 if (!tp->txq_req) in tg3_enable_msix()
11562 tp->txq_cnt = 1; in tg3_enable_msix()
11564 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11566 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11571 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11574 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11575 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11576 tp->irq_cnt, rc); in tg3_enable_msix()
11577 tp->irq_cnt = rc; in tg3_enable_msix()
11578 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11579 if (tp->txq_cnt) in tg3_enable_msix()
11580 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11583 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11584 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11586 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11587 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11591 if (tp->irq_cnt == 1) in tg3_enable_msix()
11596 if (tp->txq_cnt > 1) in tg3_enable_msix()
11599 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11611 netdev_warn(tp->dev, in tg3_ints_init()
11618 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11623 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11631 tp->irq_cnt = 1; in tg3_ints_init()
11632 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11635 if (tp->irq_cnt == 1) { in tg3_ints_init()
11636 tp->txq_cnt = 1; in tg3_ints_init()
11637 tp->rxq_cnt = 1; in tg3_ints_init()
11638 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11639 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11646 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11648 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11658 struct net_device *dev = tp->dev; in tg3_start()
11682 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11685 for (i--; i >= 0; i--) { in tg3_start()
11686 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11688 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11750 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11751 tg3_set_loopback(dev, dev->features); in tg3_start()
11756 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11757 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11758 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11795 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11796 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11797 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11812 if (tp->pcierr_recovery) { in tg3_open()
11815 return -EAGAIN; in tg3_open()
11818 if (tp->fw_needed) { in tg3_open()
11822 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11823 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11824 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11825 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11826 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11832 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11835 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11854 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11858 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11868 if (tp->pcierr_recovery) { in tg3_close()
11871 return -EAGAIN; in tg3_close()
11876 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11886 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11891 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11893 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11905 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11907 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11910 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11914 estats->member = old_estats->member + \
11915 get_stat64(&hw_stats->member)
11919 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11920 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
12003 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
12004 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
12009 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
12010 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
12011 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
12012 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
12014 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
12015 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
12016 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
12017 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
12019 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
12020 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
12021 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
12022 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
12024 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
12025 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
12026 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
12027 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
12028 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
12029 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
12030 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
12032 stats->multicast = old_stats->multicast + in tg3_get_nstats()
12033 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
12034 stats->collisions = old_stats->collisions + in tg3_get_nstats()
12035 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
12037 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
12038 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
12039 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
12041 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
12042 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
12043 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
12044 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
12045 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
12046 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
12048 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
12051 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
12052 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
12054 /* Aggregate per-queue counters. The per-queue counters are updated in tg3_get_nstats()
12055 * by a single writer, race-free. The result computed by this loop in tg3_get_nstats()
12062 rx_dropped = (unsigned long)(old_stats->rx_dropped); in tg3_get_nstats()
12063 tx_dropped = (unsigned long)(old_stats->tx_dropped); in tg3_get_nstats()
12065 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
12066 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_get_nstats()
12068 rx_dropped += tnapi->rx_dropped; in tg3_get_nstats()
12069 tx_dropped += tnapi->tx_dropped; in tg3_get_nstats()
12072 stats->rx_dropped = rx_dropped; in tg3_get_nstats()
12073 stats->tx_dropped = tx_dropped; in tg3_get_nstats()
12086 regs->version = 0; in tg3_get_regs()
12090 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
12104 return tp->nvram_size; in tg3_get_eeprom_len()
12116 return -EINVAL; in tg3_get_eeprom()
12118 offset = eeprom->offset; in tg3_get_eeprom()
12119 len = eeprom->len; in tg3_get_eeprom()
12120 eeprom->len = 0; in tg3_get_eeprom()
12122 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12124 /* Override clock, link aware and link idle modes */ in tg3_get_eeprom()
12140 b_count = 4 - b_offset; in tg3_get_eeprom()
12145 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12149 len -= b_count; in tg3_get_eeprom()
12151 eeprom->len += b_count; in tg3_get_eeprom()
12155 pd = &data[eeprom->len]; in tg3_get_eeprom()
12156 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12160 i -= 4; in tg3_get_eeprom()
12161 eeprom->len += i; in tg3_get_eeprom()
12167 eeprom->len += i; in tg3_get_eeprom()
12168 ret = -EINTR; in tg3_get_eeprom()
12174 eeprom->len += i; in tg3_get_eeprom()
12178 pd = &data[eeprom->len]; in tg3_get_eeprom()
12180 b_offset = offset + len - b_count; in tg3_get_eeprom()
12185 eeprom->len += b_count; in tg3_get_eeprom()
12190 /* Restore clock, link aware and link idle modes */ in tg3_get_eeprom()
12207 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12208 return -EINVAL; in tg3_set_eeprom()
12210 offset = eeprom->offset; in tg3_set_eeprom()
12211 len = eeprom->len; in tg3_set_eeprom()
12215 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12229 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12238 return -ENOMEM; in tg3_set_eeprom()
12242 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12243 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12262 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12263 return -EAGAIN; in tg3_get_link_ksettings()
12264 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12272 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12276 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12282 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12285 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12287 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12290 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12292 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12293 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12299 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12303 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12306 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12307 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12308 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12310 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12311 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12313 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12314 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12315 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12317 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12320 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12321 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12322 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12324 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12325 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12333 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12338 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12339 return -EAGAIN; in tg3_set_link_ksettings()
12340 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12344 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12345 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12346 return -EINVAL; in tg3_set_link_ksettings()
12348 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12349 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12350 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12351 return -EINVAL; in tg3_set_link_ksettings()
12354 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12356 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12361 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12365 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12375 return -EINVAL; in tg3_set_link_ksettings()
12386 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12388 return -EINVAL; in tg3_set_link_ksettings()
12390 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12391 return -EINVAL; in tg3_set_link_ksettings()
12395 return -EINVAL; in tg3_set_link_ksettings()
12401 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12402 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12403 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12405 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12406 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12408 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12409 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12410 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12413 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12429 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12430 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12431 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12438 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12439 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12441 wol->supported = 0; in tg3_get_wol()
12442 wol->wolopts = 0; in tg3_get_wol()
12443 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12444 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12445 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12451 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12453 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12454 return -EINVAL; in tg3_set_wol()
12455 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12457 return -EINVAL; in tg3_set_wol()
12459 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12472 return tp->msg_enable; in tg3_get_msglevel()
12478 tp->msg_enable = value; in tg3_set_msglevel()
12487 return -EAGAIN; in tg3_nway_reset()
12489 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12490 return -EINVAL; in tg3_nway_reset()
12495 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12496 return -EAGAIN; in tg3_nway_reset()
12497 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12501 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12502 r = -EINVAL; in tg3_nway_reset()
12506 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12511 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12524 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12526 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12528 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12530 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12532 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12534 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12536 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12538 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12550 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12551 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12552 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12553 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12555 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12556 return -EINVAL; in tg3_set_ringparam()
12567 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12570 tp->rx_pending > 63) in tg3_set_ringparam()
12571 tp->rx_pending = 63; in tg3_set_ringparam()
12574 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12576 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12577 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12605 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12607 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12608 epause->rx_pause = 1; in tg3_get_pauseparam()
12610 epause->rx_pause = 0; in tg3_get_pauseparam()
12612 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12613 epause->tx_pause = 1; in tg3_get_pauseparam()
12615 epause->tx_pause = 0; in tg3_get_pauseparam()
12624 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12630 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12633 return -EINVAL; in tg3_set_pauseparam()
12635 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12636 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause); in tg3_set_pauseparam()
12637 if (epause->rx_pause) { in tg3_set_pauseparam()
12638 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12640 if (epause->tx_pause) { in tg3_set_pauseparam()
12641 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12643 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12644 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12647 if (epause->autoneg) in tg3_set_pauseparam()
12652 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12653 if (phydev->autoneg) { in tg3_set_pauseparam()
12664 if (!epause->autoneg) in tg3_set_pauseparam()
12678 if (epause->autoneg) in tg3_set_pauseparam()
12682 if (epause->rx_pause) in tg3_set_pauseparam()
12683 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12685 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12686 if (epause->tx_pause) in tg3_set_pauseparam()
12687 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12689 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12708 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12721 return -EOPNOTSUPP; in tg3_get_sset_count()
12731 return -EOPNOTSUPP; in tg3_get_rxnfc()
12733 switch (info->cmd) { in tg3_get_rxnfc()
12735 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12736 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12738 info->data = num_online_cpus(); in tg3_get_rxnfc()
12739 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12740 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12746 return -EOPNOTSUPP; in tg3_get_rxnfc()
12766 rxfh->hfunc = ETH_RSS_HASH_TOP; in tg3_get_rxfh()
12767 if (!rxfh->indir) in tg3_get_rxfh()
12771 rxfh->indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12785 if (rxfh->key || in tg3_set_rxfh()
12786 (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && in tg3_set_rxfh()
12787 rxfh->hfunc != ETH_RSS_HASH_TOP)) in tg3_set_rxfh()
12788 return -EOPNOTSUPP; in tg3_set_rxfh()
12790 if (!rxfh->indir) in tg3_set_rxfh()
12794 tp->rss_ind_tbl[i] = rxfh->indir[i]; in tg3_set_rxfh()
12815 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12816 channel->max_tx = tp->txq_max; in tg3_get_channels()
12819 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12820 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12822 if (tp->rxq_req) in tg3_get_channels()
12823 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12825 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12827 if (tp->txq_req) in tg3_get_channels()
12828 channel->tx_count = tp->txq_req; in tg3_get_channels()
12830 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12840 return -EOPNOTSUPP; in tg3_set_channels()
12842 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12843 channel->tx_count > tp->txq_max) in tg3_set_channels()
12844 return -EINVAL; in tg3_set_channels()
12846 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12847 tp->txq_req = channel->tx_count; in tg3_set_channels()
12901 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12913 if (tp->hw_stats) in tg3_get_ethtool_stats()
12959 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12960 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12968 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
13001 return -EIO; in tg3_test_nvram()
13028 return -EIO; in tg3_test_nvram()
13035 return -EIO; in tg3_test_nvram()
13039 return -ENOMEM; in tg3_test_nvram()
13041 err = -EIO; in tg3_test_nvram()
13073 err = -EIO; in tg3_test_nvram()
13107 err = -EIO; in tg3_test_nvram()
13120 err = -EIO; in tg3_test_nvram()
13140 return -ENOMEM; in tg3_test_nvram()
13158 if (!netif_running(tp->dev)) in tg3_test_link()
13159 return -ENODEV; in tg3_test_link()
13161 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13167 if (tp->link_up) in tg3_test_link()
13174 return -EIO; in tg3_test_link()
13355 /* Determine the read-only value. */ in tg3_test_registers()
13358 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13365 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13370 * make sure the read-only bits are not changed and the in tg3_test_registers()
13377 /* Test the read-only bits. */ in tg3_test_registers()
13392 netdev_err(tp->dev, in tg3_test_registers()
13395 return -EIO; in tg3_test_registers()
13411 return -EIO; in tg3_do_mem_test()
13521 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13523 tnapi = &tp->napi[0]; in tg3_run_loopback()
13524 rnapi = &tp->napi[0]; in tg3_run_loopback()
13525 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13527 rnapi = &tp->napi[1]; in tg3_run_loopback()
13529 tnapi = &tp->napi[1]; in tg3_run_loopback()
13531 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13533 err = -EIO; in tg3_run_loopback()
13536 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13538 return -ENOMEM; in tg3_run_loopback()
13541 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13556 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13560 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13571 th->check = 0; in tg3_run_loopback()
13602 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13603 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13605 return -EIO; in tg3_run_loopback()
13608 val = tnapi->tx_prod; in tg3_run_loopback()
13609 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13610 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13612 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13613 rnapi->coal_now); in tg3_run_loopback()
13617 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13622 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13624 return -EIO; in tg3_run_loopback()
13627 tnapi->tx_prod++; in tg3_run_loopback()
13632 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13633 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13639 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13644 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13645 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13646 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13651 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13654 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13662 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13663 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13664 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13666 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13667 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13670 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13671 - ETH_FCS_LEN; in tg3_run_loopback()
13677 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13684 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13685 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13691 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13692 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13695 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13696 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13701 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13728 int err = -EIO; in tg3_test_loopback()
13732 if (tp->dma_limit) in tg3_test_loopback()
13733 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13735 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13736 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13738 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13764 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13783 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13827 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13828 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13833 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13836 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13845 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13847 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13849 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13859 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13863 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13866 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13884 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13888 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13893 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13898 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13901 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13906 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13927 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13938 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13940 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) in tg3_hwtstamp_set()
13941 return -EFAULT; in tg3_hwtstamp_set()
13945 return -ERANGE; in tg3_hwtstamp_set()
13949 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13952 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13956 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13960 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13964 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13968 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13972 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13976 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13980 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13984 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13988 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13992 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13996 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
14000 return -ERANGE; in tg3_hwtstamp_set()
14003 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
14005 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
14012 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_set()
14013 -EFAULT : 0; in tg3_hwtstamp_set()
14022 return -EOPNOTSUPP; in tg3_hwtstamp_get()
14028 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
14070 return -ERANGE; in tg3_hwtstamp_get()
14073 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_get()
14074 -EFAULT : 0; in tg3_hwtstamp_get()
14085 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14086 return -EAGAIN; in tg3_ioctl()
14087 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14093 data->phy_id = tp->phy_addr; in tg3_ioctl()
14099 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14103 return -EAGAIN; in tg3_ioctl()
14105 spin_lock_bh(&tp->lock); in tg3_ioctl()
14106 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14107 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14108 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14110 data->val_out = mii_regval; in tg3_ioctl()
14116 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14120 return -EAGAIN; in tg3_ioctl()
14122 spin_lock_bh(&tp->lock); in tg3_ioctl()
14123 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14124 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14125 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14139 return -EOPNOTSUPP; in tg3_ioctl()
14149 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14169 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14170 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14171 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14172 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14173 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14174 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14175 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14176 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14177 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14178 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14179 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14180 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14181 return -EINVAL; in tg3_set_coalesce()
14184 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14185 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14186 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14187 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14188 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14189 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14190 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14191 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14192 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14196 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14206 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14207 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14208 return -EOPNOTSUPP; in tg3_set_eee()
14211 if (!linkmode_equal(edata->advertised, tp->eee.advertised)) { in tg3_set_eee()
14212 netdev_warn(tp->dev, in tg3_set_eee()
14214 return -EINVAL; in tg3_set_eee()
14217 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14218 netdev_warn(tp->dev, in tg3_set_eee()
14221 return -EINVAL; in tg3_set_eee()
14224 tp->eee.eee_enabled = edata->eee_enabled; in tg3_set_eee()
14225 tp->eee.tx_lpi_enabled = edata->tx_lpi_enabled; in tg3_set_eee()
14226 tp->eee.tx_lpi_timer = edata->tx_lpi_timer; in tg3_set_eee()
14228 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14231 if (netif_running(tp->dev)) { in tg3_set_eee()
14245 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14246 netdev_warn(tp->dev, in tg3_get_eee()
14248 return -EOPNOTSUPP; in tg3_get_eee()
14251 *edata = tp->eee; in tg3_get_eee()
14302 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14303 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14304 *stats = tp->net_stats_prev; in tg3_get_stats64()
14305 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14310 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14328 WRITE_ONCE(dev->mtu, new_mtu); in tg3_set_mtu()
14416 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14433 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14443 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14462 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14466 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14469 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14472 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14476 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14495 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14496 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14500 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14501 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14504 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14505 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14509 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14510 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14514 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14515 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14519 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14520 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14524 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14525 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14534 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14537 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14540 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14543 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14546 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14549 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14552 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14570 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14574 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14581 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14591 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14616 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14619 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14622 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14625 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14628 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14634 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14637 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14639 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14643 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14647 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14665 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14667 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14676 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14679 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14684 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14687 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14714 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14718 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14728 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14731 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14736 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14743 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14749 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14755 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14761 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14769 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14771 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14783 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14785 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14797 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14805 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14809 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14813 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14820 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14826 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14829 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14832 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14842 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14856 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14858 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14870 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14880 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14883 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14897 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14908 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14911 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14921 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14944 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14945 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14950 tp->nvram_size = in tg3_get_5720_nvram_info()
14974 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14980 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14982 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14996 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
15004 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
15009 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
15013 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
15017 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15039 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
15048 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
15054 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
15060 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
15064 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15074 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
15117 netdev_warn(tp->dev, in tg3_nvram_init()
15124 tp->nvram_size = 0; in tg3_nvram_init()
15150 if (tp->nvram_size == 0) in tg3_nvram_init()
15239 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15241 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15251 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15252 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15269 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15282 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15315 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15318 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15320 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15332 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15336 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15340 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15347 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15352 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15355 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15360 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15366 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15370 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15372 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15380 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15381 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15384 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15388 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15390 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15391 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15408 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15415 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15419 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15421 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15424 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15430 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15441 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15443 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15454 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15458 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15461 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15494 return -EBUSY; in tg3_ape_otp_read()
15513 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15517 * configuration is a 32-bit value that straddles the alignment boundary.
15518 * We do two 32-bit reads and then shift and merge the results.
15550 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15551 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15556 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15565 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15566 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15567 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15568 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15569 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15570 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15572 tp->old_link = -1; in tg3_phy_init_link_config()
15583 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15586 switch (tp->pci_fn) { in tg3_phy_probe()
15588 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15591 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15594 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15597 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15603 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15604 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15605 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15620 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15634 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15636 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15638 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15640 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15652 tp->phy_id = p->phy_id; in tg3_phy_probe()
15661 return -ENODEV; in tg3_phy_probe()
15664 if (!tp->phy_id || in tg3_phy_probe()
15665 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15666 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15670 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15679 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15681 linkmode_zero(tp->eee.supported); in tg3_phy_probe()
15683 tp->eee.supported); in tg3_phy_probe()
15685 tp->eee.supported); in tg3_phy_probe()
15686 linkmode_copy(tp->eee.advertised, tp->eee.supported); in tg3_phy_probe()
15688 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15689 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15690 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15695 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15696 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15713 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15714 tp->link_config.flowctrl); in tg3_phy_probe()
15722 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15756 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15757 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15768 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15772 if (tp->board_part_number[0]) in tg3_read_vpd()
15777 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15778 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15779 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15780 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15781 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15785 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15786 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15787 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15788 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15789 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15790 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15791 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15792 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15796 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15797 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15798 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15799 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15800 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15801 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15802 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15803 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15804 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15805 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15806 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15807 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15811 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15812 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15813 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15814 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15815 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15816 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15817 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15818 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15822 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15825 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15865 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15868 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15872 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15878 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15889 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15907 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15914 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15954 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15955 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15959 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15960 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15961 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15985 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15993 offset += val - start; in tg3_read_mgmtfw_ver()
15995 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15997 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15998 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
16007 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
16008 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
16012 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
16043 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
16048 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
16050 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
16078 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16079 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16088 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16092 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16117 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16140 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16143 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16144 if (peer && peer != tp->pdev) in tg3_find_peer()
16148 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16149 * tp->pdev in that case. in tg3_find_peer()
16152 peer = tp->pdev; in tg3_find_peer()
16167 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16176 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16177 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16178 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16179 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16180 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16181 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16182 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16183 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16184 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16185 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16188 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16189 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16190 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16191 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16192 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16193 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16194 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16195 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16196 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16197 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16202 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16209 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16212 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16260 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16263 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16265 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16290 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16292 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16294 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16299 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16301 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16303 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16304 tp->misc_host_ctrl); in tg3_get_invariants()
16314 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16317 * non-zero address during special cycles. However, only in tg3_get_invariants()
16318 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16345 while (pci_id->vendor != 0) { in tg3_get_invariants()
16346 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16352 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16353 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16356 if (bridge->subordinate && in tg3_get_invariants()
16357 (bridge->subordinate->number == in tg3_get_invariants()
16358 tp->pdev->bus->number)) { in tg3_get_invariants()
16378 while (pci_id->vendor != 0) { in tg3_get_invariants()
16379 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16380 pci_id->device, in tg3_get_invariants()
16386 if (bridge->subordinate && in tg3_get_invariants()
16387 (bridge->subordinate->number <= in tg3_get_invariants()
16388 tp->pdev->bus->number) && in tg3_get_invariants()
16389 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16390 tp->pdev->bus->number)) { in tg3_get_invariants()
16399 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16400 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16401 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16406 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16414 if (bridge && bridge->subordinate && in tg3_get_invariants()
16415 (bridge->subordinate->number <= in tg3_get_invariants()
16416 tp->pdev->bus->number) && in tg3_get_invariants()
16417 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16418 tp->pdev->bus->number)) { in tg3_get_invariants()
16428 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16450 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16452 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16468 tp->fw_needed = NULL; in tg3_get_invariants()
16472 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16475 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16477 tp->irq_max = 1; in tg3_get_invariants()
16485 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16495 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16499 tp->txq_max = 1; in tg3_get_invariants()
16500 tp->rxq_max = 1; in tg3_get_invariants()
16501 if (tp->irq_max > 1) { in tg3_get_invariants()
16502 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16507 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16515 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16532 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16535 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16540 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16562 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16563 if (!tp->pcix_cap) { in tg3_get_invariants()
16564 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16565 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16566 return -EIO; in tg3_get_invariants()
16583 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16584 &tp->pci_cacheline_sz); in tg3_get_invariants()
16585 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16586 &tp->pci_lat_timer); in tg3_get_invariants()
16588 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16589 tp->pci_lat_timer = 64; in tg3_get_invariants()
16590 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16591 tp->pci_lat_timer); in tg3_get_invariants()
16594 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16603 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16617 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16618 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16622 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16623 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16627 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16629 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16638 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16642 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16646 tp->read32 = tg3_read32; in tg3_get_invariants()
16647 tp->write32 = tg3_write32; in tg3_get_invariants()
16648 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16649 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16650 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16651 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16655 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16666 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16670 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16672 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16676 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16677 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16678 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16679 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16680 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16681 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16683 iounmap(tp->regs); in tg3_get_invariants()
16684 tp->regs = NULL; in tg3_get_invariants()
16686 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16688 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16691 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16692 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16693 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16694 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16697 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16711 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16715 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16716 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16718 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16728 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16730 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16735 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16736 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16752 tp->fw_needed = NULL; in tg3_get_invariants()
16762 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16766 tp->ape_hb_interval = in tg3_get_invariants()
16770 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16775 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16778 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16781 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16784 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16789 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16791 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16792 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16794 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16797 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16802 tp->grc_local_ctrl |= in tg3_get_invariants()
16811 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16825 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16832 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16833 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16834 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16838 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16840 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16843 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16851 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16852 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16853 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16854 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16855 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16857 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16862 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16863 if (tp->phy_otp == 0) in tg3_get_invariants()
16864 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16868 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16870 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16872 tp->coalesce_mode = 0; in tg3_get_invariants()
16875 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16882 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16883 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16906 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16916 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16930 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16946 tp->fw_needed = NULL; in tg3_get_invariants()
16960 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16963 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16964 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16965 tp->misc_host_ctrl); in tg3_get_invariants()
16970 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16972 tp->mac_mode = 0; in tg3_get_invariants()
16975 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16979 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16987 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16988 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16991 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16993 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
17009 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
17011 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
17012 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
17017 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
17025 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
17026 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
17029 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
17031 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
17035 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
17036 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
17037 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
17039 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
17047 tp->rx_std_max_post = 8; in tg3_get_invariants()
17050 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
17062 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
17066 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
17081 if (tp->pci_fn & 1) in tg3_get_device_address()
17083 if (tp->pci_fn > 1) in tg3_get_device_address()
17128 return -EINVAL; in tg3_get_device_address()
17141 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17174 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17177 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17178 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17308 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17327 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17329 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17331 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17338 ret = -ENODEV; in tg3_do_test_dma()
17370 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17373 ret = -ENOMEM; in tg3_test_dma()
17377 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17380 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17387 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17391 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17393 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17406 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17408 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17413 tp->dma_rwctrl |= in tg3_test_dma()
17419 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17422 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17424 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17428 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17432 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17437 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17447 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17449 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17452 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17462 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17463 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17464 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17475 dev_err(&tp->pdev->dev, in tg3_test_dma()
17484 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17494 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17496 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17497 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17498 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17501 dev_err(&tp->pdev->dev, in tg3_test_dma()
17504 ret = -ENODEV; in tg3_test_dma()
17515 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17522 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17523 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17526 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17529 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17533 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17541 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17543 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17545 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17548 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17550 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17552 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17555 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17557 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17559 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17562 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17564 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17568 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17570 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17572 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17575 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17577 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17579 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17582 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17584 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17586 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17590 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17591 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17596 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17656 strcat(str, ":32-bit"); in tg3_bus_string()
17658 strcat(str, ":64-bit"); in tg3_bus_string()
17664 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17667 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17668 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17669 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17670 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17671 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17672 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17673 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17674 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17675 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17676 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17678 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17680 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17681 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17682 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17683 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17687 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17688 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17689 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17707 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17713 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17721 err = -ENOMEM; in tg3_init_one()
17725 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17728 tp->pdev = pdev; in tg3_init_one()
17729 tp->dev = dev; in tg3_init_one()
17730 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17731 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17732 tp->irq_sync = 1; in tg3_init_one()
17733 tp->pcierr_recovery = false; in tg3_init_one()
17736 tp->msg_enable = tg3_debug; in tg3_init_one()
17738 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17758 tp->misc_host_ctrl = in tg3_init_one()
17764 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17768 * are running in big-endian mode. in tg3_init_one()
17770 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17773 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17775 spin_lock_init(&tp->lock); in tg3_init_one()
17776 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17777 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17779 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17780 if (!tp->regs) { in tg3_init_one()
17781 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17782 err = -ENOMEM; in tg3_init_one()
17786 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17787 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17788 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17789 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17790 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17791 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17792 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17793 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17794 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17795 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17796 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17797 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17799 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17800 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17802 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17803 if (!tp->aperegs) { in tg3_init_one()
17804 dev_err(&pdev->dev, in tg3_init_one()
17806 err = -ENOMEM; in tg3_init_one()
17811 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17812 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17814 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17815 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17816 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17817 dev->irq = pdev->irq; in tg3_init_one()
17821 dev_err(&pdev->dev, in tg3_init_one()
17827 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17828 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17829 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17847 err = dma_set_mask(&pdev->dev, dma_mask); in tg3_init_one()
17850 err = dma_set_coherent_mask(&pdev->dev, in tg3_init_one()
17853 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17860 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in tg3_init_one()
17862 dev_err(&pdev->dev, in tg3_init_one()
17901 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17903 dev->vlan_features |= features; in tg3_init_one()
17907 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17915 dev->hw_features |= features; in tg3_init_one()
17916 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17918 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17919 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17920 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17926 tp->rx_pending = 63; in tg3_init_one()
17931 dev_err(&pdev->dev, in tg3_init_one()
17940 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17941 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17943 tnapi->tp = tp; in tg3_init_one()
17944 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17946 tnapi->int_mbox = intmbx; in tg3_init_one()
17949 tnapi->consmbox = rcvmbx; in tg3_init_one()
17950 tnapi->prodmbox = sndmbx; in tg3_init_one()
17953 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17955 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17973 sndmbx -= 0x4; in tg3_init_one()
17993 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
18012 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
18018 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
18019 &tp->pdev->dev); in tg3_init_one()
18020 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
18021 tp->ptp_clock = NULL; in tg3_init_one()
18025 tp->board_part_number, in tg3_init_one()
18028 dev->dev_addr); in tg3_init_one()
18030 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
18033 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
18034 ethtype = "10/100Base-TX"; in tg3_init_one()
18035 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
18036 ethtype = "1000Base-SX"; in tg3_init_one()
18038 ethtype = "10/100/1000Base-T"; in tg3_init_one()
18043 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
18044 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
18048 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
18050 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
18053 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
18054 tp->dma_rwctrl, in tg3_init_one()
18055 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
18056 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
18063 if (tp->aperegs) { in tg3_init_one()
18064 iounmap(tp->aperegs); in tg3_init_one()
18065 tp->aperegs = NULL; in tg3_init_one()
18069 if (tp->regs) { in tg3_init_one()
18070 iounmap(tp->regs); in tg3_init_one()
18071 tp->regs = NULL; in tg3_init_one()
18095 release_firmware(tp->fw); in tg3_remove_one()
18105 if (tp->aperegs) { in tg3_remove_one()
18106 iounmap(tp->aperegs); in tg3_remove_one()
18107 tp->aperegs = NULL; in tg3_remove_one()
18109 if (tp->regs) { in tg3_remove_one()
18110 iounmap(tp->regs); in tg3_remove_one()
18111 tp->regs = NULL; in tg3_remove_one()
18174 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18259 pdev->current_state != PCI_D3cold && in tg3_shutdown()
18260 pdev->current_state != PCI_UNKNOWN) { in tg3_shutdown()
18277 * tg3_io_error_detected - called when PCI error is detected
18299 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18304 tp->pcierr_recovery = true; in tg3_io_error_detected()
18338 * tg3_io_slot_reset - called after the pci bus has been reset.
18341 * Restart the card from scratch, as if from a cold-boot.
18356 dev_err(&pdev->dev, in tg3_io_slot_reset()
18357 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18389 * tg3_io_resume - called when traffic can start flowing again.
18430 tp->pcierr_recovery = false; in tg3_io_resume()