Lines Matching +full:fw +full:- +full:cfg +full:- +full:mmio
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
124 * and dev->tx_timeout() should be called to fix the problem
147 /* Do not place this n-ring entries value into the tp struct itself,
151 * replace things like '% foo' with '& (foo - 1)'.
155 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
162 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
165 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
198 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
202 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
208 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
473 writel(val, tp->regs + off); in tg3_write32()
478 return readl(tp->regs + off); in tg3_read32()
483 writel(val, tp->aperegs + off); in tg3_ape_write32()
488 return readl(tp->aperegs + off); in tg3_ape_read32()
495 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
498 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
503 writel(val, tp->regs + off); in tg3_write_flush_reg32()
504 readl(tp->regs + off); in tg3_write_flush_reg32()
512 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
515 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
534 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
537 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
554 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
557 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
569 /* Non-posted methods */ in _tw32_flush()
570 tp->write32(tp, off, val); in _tw32_flush()
576 tp->read32(tp, off); in _tw32_flush()
587 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
591 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
596 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
607 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
612 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
624 #define tr32(reg) tp->read32(tp, reg)
634 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
648 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
661 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
675 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
698 if (!tp->pci_fn) in tg3_ape_lock_init()
701 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
724 if (!tp->pci_fn) in tg3_ape_lock()
727 bit = 1 << tp->pci_fn; in tg3_ape_lock()
736 return -EINVAL; in tg3_ape_lock()
756 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
765 ret = -EBUSY; in tg3_ape_lock()
785 if (!tp->pci_fn) in tg3_ape_unlock()
788 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
814 return -EBUSY; in tg3_ape_event_lock()
823 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
826 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
857 return -ENODEV; in tg3_ape_scratchpad_read()
861 return -EAGAIN; in tg3_ape_scratchpad_read()
873 len -= length; in tg3_ape_scratchpad_read()
877 return -EAGAIN; in tg3_ape_scratchpad_read()
898 return -EAGAIN; in tg3_ape_scratchpad_read()
900 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
918 return -EAGAIN; in tg3_ape_send_event()
922 return -EAGAIN; in tg3_ape_send_event()
948 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
965 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
991 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
994 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
995 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1003 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1004 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1005 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1012 tp->irq_sync = 0; in tg3_enable_ints()
1016 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1018 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1019 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1020 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1022 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1024 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1026 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1031 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1032 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1034 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1036 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1041 struct tg3 *tp = tnapi->tp; in tg3_has_work()
1042 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1047 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1052 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1056 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1057 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1070 struct tg3 *tp = tnapi->tp; in tg3_int_reenable()
1072 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1079 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1080 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1097 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1125 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1127 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1131 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1153 loops -= 1; in __tg3_readphy()
1156 ret = -EBUSY; in __tg3_readphy()
1162 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1163 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1167 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1174 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1184 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1188 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1190 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1194 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1214 loops -= 1; in __tg3_writephy()
1217 ret = -EBUSY; in __tg3_writephy()
1221 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1222 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1226 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1233 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1363 return -EBUSY; in tg3_bmcr_reset()
1366 while (limit--) { in tg3_bmcr_reset()
1369 return -EBUSY; in tg3_bmcr_reset()
1378 return -EBUSY; in tg3_bmcr_reset()
1385 struct tg3 *tp = bp->priv; in tg3_mdio_read()
1388 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1391 val = -EIO; in tg3_mdio_read()
1393 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1400 struct tg3 *tp = bp->priv; in tg3_mdio_write()
1403 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1406 ret = -EIO; in tg3_mdio_write()
1408 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1418 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1419 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1437 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1496 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1497 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1514 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1522 tp->phy_addr += 7; in tg3_mdio_init()
1526 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1529 tp->phy_addr = addr; in tg3_mdio_init()
1531 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1538 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1539 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1540 return -ENOMEM; in tg3_mdio_init()
1542 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1543 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev)); in tg3_mdio_init()
1544 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1545 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1546 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1547 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1548 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1558 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1560 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1561 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1565 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1567 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1568 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1569 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1570 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1571 return -ENODEV; in tg3_mdio_init()
1574 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1576 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1577 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1581 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1587 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1591 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1592 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1593 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1609 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1610 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1614 /* tp->lock is held. */
1623 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1628 /* tp->lock is held. */
1636 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1637 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1651 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1658 /* tp->lock is held. */
1678 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1693 /* tp->lock is held. */
1715 /* tp->lock is held. */
1731 /* tp->lock is held. */
1760 /* tp->lock is held. */
1781 /* tp->lock is held. */
1825 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1826 return -ENODEV; in tg3_poll_fw()
1830 return -ENODEV; in tg3_poll_fw()
1838 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1841 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1858 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1873 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1874 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1877 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1878 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1880 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1882 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1885 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1891 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1892 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1893 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1898 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1965 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1966 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1969 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1971 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1974 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1979 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1981 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1984 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1986 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1988 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1989 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1992 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1994 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1996 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1997 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2005 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2007 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2009 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2012 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2014 if (phydev->link) { in tg3_adjust_link()
2018 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2020 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2026 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2030 tp->link_config.flowctrl); in tg3_adjust_link()
2032 if (phydev->pause) in tg3_adjust_link()
2034 if (phydev->asym_pause) in tg3_adjust_link()
2042 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2043 tp->mac_mode = mac_mode; in tg3_adjust_link()
2044 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2049 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2057 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2068 if (phydev->link != tp->old_link || in tg3_adjust_link()
2069 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2070 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2071 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2074 tp->old_link = phydev->link; in tg3_adjust_link()
2075 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2076 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2078 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2088 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2094 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2097 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2098 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2100 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2105 switch (phydev->interface) { in tg3_phy_init()
2108 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2119 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2120 return -EINVAL; in tg3_phy_init()
2123 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2134 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2137 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2139 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2140 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2141 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2142 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2143 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2145 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2155 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2158 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2163 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2164 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2165 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2174 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2177 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2178 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2225 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2228 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2255 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2258 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2296 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2309 if (!tp->phy_otp) in tg3_phy_apply_otp()
2312 otp = tp->phy_otp; in tg3_phy_apply_otp()
2345 struct ethtool_keee *dest = &tp->eee; in tg3_eee_pull_config()
2347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2359 dest->eee_active = 1; in tg3_eee_pull_config()
2361 dest->eee_active = 0; in tg3_eee_pull_config()
2366 mii_eee_cap1_mod_linkmode_t(dest->lp_advertised, val); in tg3_eee_pull_config()
2371 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2372 mii_eee_cap1_mod_linkmode_t(dest->advertised, val); in tg3_eee_pull_config()
2376 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2379 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2386 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2389 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2391 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2393 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2394 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2395 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2398 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2406 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2407 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2410 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2426 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2445 while (limit--) { in tg3_wait_macro_done()
2454 return -EBUSY; in tg3_wait_macro_done()
2483 return -EBUSY; in tg3_phy_write_and_check_testpat()
2491 return -EBUSY; in tg3_phy_write_and_check_testpat()
2497 return -EBUSY; in tg3_phy_write_and_check_testpat()
2507 return -EBUSY; in tg3_phy_write_and_check_testpat()
2517 return -EBUSY; in tg3_phy_write_and_check_testpat()
2539 return -EBUSY; in tg3_phy_reset_chanpat()
2567 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2588 } while (--retries); in tg3_phy_reset_5703_4_5()
2615 netif_carrier_off(tp->dev); in tg3_carrier_off()
2616 tp->link_up = false; in tg3_carrier_off()
2622 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2623 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2627 * link unless the FORCE argument is non-zero.
2642 return -EBUSY; in tg3_phy_reset()
2644 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2645 netif_carrier_off(tp->dev); in tg3_phy_reset()
2690 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2695 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2701 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2708 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2713 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2720 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2723 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2736 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2737 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2740 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2796 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2818 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2822 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2827 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2843 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2865 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2872 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2873 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2874 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2880 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2898 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2904 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2917 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2923 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2929 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2976 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2979 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3006 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3008 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3024 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3028 if (!tp->pci_fn) in tg3_phy_power_bug()
3033 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3034 !tp->pci_fn) in tg3_phy_power_bug()
3047 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3048 !tp->pci_fn) in tg3_phy_led_bug()
3060 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3063 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3082 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3130 /* tp->lock is held. */
3136 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3145 return -ENODEV; in tg3_nvram_lock()
3148 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3153 /* tp->lock is held. */
3157 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3158 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3159 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3164 /* tp->lock is held. */
3174 /* tp->lock is held. */
3191 return -EINVAL; in tg3_nvram_read_using_eeprom()
3211 return -EBUSY; in tg3_nvram_read_using_eeprom()
3240 return -EBUSY; in tg3_nvram_exec_cmd()
3251 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3253 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3255 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3266 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3269 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3270 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3279 * machine, the 32-bit value will be byteswapped.
3291 return -EINVAL; in tg3_nvram_read()
3364 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3377 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3378 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3384 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3406 len -= size; in tg3_nvram_write_block_unbuffered()
3410 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3452 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3484 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3492 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3495 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3505 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3532 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3569 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3581 /* tp->lock is held. */
3592 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3593 return -EBUSY; in tg3_pause_cpu()
3596 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3599 /* tp->lock is held. */
3611 /* tp->lock is held. */
3617 /* tp->lock is held. */
3624 /* tp->lock is held. */
3630 /* tp->lock is held. */
3657 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3659 return -ENODEV; in tg3_halt_cpu()
3677 * tp->fw->size minus headers. in tg3_fw_data_len()
3687 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3688 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3690 fw_len = tp->fw->size; in tg3_fw_data_len()
3692 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3695 /* tp->lock is held. */
3702 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3705 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3708 return -EINVAL; in tg3_load_firmware_cpu()
3736 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3744 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3748 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3752 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3761 /* tp->lock is held. */
3779 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3782 /* tp->lock is held. */
3788 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3792 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3810 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3812 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3815 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3816 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3841 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3842 return -EBUSY; in tg3_validate_rxcpu_state()
3847 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3849 return -EEXIST; in tg3_validate_rxcpu_state()
3855 /* tp->lock is held. */
3866 if (!tp->fw) in tg3_load_57766_firmware()
3871 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3883 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3884 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3896 /* tp->lock is held. */
3906 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3910 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3914 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3933 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3935 netdev_err(tp->dev, in tg3_load_tso_firmware()
3938 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3939 return -ENODEV; in tg3_load_tso_firmware()
3946 /* tp->lock is held. */
3960 index -= 4; in __tg3_set_one_mac_addr()
3966 /* tp->lock is held. */
3975 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3981 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3984 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3989 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
4000 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4001 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4010 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4015 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4032 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4039 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4044 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4045 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4050 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4052 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4054 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4055 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4056 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4058 &tp->link_config.advertising, in tg3_power_down_prepare()
4059 phydev->advertising); in tg3_power_down_prepare()
4083 linkmode_copy(phydev->advertising, advertising); in tg3_power_down_prepare()
4086 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4098 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4099 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4101 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4130 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4132 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4141 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4143 else if (tp->phy_flags & in tg3_power_down_prepare()
4145 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4152 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4166 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4190 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4217 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4220 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4236 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4272 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4273 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4310 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4336 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4348 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4358 if (!tp->eee.eee_enabled) in tg3_phy_autoneg_cfg()
4363 mii_eee_cap1_mod_linkmode_t(tp->eee.advertised, val); in tg3_phy_autoneg_cfg()
4398 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4399 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4402 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4403 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4409 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4410 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4418 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4419 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4423 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4428 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4429 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4443 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4444 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4455 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4469 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4503 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4504 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4507 err = -EIO; in tg3_phy_pull_config()
4511 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4514 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4517 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4520 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4523 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4524 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4533 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4535 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4537 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4543 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4544 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4547 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4555 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4557 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4559 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4562 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4565 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4577 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4583 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4613 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4618 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4619 if (!linkmode_equal(tp->eee.advertised, eee.advertised) || in tg3_phy_eee_config_ok()
4620 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4621 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4636 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4640 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4641 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4651 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4680 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4693 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4700 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4702 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4704 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4705 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4706 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4743 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4753 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4757 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4775 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4777 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4783 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4789 tp->link_up) { in tg3_setup_copper_phy()
4798 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4819 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4822 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4843 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4845 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4850 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4860 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4861 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4863 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4912 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4913 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4915 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4929 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4936 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4937 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4943 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4946 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4955 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4962 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4970 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4971 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4976 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4980 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4982 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4983 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4984 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4986 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4987 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4999 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5001 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5004 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5012 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5013 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5014 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5018 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5019 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5021 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5027 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5029 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5030 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5034 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5049 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5063 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5064 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5065 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5068 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5137 #define ANEG_FAILED -1
5149 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5150 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5151 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5152 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5153 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5154 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5155 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5156 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5157 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5159 ap->cur_time++; in tg3_fiber_aneg_smachine()
5164 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5165 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5166 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5167 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5169 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5170 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5171 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5175 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5177 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5179 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5181 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5182 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5183 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5184 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5185 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5190 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5193 switch (ap->state) { in tg3_fiber_aneg_smachine()
5195 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5196 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5200 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5201 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5202 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5203 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5204 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5205 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5206 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5207 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5208 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5210 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5212 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5217 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5218 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5219 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5221 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5222 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5226 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5230 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5232 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5242 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5243 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5244 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5246 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5248 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5249 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5250 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5251 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5254 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5258 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5259 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5263 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5264 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5265 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5266 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5269 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5273 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5274 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5275 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5276 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5278 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5280 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5281 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5282 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5287 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5291 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5300 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5301 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5302 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5303 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5304 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5305 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5306 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5307 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5308 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5309 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5310 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5311 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5312 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5313 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5315 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5317 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5318 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5319 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5320 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5321 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5322 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5324 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5329 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5330 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5331 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5334 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5336 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5337 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5339 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5340 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5350 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5351 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5352 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5355 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5360 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5361 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5362 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5365 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5368 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5373 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5403 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5407 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5423 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5424 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5462 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5507 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5508 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5514 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5535 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5538 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5545 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5546 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5550 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5561 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5562 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5582 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5587 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5588 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5590 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5591 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5607 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5615 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5617 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5624 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5625 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5639 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5656 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5686 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5689 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5706 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5707 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5708 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5711 tp->link_up && in tg3_setup_fiber_phy()
5728 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5729 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5730 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5733 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5740 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5748 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5750 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5765 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5766 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5767 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5770 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5775 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5776 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5777 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5781 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5782 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5789 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5791 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5792 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5816 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5819 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5824 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5827 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5839 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5847 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5848 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5856 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5869 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5870 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5872 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5881 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5882 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5890 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5891 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5901 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5911 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5935 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5960 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5974 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5975 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5976 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5978 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5983 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5984 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
5992 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
5994 tp->serdes_counter--; in tg3_serdes_parallel_detect()
5998 if (!tp->link_up && in tg3_serdes_parallel_detect()
5999 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6025 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6028 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6029 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6030 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6044 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6055 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6057 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6086 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6087 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6095 if (tp->link_up) { in tg3_setup_phy()
6097 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6105 if (!tp->link_up) in tg3_setup_phy()
6107 tp->pwrmgmt_thresh; in tg3_setup_phy()
6116 /* tp->lock must be held */
6129 /* tp->lock must be held */
6146 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; in tg3_get_ts_info()
6149 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6154 if (tp->ptp_clock) in tg3_get_ts_info()
6155 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6157 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6159 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6199 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6213 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6231 tp->ptp_adjust = 0; in tg3_ptp_settime()
6244 switch (rq->type) { in tg3_ptp_enable()
6247 if (rq->perout.flags) in tg3_ptp_enable()
6248 return -EOPNOTSUPP; in tg3_ptp_enable()
6250 if (rq->perout.index != 0) in tg3_ptp_enable()
6251 return -EINVAL; in tg3_ptp_enable()
6260 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6261 rq->perout.start.nsec; in tg3_ptp_enable()
6263 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6264 netdev_warn(tp->dev, in tg3_ptp_enable()
6265 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6266 rval = -EINVAL; in tg3_ptp_enable()
6271 netdev_warn(tp->dev, in tg3_ptp_enable()
6273 rval = -EINVAL; in tg3_ptp_enable()
6297 return -EOPNOTSUPP; in tg3_ptp_enable()
6304 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6305 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6320 if (tp->ptp_txts_retrycnt > 2) in tg3_ptp_ts_aux_work()
6325 if (hwclock != tp->pre_tx_ts) { in tg3_ptp_ts_aux_work()
6327 skb_tstamp_tx(tp->tx_tstamp_skb, ×tamp); in tg3_ptp_ts_aux_work()
6330 tp->ptp_txts_retrycnt++; in tg3_ptp_ts_aux_work()
6333 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_ts_aux_work()
6334 tp->tx_tstamp_skb = NULL; in tg3_ptp_ts_aux_work()
6335 tp->ptp_txts_retrycnt = 0; in tg3_ptp_ts_aux_work()
6336 tp->pre_tx_ts = 0; in tg3_ptp_ts_aux_work()
6337 return -1; in tg3_ptp_ts_aux_work()
6357 /* tp->lock must be held */
6365 tp->ptp_adjust = 0; in tg3_ptp_init()
6366 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6369 /* tp->lock must be held */
6375 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6376 tp->ptp_adjust = 0; in tg3_ptp_resume()
6381 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6384 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6385 tp->ptp_clock = NULL; in tg3_ptp_fini()
6386 tp->ptp_adjust = 0; in tg3_ptp_fini()
6387 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_fini()
6388 tp->tx_tstamp_skb = NULL; in tg3_ptp_fini()
6393 return tp->irq_sync; in tg3_irq_sync()
6463 if (tp->pdev->error_state != pci_channel_io_normal) { in tg3_dump_state()
6464 netdev_err(tp->dev, "PCI channel ERROR!\n"); in tg3_dump_state()
6484 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6491 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6492 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6495 netdev_err(tp->dev, in tg3_dump_state()
6498 tnapi->hw_status->status, in tg3_dump_state()
6499 tnapi->hw_status->status_tag, in tg3_dump_state()
6500 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6501 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6502 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6503 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6504 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6506 netdev_err(tp->dev, in tg3_dump_state()
6509 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6510 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6511 tnapi->rx_rcb_ptr, in tg3_dump_state()
6512 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6513 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6514 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6515 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6519 /* This is called whenever we suspect that the system chipset is re-
6520 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6528 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6530 netdev_warn(tp->dev, in tg3_tx_recover()
6531 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6543 return tnapi->tx_pending - in tg3_tx_avail()
6544 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6553 struct tg3 *tp = tnapi->tp; in tg3_tx()
6554 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6555 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6557 int index = tnapi - tp->napi; in tg3_tx()
6561 index--; in tg3_tx()
6563 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6566 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6568 struct sk_buff *skb = ri->skb; in tg3_tx()
6576 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6581 if (hwclock != tp->pre_tx_ts) { in tg3_tx()
6584 tp->pre_tx_ts = 0; in tg3_tx()
6586 tp->tx_tstamp_skb = skb; in tg3_tx()
6591 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6594 ri->skb = NULL; in tg3_tx()
6596 while (ri->fragmented) { in tg3_tx()
6597 ri->fragmented = false; in tg3_tx()
6599 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6604 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6605 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6606 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6609 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6611 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6614 while (ri->fragmented) { in tg3_tx()
6615 ri->fragmented = false; in tg3_tx()
6617 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6624 bytes_compl += skb->len; in tg3_tx()
6629 ptp_schedule_worker(tp->ptp_clock, 0); in tg3_tx()
6639 tnapi->tx_cons = sw_idx; in tg3_tx()
6671 if (!ri->data) in tg3_rx_data_free()
6674 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6676 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6677 ri->data = NULL; in tg3_rx_data_free()
6704 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6705 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6706 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6707 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6711 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6712 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6713 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6718 return -EINVAL; in tg3_alloc_rx_data()
6737 return -ENOMEM; in tg3_alloc_rx_data()
6739 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6741 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6743 return -EIO; in tg3_alloc_rx_data()
6746 map->data = data; in tg3_alloc_rx_data()
6749 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6750 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6764 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx()
6767 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6772 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6773 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6774 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6775 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6776 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6780 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6781 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6782 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6783 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6784 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6791 dest_map->data = src_map->data; in tg3_recycle_rx()
6794 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6795 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6802 src_map->data = NULL; in tg3_recycle_rx()
6817 * it is first placed into the on-chip ram. When the packet's length
6825 * rings, then cache lines never move beyond shared-modified state.
6831 struct tg3 *tp = tnapi->tp; in tg3_rx()
6834 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6837 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6839 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6847 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6848 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6851 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6859 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6860 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6862 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6864 data = ri->data; in tg3_rx()
6868 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6870 data = ri->data; in tg3_rx()
6877 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6883 tnapi->rx_dropped++; in tg3_rx()
6888 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6891 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6893 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6908 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6916 ri->data = NULL; in tg3_rx()
6931 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6937 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6939 memcpy(skb->data, in tg3_rx()
6942 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6951 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6952 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6953 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6955 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6959 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6961 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6962 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6963 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6968 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6969 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6971 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6973 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6976 budget--; in tg3_rx()
6981 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6982 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6983 tp->rx_std_ring_mask; in tg3_rx()
6985 tpr->rx_std_prod_idx); in tg3_rx()
6991 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6995 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
7001 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
7002 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
7010 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
7011 tp->rx_std_ring_mask; in tg3_rx()
7013 tpr->rx_std_prod_idx); in tg3_rx()
7016 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
7017 tp->rx_jmb_ring_mask; in tg3_rx()
7019 tpr->rx_jmb_prod_idx); in tg3_rx()
7027 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7028 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7030 if (tnapi != &tp->napi[1]) { in tg3_rx()
7031 tp->rx_refill = true; in tg3_rx()
7032 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7043 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7045 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7046 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7047 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7048 spin_lock(&tp->lock); in tg3_poll_link()
7058 spin_unlock(&tp->lock); in tg3_poll_link()
7071 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7078 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7081 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7082 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7084 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7085 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7088 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7090 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7091 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7094 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7095 cpycnt = i - di; in tg3_rx_prodring_xfer()
7096 err = -ENOSPC; in tg3_rx_prodring_xfer()
7110 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7111 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7116 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7117 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7118 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7119 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7122 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7123 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7124 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7125 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7129 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7136 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7139 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7140 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7142 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7143 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7146 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7148 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7149 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7152 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7153 cpycnt = i - di; in tg3_rx_prodring_xfer()
7154 err = -ENOSPC; in tg3_rx_prodring_xfer()
7168 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7169 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7174 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7175 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7176 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7177 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7180 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7181 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7182 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7183 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7191 struct tg3 *tp = tnapi->tp; in tg3_poll_work()
7194 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7200 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7205 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7207 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7208 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7210 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7211 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7213 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7214 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7216 tp->rx_refill = false; in tg3_poll_work()
7217 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7219 &tp->napi[i].prodring); in tg3_poll_work()
7223 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7225 dpr->rx_std_prod_idx); in tg3_poll_work()
7227 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7229 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7232 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7240 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7241 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7246 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7247 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7254 struct tg3 *tp = tnapi->tp; in tg3_poll_msix()
7256 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7267 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7271 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7272 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7276 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7277 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7282 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7287 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7292 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7293 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7295 tnapi->coal_now); in tg3_poll_msix()
7322 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7327 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7332 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7348 struct tg3 *tp = tnapi->tp; in tg3_poll()
7350 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7353 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7367 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7371 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7372 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7375 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7396 int txq_idx = tp->txq_cnt - 1; in tg3_napi_disable()
7397 int rxq_idx = tp->rxq_cnt - 1; in tg3_napi_disable()
7401 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_napi_disable()
7402 tnapi = &tp->napi[i]; in tg3_napi_disable()
7403 if (tnapi->tx_buffers) { in tg3_napi_disable()
7404 netif_queue_set_napi(tp->dev, txq_idx, in tg3_napi_disable()
7406 txq_idx--; in tg3_napi_disable()
7408 if (tnapi->rx_rcb) { in tg3_napi_disable()
7409 netif_queue_set_napi(tp->dev, rxq_idx, in tg3_napi_disable()
7411 rxq_idx--; in tg3_napi_disable()
7413 napi_disable(&tnapi->napi); in tg3_napi_disable()
7423 for (i = 0; i < tp->irq_cnt; i++) { in tg3_napi_enable()
7424 tnapi = &tp->napi[i]; in tg3_napi_enable()
7425 napi_enable_locked(&tnapi->napi); in tg3_napi_enable()
7426 if (tnapi->tx_buffers) { in tg3_napi_enable()
7427 netif_queue_set_napi(tp->dev, txq_idx, in tg3_napi_enable()
7429 &tnapi->napi); in tg3_napi_enable()
7432 if (tnapi->rx_rcb) { in tg3_napi_enable()
7433 netif_queue_set_napi(tp->dev, rxq_idx, in tg3_napi_enable()
7435 &tnapi->napi); in tg3_napi_enable()
7445 for (i = 0; i < tp->irq_cnt; i++) { in tg3_napi_init()
7446 netif_napi_add_locked(tp->dev, &tp->napi[i].napi, in tg3_napi_init()
7448 netif_napi_set_irq_locked(&tp->napi[i].napi, in tg3_napi_init()
7449 tp->napi[i].irq_vec); in tg3_napi_init()
7457 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7458 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7463 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7465 netif_carrier_off(tp->dev); in tg3_netif_stop()
7466 netif_tx_disable(tp->dev); in tg3_netif_stop()
7469 /* tp->lock must be held */
7478 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7480 if (tp->link_up) in tg3_netif_start()
7481 netif_carrier_on(tp->dev); in tg3_netif_start()
7484 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7489 __releases(tp->lock) in tg3_irq_quiesce()
7490 __acquires(tp->lock) in tg3_irq_quiesce()
7494 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7496 tp->irq_sync = 1; in tg3_irq_quiesce()
7499 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7501 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7502 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7504 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7508 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7514 spin_lock_bh(&tp->lock); in tg3_full_lock()
7521 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7524 /* One-shot MSI handler - Chip automatically disables interrupt
7530 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot()
7532 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7533 if (tnapi->rx_rcb) in tg3_msi_1shot()
7534 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7537 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7542 /* MSI ISR - No need to check for interrupt sharing and no need to
7549 struct tg3 *tp = tnapi->tp; in tg3_msi()
7551 prefetch(tnapi->hw_status); in tg3_msi()
7552 if (tnapi->rx_rcb) in tg3_msi()
7553 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7555 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7556 * chip-internal interrupt pending events. in tg3_msi()
7557 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7558 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7561 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7563 napi_schedule(&tnapi->napi); in tg3_msi()
7571 struct tg3 *tp = tnapi->tp; in tg3_interrupt()
7572 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7580 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7589 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7590 * chip-internal interrupt pending events. in tg3_interrupt()
7591 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7592 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7595 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7602 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7604 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7605 napi_schedule(&tnapi->napi); in tg3_interrupt()
7607 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7620 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged()
7621 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7629 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7638 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7639 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7640 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7641 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7644 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7656 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7661 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7663 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7673 struct tg3 *tp = tnapi->tp; in tg3_test_isr()
7674 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7676 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7693 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7694 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7732 /* Test for DMA addresses > 40-bit */
7749 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7750 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7751 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7752 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7759 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set()
7774 if (tp->dma_limit) { in tg3_tx_frag_set()
7777 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7778 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7779 len -= tp->dma_limit; in tg3_tx_frag_set()
7783 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7784 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7787 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7789 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7791 *budget -= 1; in tg3_tx_frag_set()
7800 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7802 *budget -= 1; in tg3_tx_frag_set()
7806 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7810 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7822 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7824 skb = txb->skb; in tg3_tx_skb_unmap()
7825 txb->skb = NULL; in tg3_tx_skb_unmap()
7827 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7830 while (txb->fragmented) { in tg3_tx_skb_unmap()
7831 txb->fragmented = false; in tg3_tx_skb_unmap()
7833 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7837 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7840 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7842 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7846 while (txb->fragmented) { in tg3_tx_skb_unmap()
7847 txb->fragmented = false; in tg3_tx_skb_unmap()
7849 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7854 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7860 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround()
7868 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7876 ret = -1; in tigon3_dma_hwbug_workaround()
7879 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7880 new_skb->len, DMA_TO_DEVICE); in tigon3_dma_hwbug_workaround()
7882 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7884 ret = -1; in tigon3_dma_hwbug_workaround()
7890 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7891 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7895 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7897 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7899 ret = -1; in tigon3_dma_hwbug_workaround()
7914 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7925 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7944 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7947 tnapi->tx_dropped++; in tg3_tso_bug()
7953 __tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7968 int i = -1, would_hit_hwbug; in __tg3_start_xmit()
7979 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in __tg3_start_xmit()
7986 * and TX reclaim runs via tp->napi.poll inside of a software in __tg3_start_xmit()
7990 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in __tg3_start_xmit()
8001 entry = tnapi->tx_prod; in __tg3_start_xmit()
8004 mss = skb_shinfo(skb)->gso_size; in __tg3_start_xmit()
8014 hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN; in __tg3_start_xmit()
8016 /* HW/FW can not correctly segment packets that have been in __tg3_start_xmit()
8019 if (skb->protocol == htons(ETH_P_8021Q) || in __tg3_start_xmit()
8020 skb->protocol == htons(ETH_P_8021AD)) { in __tg3_start_xmit()
8033 ip_csum = iph->check; in __tg3_start_xmit()
8034 ip_tot_len = iph->tot_len; in __tg3_start_xmit()
8035 iph->check = 0; in __tg3_start_xmit()
8036 iph->tot_len = htons(mss + hdr_len); in __tg3_start_xmit()
8043 tcp_csum = tcph->check; in __tg3_start_xmit()
8048 tcph->check = 0; in __tg3_start_xmit()
8051 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in __tg3_start_xmit()
8064 if (tcp_opt_len || iph->ihl > 5) { in __tg3_start_xmit()
8067 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in __tg3_start_xmit()
8071 if (tcp_opt_len || iph->ihl > 5) { in __tg3_start_xmit()
8074 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in __tg3_start_xmit()
8078 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in __tg3_start_xmit()
8079 /* HW/FW can not correctly checksum packets that have been in __tg3_start_xmit()
8082 if (skb->protocol == htons(ETH_P_8021Q) || in __tg3_start_xmit()
8083 skb->protocol == htons(ETH_P_8021AD)) { in __tg3_start_xmit()
8092 !mss && skb->len > VLAN_ETH_FRAME_LEN) in __tg3_start_xmit()
8100 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in __tg3_start_xmit()
8103 if (!tp->pre_tx_ts) { in __tg3_start_xmit()
8104 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in __tg3_start_xmit()
8106 tg3_read_tx_tstamp(tp, &tp->pre_tx_ts); in __tg3_start_xmit()
8113 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in __tg3_start_xmit()
8115 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8119 tnapi->tx_buffers[entry].skb = skb; in __tg3_start_xmit()
8120 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in __tg3_start_xmit()
8128 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in __tg3_start_xmit()
8131 } else if (skb_shinfo(skb)->nr_frags > 0) { in __tg3_start_xmit()
8142 last = skb_shinfo(skb)->nr_frags - 1; in __tg3_start_xmit()
8144 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in __tg3_start_xmit()
8147 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in __tg3_start_xmit()
8150 tnapi->tx_buffers[entry].skb = NULL; in __tg3_start_xmit()
8151 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in __tg3_start_xmit()
8153 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8168 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in __tg3_start_xmit()
8175 iph->check = ip_csum; in __tg3_start_xmit()
8176 iph->tot_len = ip_tot_len; in __tg3_start_xmit()
8178 tcph->check = tcp_csum; in __tg3_start_xmit()
8185 entry = tnapi->tx_prod; in __tg3_start_xmit()
8193 netdev_tx_sent_queue(txq, skb->len); in __tg3_start_xmit()
8198 tnapi->tx_prod = entry; in __tg3_start_xmit()
8215 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in __tg3_start_xmit()
8216 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in __tg3_start_xmit()
8220 tnapi->tx_dropped++; in __tg3_start_xmit()
8249 tnapi = &tp->napi[skb_queue_mapping]; in tg3_start_xmit()
8254 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_start_xmit()
8263 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8266 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8269 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8271 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8272 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8274 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8276 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8279 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8281 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8284 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8296 return -EIO; in tg3_phy_lpbk_set()
8307 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8317 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8333 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8338 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8349 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8353 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8356 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8364 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8386 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8389 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8391 netif_carrier_on(tp->dev); in tg3_set_loopback()
8392 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8395 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8398 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8402 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8412 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8420 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8433 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8434 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8435 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8436 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8437 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8440 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8441 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8442 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8443 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8451 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8452 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8453 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8456 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8457 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8466 * end up in the driver. tp->{tx,}lock are held and thus
8474 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8475 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8476 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8477 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8479 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8480 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8482 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8483 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8489 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8493 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8495 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8501 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8504 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8505 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8506 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8507 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8512 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8517 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8520 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8523 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8531 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8536 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8539 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8540 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8541 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8543 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8547 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8552 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8555 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8558 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8568 return -ENOMEM; in tg3_rx_prodring_alloc()
8574 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8575 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8576 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8577 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8578 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8579 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8580 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8581 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8583 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8584 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8585 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8586 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8593 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8595 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8596 return -ENOMEM; in tg3_rx_prodring_init()
8598 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8600 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8602 if (!tpr->rx_std) in tg3_rx_prodring_init()
8606 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8608 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8611 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8613 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8615 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8623 return -ENOMEM; in tg3_rx_prodring_init()
8630 * end up in the driver. tp->{tx,}lock is not held and we are not
8637 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8638 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8640 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8642 if (!tnapi->tx_buffers) in tg3_free_rings()
8646 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8652 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8656 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8664 * end up in the driver. tp->{tx,}lock are held and thus
8674 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8675 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8677 tnapi->last_tag = 0; in tg3_init_rings()
8678 tnapi->last_irq_tag = 0; in tg3_init_rings()
8679 tnapi->hw_status->status = 0; in tg3_init_rings()
8680 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8681 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8683 tnapi->tx_prod = 0; in tg3_init_rings()
8684 tnapi->tx_cons = 0; in tg3_init_rings()
8685 if (tnapi->tx_ring) in tg3_init_rings()
8686 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8688 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8689 if (tnapi->rx_rcb) in tg3_init_rings()
8690 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8692 if (tnapi->prodring.rx_std && in tg3_init_rings()
8693 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8695 return -ENOMEM; in tg3_init_rings()
8706 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8707 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8709 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8710 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8711 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8712 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8715 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8716 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8723 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8731 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8732 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8735 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8738 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8740 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8742 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8750 return -ENOMEM; in tg3_mem_tx_acquire()
8757 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8758 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8760 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8762 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8765 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8767 tnapi->rx_rcb, in tg3_mem_rx_release()
8768 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8769 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8777 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8786 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8788 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8798 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8800 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8802 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8810 return -ENOMEM; in tg3_mem_rx_acquire()
8821 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8822 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8824 if (tnapi->hw_status) { in tg3_free_consistent()
8825 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8826 tnapi->hw_status, in tg3_free_consistent()
8827 tnapi->status_mapping); in tg3_free_consistent()
8828 tnapi->hw_status = NULL; in tg3_free_consistent()
8835 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8837 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8839 if (tp->hw_stats) { in tg3_free_consistent()
8840 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8841 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8842 tp->hw_stats = NULL; in tg3_free_consistent()
8854 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8856 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8857 if (!tp->hw_stats) in tg3_alloc_consistent()
8860 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8861 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8864 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8866 &tnapi->status_mapping, in tg3_alloc_consistent()
8868 if (!tnapi->hw_status) in tg3_alloc_consistent()
8871 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8884 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8887 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8890 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8893 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8896 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8898 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8909 return -ENOMEM; in tg3_alloc_consistent()
8915 * clears. tp->lock is held.
8944 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8945 dev_err(&tp->pdev->dev, in tg3_stop_block()
8949 return -ENODEV; in tg3_stop_block()
8959 dev_err(&tp->pdev->dev, in tg3_stop_block()
8962 return -ENODEV; in tg3_stop_block()
8968 /* tp->lock is held. */
8975 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8976 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8977 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8978 err = -ENODEV; in tg3_abort_hw()
8982 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8983 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
9001 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
9002 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
9005 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
9006 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
9014 dev_err(&tp->pdev->dev, in tg3_abort_hw()
9017 err |= -ENODEV; in tg3_abort_hw()
9031 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
9032 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
9033 if (tnapi->hw_status) in tg3_abort_hw()
9034 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
9043 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
9051 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
9052 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
9053 tp->misc_host_ctrl); in tg3_restore_pci_state()
9065 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
9067 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
9070 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
9071 tp->pci_cacheline_sz); in tg3_restore_pci_state()
9072 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
9073 tp->pci_lat_timer); in tg3_restore_pci_state()
9076 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
9080 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9083 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9095 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9096 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9098 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9099 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9150 /* tp->lock is held. */
9152 __releases(tp->lock) in tg3_chip_reset()
9153 __acquires(tp->lock) in tg3_chip_reset()
9159 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9160 return -ENODEV; in tg3_chip_reset()
9169 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9187 write_op = tp->write32; in tg3_chip_reset()
9189 tp->write32 = tg3_write32; in tg3_chip_reset()
9198 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9199 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9200 if (tnapi->hw_status) { in tg3_chip_reset()
9201 tnapi->hw_status->status = 0; in tg3_chip_reset()
9202 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9204 tnapi->last_tag = 0; in tg3_chip_reset()
9205 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9211 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9212 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9258 tp->write32 = write_op; in tg3_chip_reset()
9261 * Some 575X chips even will not respond to a PCI cfg access in tg3_chip_reset()
9275 /* Flush PCI posted writes. The normal MMIO registers in tg3_chip_reset()
9281 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9285 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9296 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9297 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9309 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9312 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9348 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9356 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9358 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9360 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9361 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9364 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9365 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9366 val = tp->mac_mode; in tg3_chip_reset()
9367 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9368 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9369 val = tp->mac_mode; in tg3_chip_reset()
9402 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9413 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9419 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9421 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9432 /* tp->lock is held. */
9449 if (tp->hw_stats) { in tg3_halt()
9451 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9452 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9455 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9458 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_halt()
9460 tnapi->rx_dropped = 0; in tg3_halt()
9461 tnapi->tx_dropped = 0; in tg3_halt()
9475 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9476 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9478 eth_hw_addr_set(dev, addr->sa_data); in tg3_set_mac_addr()
9496 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9499 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9504 /* tp->lock is held. */
9531 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9532 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9533 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9539 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9543 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9545 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9547 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9551 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9561 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9564 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9565 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9566 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9567 limit--; in tg3_coal_rx_init()
9578 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9580 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9582 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9585 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9598 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9600 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9601 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9603 if (!tp->link_up) in __tg3_set_coalesce()
9610 /* tp->lock is held. */
9632 /* tp->lock is held. */
9641 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9642 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9644 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9647 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9653 /* tp->lock is held. */
9676 /* tp->lock is held. */
9685 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9686 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9688 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9691 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9692 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9697 /* tp->lock is held. */
9702 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9709 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9710 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9711 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9712 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9716 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9717 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9718 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9720 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9721 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9722 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9723 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9724 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9725 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9728 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9730 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9731 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9732 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9733 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9736 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9744 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9748 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9750 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9754 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9755 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9761 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9784 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9785 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9798 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9826 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9837 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9840 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9855 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9870 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9876 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9882 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9883 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9894 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9904 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9905 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9911 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9916 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9925 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9929 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9944 /* tp->lock is held. */
9949 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9960 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9961 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9964 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9968 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
10082 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10083 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10129 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10135 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10138 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10142 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10144 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10145 * the offload processors, so make the chip do the pseudo- in tg3_reset_hw()
10147 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10150 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10153 if (tp->rxptpctl) in tg3_reset_hw()
10155 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10160 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10166 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10167 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10192 fw_len = tp->fw_len; in tg3_reset_hw()
10193 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10197 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10200 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10202 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10204 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10206 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10209 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10211 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10213 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10216 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10218 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10235 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10236 return -ENODEV; in tg3_reset_hw()
10262 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10264 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10282 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10284 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10310 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10311 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10313 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10314 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10315 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10324 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10378 tp->dma_limit = 0; in tg3_reset_hw()
10379 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10381 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10467 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10475 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10477 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10491 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10498 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10499 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10505 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10509 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10511 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10513 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10514 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10517 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10537 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10538 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10542 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10545 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10551 if (tp->irq_cnt > 1) in tg3_reset_hw()
10594 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10603 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10670 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10674 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10679 tp->tx_mode &= ~val; in tg3_reset_hw()
10680 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10683 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10697 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10699 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10702 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10705 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10712 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10715 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10718 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10722 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10725 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10727 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10729 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10749 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10750 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10754 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10760 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10761 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10762 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10766 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10767 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10773 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10774 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10786 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10799 limit -= 4; in tg3_reset_hw()
10859 * packet processing. Invoked with tp->lock held.
10886 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10887 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10900 spin_lock_bh(&tp->lock); in tg3_show_temp()
10901 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10903 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10925 if (tp->hwmon_dev) { in tg3_hwmon_close()
10926 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10927 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10935 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10951 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10953 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10954 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10955 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10966 (PSTAT)->low += __val; \
10967 if ((PSTAT)->low < __val) \
10968 (PSTAT)->high += 1; \
10973 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10975 if (!tp->link_up) in tg3_periodic_fetch_stats()
10978 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10979 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10980 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10981 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10982 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10983 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10984 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10985 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10986 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10987 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10988 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10989 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10990 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10992 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10993 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
11002 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
11003 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
11004 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
11005 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
11006 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
11007 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
11008 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
11009 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
11010 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
11011 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
11012 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
11013 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
11014 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
11015 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
11017 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
11022 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
11028 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
11029 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
11030 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
11032 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
11034 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
11041 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
11042 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
11045 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
11046 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
11047 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
11048 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
11054 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
11055 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
11056 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
11064 spin_lock(&tp->lock); in tg3_timer()
11066 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
11067 spin_unlock(&tp->lock); in tg3_timer()
11081 /* All of this garbage is because when using non-tagged in tg3_timer()
11085 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11087 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11089 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11094 spin_unlock(&tp->lock); in tg3_timer()
11101 if (!--tp->timer_counter) { in tg3_timer()
11105 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11115 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11127 if (tp->link_up && in tg3_timer()
11131 if (!tp->link_up && in tg3_timer()
11137 if (!tp->serdes_counter) { in tg3_timer()
11139 (tp->mac_mode & in tg3_timer()
11142 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11147 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11155 if (link_up != tp->link_up) in tg3_timer()
11159 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11179 if (!--tp->asf_counter) { in tg3_timer()
11191 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11197 spin_unlock(&tp->lock); in tg3_timer()
11200 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11201 add_timer(&tp->timer); in tg3_timer()
11209 tp->timer_offset = HZ; in tg3_timer_init()
11211 tp->timer_offset = HZ / 10; in tg3_timer_init()
11213 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11215 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11216 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11219 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11224 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11225 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11227 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11228 add_timer(&tp->timer); in tg3_timer_start()
11233 timer_delete_sync(&tp->timer); in tg3_timer_stop()
11236 /* Restart hardware after configuration changes, self-test, etc.
11237 * Invoked with tp->lock held.
11240 __releases(tp->lock) in tg3_restart_hw()
11241 __acquires(tp->lock) in tg3_restart_hw()
11242 __releases(tp->dev->lock) in tg3_restart_hw()
11243 __acquires(tp->dev->lock) in tg3_restart_hw()
11249 netdev_err(tp->dev, in tg3_restart_hw()
11250 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11254 tp->irq_sync = 0; in tg3_restart_hw()
11256 netdev_unlock(tp->dev); in tg3_restart_hw()
11257 dev_close(tp->dev); in tg3_restart_hw()
11258 netdev_lock(tp->dev); in tg3_restart_hw()
11272 if (tp->pcierr_recovery || !netif_running(tp->dev) || in tg3_reset_task()
11273 tp->pdev->error_state != pci_channel_io_normal) { in tg3_reset_task()
11286 netdev_lock(tp->dev); in tg3_reset_task()
11290 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11291 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11300 tp->irq_sync = 0; in tg3_reset_task()
11306 netdev_unlock(tp->dev); in tg3_reset_task()
11307 dev_close(tp->dev); in tg3_reset_task()
11313 netdev_unlock(tp->dev); in tg3_reset_task()
11325 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11327 if (tp->irq_cnt == 1) in tg3_request_irq()
11328 name = tp->dev->name; in tg3_request_irq()
11330 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11331 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11332 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11333 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11334 else if (tnapi->tx_buffers) in tg3_request_irq()
11335 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11336 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11337 else if (tnapi->rx_rcb) in tg3_request_irq()
11338 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11339 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11341 snprintf(name, sizeof(tnapi->irq_lbl), in tg3_request_irq()
11342 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11357 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11362 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11363 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11368 return -ENODEV; in tg3_test_interrupt()
11372 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11383 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11384 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11388 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11391 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11392 tnapi->coal_now); in tg3_test_interrupt()
11397 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11407 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11408 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11415 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11431 return -EIO; in tg3_test_interrupt()
11448 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11449 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11454 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11460 if (err != -EIO) in tg3_test_msi()
11464 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11468 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11470 pci_disable_msi(tp->pdev); in tg3_test_msi()
11473 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11490 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11499 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11500 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11501 tp->fw_needed); in tg3_request_firmware()
11502 return -ENOENT; in tg3_request_firmware()
11505 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11512 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11513 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11514 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11515 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11516 release_firmware(tp->fw); in tg3_request_firmware()
11517 tp->fw = NULL; in tg3_request_firmware()
11518 return -EINVAL; in tg3_request_firmware()
11522 tp->fw_needed = NULL; in tg3_request_firmware()
11528 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11532 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11536 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11547 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11548 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11549 if (!tp->rxq_cnt) in tg3_enable_msix()
11550 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11551 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11552 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11554 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11558 if (!tp->txq_req) in tg3_enable_msix()
11559 tp->txq_cnt = 1; in tg3_enable_msix()
11561 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11563 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11568 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11571 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11572 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11573 tp->irq_cnt, rc); in tg3_enable_msix()
11574 tp->irq_cnt = rc; in tg3_enable_msix()
11575 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11576 if (tp->txq_cnt) in tg3_enable_msix()
11577 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11580 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11581 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11583 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11584 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11588 if (tp->irq_cnt == 1) in tg3_enable_msix()
11593 if (tp->txq_cnt > 1) in tg3_enable_msix()
11596 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11608 netdev_warn(tp->dev, in tg3_ints_init()
11615 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11620 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11628 tp->irq_cnt = 1; in tg3_ints_init()
11629 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11632 if (tp->irq_cnt == 1) { in tg3_ints_init()
11633 tp->txq_cnt = 1; in tg3_ints_init()
11634 tp->rxq_cnt = 1; in tg3_ints_init()
11635 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11636 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11643 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11645 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11655 struct net_device *dev = tp->dev; in tg3_start()
11679 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11682 for (i--; i >= 0; i--) { in tg3_start()
11683 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11685 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11747 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11748 tg3_set_loopback(dev, dev->features); in tg3_start()
11753 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11754 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11755 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11792 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11793 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11794 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11809 if (tp->pcierr_recovery) { in tg3_open()
11812 return -EAGAIN; in tg3_open()
11815 if (tp->fw_needed) { in tg3_open()
11819 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11820 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11821 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11822 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11823 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11829 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11832 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11851 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11855 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11865 if (tp->pcierr_recovery) { in tg3_close()
11868 return -EAGAIN; in tg3_close()
11873 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11883 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11888 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11890 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11902 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11904 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11907 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11911 estats->member = old_estats->member + \
11912 get_stat64(&hw_stats->member)
11916 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11917 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
12000 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
12001 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
12006 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
12007 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
12008 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
12009 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
12011 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
12012 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
12013 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
12014 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
12016 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
12017 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
12018 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
12019 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
12021 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
12022 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
12023 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
12024 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
12025 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
12026 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
12027 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
12029 stats->multicast = old_stats->multicast + in tg3_get_nstats()
12030 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
12031 stats->collisions = old_stats->collisions + in tg3_get_nstats()
12032 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
12034 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
12035 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
12036 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
12038 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
12039 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
12040 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
12041 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
12042 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
12043 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
12045 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
12048 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
12049 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
12051 /* Aggregate per-queue counters. The per-queue counters are updated in tg3_get_nstats()
12052 * by a single writer, race-free. The result computed by this loop in tg3_get_nstats()
12059 rx_dropped = (unsigned long)(old_stats->rx_dropped); in tg3_get_nstats()
12060 tx_dropped = (unsigned long)(old_stats->tx_dropped); in tg3_get_nstats()
12062 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
12063 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_get_nstats()
12065 rx_dropped += tnapi->rx_dropped; in tg3_get_nstats()
12066 tx_dropped += tnapi->tx_dropped; in tg3_get_nstats()
12069 stats->rx_dropped = rx_dropped; in tg3_get_nstats()
12070 stats->tx_dropped = tx_dropped; in tg3_get_nstats()
12083 regs->version = 0; in tg3_get_regs()
12087 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
12101 return tp->nvram_size; in tg3_get_eeprom_len()
12113 return -EINVAL; in tg3_get_eeprom()
12115 offset = eeprom->offset; in tg3_get_eeprom()
12116 len = eeprom->len; in tg3_get_eeprom()
12117 eeprom->len = 0; in tg3_get_eeprom()
12119 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12137 b_count = 4 - b_offset; in tg3_get_eeprom()
12142 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12146 len -= b_count; in tg3_get_eeprom()
12148 eeprom->len += b_count; in tg3_get_eeprom()
12152 pd = &data[eeprom->len]; in tg3_get_eeprom()
12153 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12157 i -= 4; in tg3_get_eeprom()
12158 eeprom->len += i; in tg3_get_eeprom()
12164 eeprom->len += i; in tg3_get_eeprom()
12165 ret = -EINTR; in tg3_get_eeprom()
12171 eeprom->len += i; in tg3_get_eeprom()
12175 pd = &data[eeprom->len]; in tg3_get_eeprom()
12177 b_offset = offset + len - b_count; in tg3_get_eeprom()
12182 eeprom->len += b_count; in tg3_get_eeprom()
12204 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12205 return -EINVAL; in tg3_set_eeprom()
12207 offset = eeprom->offset; in tg3_set_eeprom()
12208 len = eeprom->len; in tg3_set_eeprom()
12212 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12226 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12235 return -ENOMEM; in tg3_set_eeprom()
12239 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12240 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12259 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12260 return -EAGAIN; in tg3_get_link_ksettings()
12261 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12269 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12273 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12279 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12282 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12284 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12287 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12289 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12290 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12296 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12300 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12303 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12304 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12305 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12307 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12308 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12310 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12311 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12312 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12314 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12317 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12318 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12319 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12321 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12322 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12330 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12335 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12336 return -EAGAIN; in tg3_set_link_ksettings()
12337 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12341 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12342 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12343 return -EINVAL; in tg3_set_link_ksettings()
12345 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12346 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12347 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12348 return -EINVAL; in tg3_set_link_ksettings()
12351 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12353 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12358 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12362 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12372 return -EINVAL; in tg3_set_link_ksettings()
12383 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12385 return -EINVAL; in tg3_set_link_ksettings()
12387 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12388 return -EINVAL; in tg3_set_link_ksettings()
12392 return -EINVAL; in tg3_set_link_ksettings()
12398 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12399 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12400 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12402 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12403 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12405 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12406 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12407 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12410 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12426 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12427 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12428 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12435 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12436 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12438 wol->supported = 0; in tg3_get_wol()
12439 wol->wolopts = 0; in tg3_get_wol()
12440 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12441 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12442 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12448 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12450 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12451 return -EINVAL; in tg3_set_wol()
12452 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12454 return -EINVAL; in tg3_set_wol()
12456 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12469 return tp->msg_enable; in tg3_get_msglevel()
12475 tp->msg_enable = value; in tg3_set_msglevel()
12484 return -EAGAIN; in tg3_nway_reset()
12486 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12487 return -EINVAL; in tg3_nway_reset()
12492 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12493 return -EAGAIN; in tg3_nway_reset()
12494 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12498 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12499 r = -EINVAL; in tg3_nway_reset()
12503 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12508 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12521 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12523 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12525 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12527 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12529 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12531 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12533 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12535 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12547 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12548 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12549 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12550 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12552 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12553 return -EINVAL; in tg3_set_ringparam()
12564 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12567 tp->rx_pending > 63) in tg3_set_ringparam()
12568 tp->rx_pending = 63; in tg3_set_ringparam()
12571 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12573 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12574 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12602 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12604 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12605 epause->rx_pause = 1; in tg3_get_pauseparam()
12607 epause->rx_pause = 0; in tg3_get_pauseparam()
12609 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12610 epause->tx_pause = 1; in tg3_get_pauseparam()
12612 epause->tx_pause = 0; in tg3_get_pauseparam()
12621 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12627 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12630 return -EINVAL; in tg3_set_pauseparam()
12632 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12633 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause); in tg3_set_pauseparam()
12634 if (epause->rx_pause) { in tg3_set_pauseparam()
12635 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12637 if (epause->tx_pause) { in tg3_set_pauseparam()
12638 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12640 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12641 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12644 if (epause->autoneg) in tg3_set_pauseparam()
12649 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12650 if (phydev->autoneg) { in tg3_set_pauseparam()
12661 if (!epause->autoneg) in tg3_set_pauseparam()
12675 if (epause->autoneg) in tg3_set_pauseparam()
12679 if (epause->rx_pause) in tg3_set_pauseparam()
12680 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12682 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12683 if (epause->tx_pause) in tg3_set_pauseparam()
12684 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12686 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12705 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12718 return -EOPNOTSUPP; in tg3_get_sset_count()
12728 return -EOPNOTSUPP; in tg3_get_rxnfc()
12730 switch (info->cmd) { in tg3_get_rxnfc()
12732 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12733 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12735 info->data = num_online_cpus(); in tg3_get_rxnfc()
12736 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12737 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12743 return -EOPNOTSUPP; in tg3_get_rxnfc()
12763 rxfh->hfunc = ETH_RSS_HASH_TOP; in tg3_get_rxfh()
12764 if (!rxfh->indir) in tg3_get_rxfh()
12768 rxfh->indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12782 if (rxfh->key || in tg3_set_rxfh()
12783 (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && in tg3_set_rxfh()
12784 rxfh->hfunc != ETH_RSS_HASH_TOP)) in tg3_set_rxfh()
12785 return -EOPNOTSUPP; in tg3_set_rxfh()
12787 if (!rxfh->indir) in tg3_set_rxfh()
12791 tp->rss_ind_tbl[i] = rxfh->indir[i]; in tg3_set_rxfh()
12812 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12813 channel->max_tx = tp->txq_max; in tg3_get_channels()
12816 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12817 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12819 if (tp->rxq_req) in tg3_get_channels()
12820 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12822 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12824 if (tp->txq_req) in tg3_get_channels()
12825 channel->tx_count = tp->txq_req; in tg3_get_channels()
12827 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12837 return -EOPNOTSUPP; in tg3_set_channels()
12839 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12840 channel->tx_count > tp->txq_max) in tg3_set_channels()
12841 return -EINVAL; in tg3_set_channels()
12843 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12844 tp->txq_req = channel->tx_count; in tg3_set_channels()
12898 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12910 if (tp->hw_stats) in tg3_get_ethtool_stats()
12956 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12957 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12965 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
12998 return -EIO; in tg3_test_nvram()
13025 return -EIO; in tg3_test_nvram()
13032 return -EIO; in tg3_test_nvram()
13036 return -ENOMEM; in tg3_test_nvram()
13038 err = -EIO; in tg3_test_nvram()
13070 err = -EIO; in tg3_test_nvram()
13104 err = -EIO; in tg3_test_nvram()
13117 err = -EIO; in tg3_test_nvram()
13137 return -ENOMEM; in tg3_test_nvram()
13155 if (!netif_running(tp->dev)) in tg3_test_link()
13156 return -ENODEV; in tg3_test_link()
13158 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13164 if (tp->link_up) in tg3_test_link()
13171 return -EIO; in tg3_test_link()
13352 /* Determine the read-only value. */ in tg3_test_registers()
13355 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13362 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13367 * make sure the read-only bits are not changed and the in tg3_test_registers()
13374 /* Test the read-only bits. */ in tg3_test_registers()
13389 netdev_err(tp->dev, in tg3_test_registers()
13392 return -EIO; in tg3_test_registers()
13408 return -EIO; in tg3_do_mem_test()
13518 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13520 tnapi = &tp->napi[0]; in tg3_run_loopback()
13521 rnapi = &tp->napi[0]; in tg3_run_loopback()
13522 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13524 rnapi = &tp->napi[1]; in tg3_run_loopback()
13526 tnapi = &tp->napi[1]; in tg3_run_loopback()
13528 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13530 err = -EIO; in tg3_run_loopback()
13533 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13535 return -ENOMEM; in tg3_run_loopback()
13538 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13553 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13557 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13568 th->check = 0; in tg3_run_loopback()
13599 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13600 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13602 return -EIO; in tg3_run_loopback()
13605 val = tnapi->tx_prod; in tg3_run_loopback()
13606 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13607 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13609 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13610 rnapi->coal_now); in tg3_run_loopback()
13614 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13619 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13621 return -EIO; in tg3_run_loopback()
13624 tnapi->tx_prod++; in tg3_run_loopback()
13629 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13630 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13636 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13641 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13642 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13643 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13648 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13651 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13659 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13660 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13661 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13663 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13664 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13667 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13668 - ETH_FCS_LEN; in tg3_run_loopback()
13674 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13681 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13682 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13688 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13689 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13692 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13693 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13698 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13725 int err = -EIO; in tg3_test_loopback()
13729 if (tp->dma_limit) in tg3_test_loopback()
13730 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13732 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13733 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13735 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13761 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13780 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13824 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13825 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13830 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13833 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13842 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13844 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13846 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13856 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13860 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13863 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13881 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13885 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13890 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13895 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13898 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13903 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13924 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13936 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13938 if (stmpconf->tx_type != HWTSTAMP_TX_ON && in tg3_hwtstamp_set()
13939 stmpconf->tx_type != HWTSTAMP_TX_OFF) in tg3_hwtstamp_set()
13940 return -ERANGE; in tg3_hwtstamp_set()
13942 switch (stmpconf->rx_filter) { in tg3_hwtstamp_set()
13944 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13947 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13951 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13955 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13959 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13963 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13967 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13971 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13975 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13979 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13983 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13987 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13991 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13995 return -ERANGE; in tg3_hwtstamp_set()
13998 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
14000 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
14002 if (stmpconf->tx_type == HWTSTAMP_TX_ON) in tg3_hwtstamp_set()
14016 return -EOPNOTSUPP; in tg3_hwtstamp_get()
14018 stmpconf->flags = 0; in tg3_hwtstamp_get()
14019 stmpconf->tx_type = tg3_flag(tp, TX_TSTAMP_EN) ? in tg3_hwtstamp_get()
14022 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
14024 stmpconf->rx_filter = HWTSTAMP_FILTER_NONE; in tg3_hwtstamp_get()
14027 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; in tg3_hwtstamp_get()
14030 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; in tg3_hwtstamp_get()
14033 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; in tg3_hwtstamp_get()
14036 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; in tg3_hwtstamp_get()
14039 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; in tg3_hwtstamp_get()
14042 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; in tg3_hwtstamp_get()
14045 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; in tg3_hwtstamp_get()
14048 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC; in tg3_hwtstamp_get()
14051 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; in tg3_hwtstamp_get()
14054 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; in tg3_hwtstamp_get()
14057 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ; in tg3_hwtstamp_get()
14060 stmpconf->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; in tg3_hwtstamp_get()
14064 return -ERANGE; in tg3_hwtstamp_get()
14078 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14079 return -EAGAIN; in tg3_ioctl()
14080 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14086 data->phy_id = tp->phy_addr; in tg3_ioctl()
14092 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14096 return -EAGAIN; in tg3_ioctl()
14098 spin_lock_bh(&tp->lock); in tg3_ioctl()
14099 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14100 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14101 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14103 data->val_out = mii_regval; in tg3_ioctl()
14109 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14113 return -EAGAIN; in tg3_ioctl()
14115 spin_lock_bh(&tp->lock); in tg3_ioctl()
14116 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14117 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14118 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14126 return -EOPNOTSUPP; in tg3_ioctl()
14136 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14156 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14157 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14158 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14159 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14160 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14161 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14162 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14163 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14164 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14165 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14166 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14167 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14168 return -EINVAL; in tg3_set_coalesce()
14171 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14172 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14173 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14174 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14175 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14176 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14177 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14178 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14179 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14183 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14193 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14194 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14195 return -EOPNOTSUPP; in tg3_set_eee()
14198 if (!linkmode_equal(edata->advertised, tp->eee.advertised)) { in tg3_set_eee()
14199 netdev_warn(tp->dev, in tg3_set_eee()
14201 return -EINVAL; in tg3_set_eee()
14204 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14205 netdev_warn(tp->dev, in tg3_set_eee()
14208 return -EINVAL; in tg3_set_eee()
14211 tp->eee.eee_enabled = edata->eee_enabled; in tg3_set_eee()
14212 tp->eee.tx_lpi_enabled = edata->tx_lpi_enabled; in tg3_set_eee()
14213 tp->eee.tx_lpi_timer = edata->tx_lpi_timer; in tg3_set_eee()
14215 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14218 if (netif_running(tp->dev)) { in tg3_set_eee()
14232 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14233 netdev_warn(tp->dev, in tg3_get_eee()
14235 return -EOPNOTSUPP; in tg3_get_eee()
14238 *edata = tp->eee; in tg3_get_eee()
14289 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14290 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14291 *stats = tp->net_stats_prev; in tg3_get_stats64()
14292 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14297 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14315 WRITE_ONCE(dev->mtu, new_mtu); in tg3_set_mtu()
14405 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14422 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14432 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14451 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14455 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14458 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14461 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14465 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14484 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14485 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14489 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14490 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14493 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14494 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14498 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14499 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14503 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14504 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14508 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14509 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14513 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14514 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14523 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14526 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14529 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14532 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14535 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14538 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14541 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14559 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14563 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14570 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14580 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14605 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14608 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14611 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14614 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14617 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14623 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14626 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14628 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14632 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14636 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14654 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14656 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14665 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14668 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14673 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14676 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14703 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14707 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14717 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14720 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14725 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14732 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14738 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14744 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14750 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14758 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14760 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14772 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14774 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14786 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14794 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14798 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14802 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14809 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14815 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14818 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14821 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14831 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14845 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14847 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14859 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14869 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14872 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14886 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14897 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14900 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14910 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14933 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14934 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14939 tp->nvram_size = in tg3_get_5720_nvram_info()
14963 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14969 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14971 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14985 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14993 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14998 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
15002 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
15006 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15028 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
15037 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
15043 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
15049 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
15053 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15063 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
15106 netdev_warn(tp->dev, in tg3_nvram_init()
15113 tp->nvram_size = 0; in tg3_nvram_init()
15139 if (tp->nvram_size == 0) in tg3_nvram_init()
15228 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15230 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15240 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15241 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15258 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15271 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15304 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15307 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15309 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15321 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15325 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15329 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15336 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15341 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15344 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15349 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15355 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15359 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15361 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15369 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15370 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15373 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15377 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15379 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15380 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15397 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15404 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15408 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15410 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15413 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15419 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15430 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15432 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15443 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15447 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15450 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15483 return -EBUSY; in tg3_ape_otp_read()
15502 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15506 * configuration is a 32-bit value that straddles the alignment boundary.
15507 * We do two 32-bit reads and then shift and merge the results.
15539 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15540 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15545 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15554 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15555 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15556 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15557 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15558 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15559 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15561 tp->old_link = -1; in tg3_phy_init_link_config()
15572 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15575 switch (tp->pci_fn) { in tg3_phy_probe()
15577 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15580 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15583 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15586 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15592 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15593 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15594 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15609 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15623 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15625 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15627 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15629 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15641 tp->phy_id = p->phy_id; in tg3_phy_probe()
15650 return -ENODEV; in tg3_phy_probe()
15653 if (!tp->phy_id || in tg3_phy_probe()
15654 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15655 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15659 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15668 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15670 linkmode_zero(tp->eee.supported); in tg3_phy_probe()
15672 tp->eee.supported); in tg3_phy_probe()
15674 tp->eee.supported); in tg3_phy_probe()
15675 linkmode_copy(tp->eee.advertised, tp->eee.supported); in tg3_phy_probe()
15677 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15678 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15679 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15684 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15685 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15702 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15703 tp->link_config.flowctrl); in tg3_phy_probe()
15711 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15745 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15746 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15757 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15761 if (tp->board_part_number[0]) in tg3_read_vpd()
15766 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15767 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15768 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15769 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15770 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15774 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15775 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15776 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15777 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15778 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15779 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15780 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15781 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15785 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15786 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15787 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15788 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15789 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15790 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15791 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15792 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15793 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15794 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15795 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15796 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15800 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15801 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15802 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15803 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15804 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15805 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15806 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15807 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15811 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15814 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15854 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15857 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15861 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15867 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15878 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15896 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15903 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15943 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15944 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15948 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15949 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15950 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15974 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15982 offset += val - start; in tg3_read_mgmtfw_ver()
15984 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15986 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15987 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15996 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
15997 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
16001 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
16032 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
16037 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
16039 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
16067 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16068 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16077 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16081 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16106 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16129 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16132 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16133 if (peer && peer != tp->pdev) in tg3_find_peer()
16137 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16138 * tp->pdev in that case. in tg3_find_peer()
16141 peer = tp->pdev; in tg3_find_peer()
16156 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16165 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16166 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16167 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16168 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16169 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16170 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16171 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16172 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16173 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16174 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16175 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16177 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16178 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16179 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16180 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16181 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16182 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16183 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16184 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16185 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16191 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16198 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16201 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16249 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16252 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16254 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16279 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16281 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16283 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16288 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16290 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16292 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16293 tp->misc_host_ctrl); in tg3_get_invariants()
16303 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16306 * non-zero address during special cycles. However, only in tg3_get_invariants()
16307 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16334 while (pci_id->vendor != 0) { in tg3_get_invariants()
16335 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16341 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16342 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16345 if (bridge->subordinate && in tg3_get_invariants()
16346 (bridge->subordinate->number == in tg3_get_invariants()
16347 tp->pdev->bus->number)) { in tg3_get_invariants()
16367 while (pci_id->vendor != 0) { in tg3_get_invariants()
16368 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16369 pci_id->device, in tg3_get_invariants()
16375 if (bridge->subordinate && in tg3_get_invariants()
16376 (bridge->subordinate->number <= in tg3_get_invariants()
16377 tp->pdev->bus->number) && in tg3_get_invariants()
16378 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16379 tp->pdev->bus->number)) { in tg3_get_invariants()
16388 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16389 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16390 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16395 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16403 if (bridge && bridge->subordinate && in tg3_get_invariants()
16404 (bridge->subordinate->number <= in tg3_get_invariants()
16405 tp->pdev->bus->number) && in tg3_get_invariants()
16406 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16407 tp->pdev->bus->number)) { in tg3_get_invariants()
16417 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16439 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16441 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16457 tp->fw_needed = NULL; in tg3_get_invariants()
16461 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16464 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16466 tp->irq_max = 1; in tg3_get_invariants()
16474 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16484 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16488 tp->txq_max = 1; in tg3_get_invariants()
16489 tp->rxq_max = 1; in tg3_get_invariants()
16490 if (tp->irq_max > 1) { in tg3_get_invariants()
16491 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16496 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16504 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16521 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16524 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16529 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16551 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16552 if (!tp->pcix_cap) { in tg3_get_invariants()
16553 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16554 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16555 return -EIO; in tg3_get_invariants()
16572 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16573 &tp->pci_cacheline_sz); in tg3_get_invariants()
16574 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16575 &tp->pci_lat_timer); in tg3_get_invariants()
16577 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16578 tp->pci_lat_timer = 64; in tg3_get_invariants()
16579 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16580 tp->pci_lat_timer); in tg3_get_invariants()
16583 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16584 * situation is decided before the first MMIO register access. in tg3_get_invariants()
16592 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16606 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16607 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16611 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16612 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16616 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16618 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16627 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16631 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16635 tp->read32 = tg3_read32; in tg3_get_invariants()
16636 tp->write32 = tg3_write32; in tg3_get_invariants()
16637 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16638 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16639 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16640 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16644 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16655 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16659 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16661 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16665 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16666 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16667 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16668 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16669 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16670 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16672 iounmap(tp->regs); in tg3_get_invariants()
16673 tp->regs = NULL; in tg3_get_invariants()
16675 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16677 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16680 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16681 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16682 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16683 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16686 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16700 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16704 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16705 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16707 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16717 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16719 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16724 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16725 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16741 tp->fw_needed = NULL; in tg3_get_invariants()
16751 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16755 tp->ape_hb_interval = in tg3_get_invariants()
16759 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16764 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16767 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16770 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16773 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16778 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16780 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16781 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16783 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16786 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16791 tp->grc_local_ctrl |= in tg3_get_invariants()
16800 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16814 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16821 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16822 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16823 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16827 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16829 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16832 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16840 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16841 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16842 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16843 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16844 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16846 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16851 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16852 if (tp->phy_otp == 0) in tg3_get_invariants()
16853 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16857 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16859 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16861 tp->coalesce_mode = 0; in tg3_get_invariants()
16864 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16871 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16872 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16895 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16905 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16919 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16935 tp->fw_needed = NULL; in tg3_get_invariants()
16949 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16952 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16953 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16954 tp->misc_host_ctrl); in tg3_get_invariants()
16959 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16961 tp->mac_mode = 0; in tg3_get_invariants()
16964 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16968 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16976 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16977 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16980 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16982 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16998 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
17000 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
17001 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
17006 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
17014 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
17015 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
17018 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
17020 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
17024 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
17025 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
17026 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
17028 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
17036 tp->rx_std_max_post = 8; in tg3_get_invariants()
17039 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
17051 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
17055 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
17070 if (tp->pci_fn & 1) in tg3_get_device_address()
17072 if (tp->pci_fn > 1) in tg3_get_device_address()
17117 return -EINVAL; in tg3_get_device_address()
17130 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17163 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17166 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17167 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17297 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17316 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17318 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17320 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17327 ret = -ENODEV; in tg3_do_test_dma()
17359 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17362 ret = -ENOMEM; in tg3_test_dma()
17366 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17369 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17376 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17380 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17382 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17395 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17397 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17402 tp->dma_rwctrl |= in tg3_test_dma()
17408 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17411 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17413 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17417 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17421 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17426 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17436 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17438 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17441 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17451 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17452 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17453 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17464 dev_err(&tp->pdev->dev, in tg3_test_dma()
17473 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17483 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17485 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17486 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17487 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17490 dev_err(&tp->pdev->dev, in tg3_test_dma()
17493 ret = -ENODEV; in tg3_test_dma()
17504 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17511 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17512 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17515 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17518 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17522 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17530 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17532 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17534 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17537 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17539 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17541 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17544 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17546 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17548 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17551 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17553 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17557 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17559 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17561 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17564 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17566 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17568 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17571 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17573 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17575 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17579 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17580 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17585 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17645 strcat(str, ":32-bit"); in tg3_bus_string()
17647 strcat(str, ":64-bit"); in tg3_bus_string()
17653 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17656 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17657 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17658 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17659 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17660 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17661 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17662 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17663 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17664 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17665 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17667 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17669 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17670 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17671 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17672 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17676 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17677 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17678 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17696 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17702 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17710 err = -ENOMEM; in tg3_init_one()
17714 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17717 tp->pdev = pdev; in tg3_init_one()
17718 tp->dev = dev; in tg3_init_one()
17719 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17720 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17721 tp->irq_sync = 1; in tg3_init_one()
17722 tp->pcierr_recovery = false; in tg3_init_one()
17725 tp->msg_enable = tg3_debug; in tg3_init_one()
17727 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17747 tp->misc_host_ctrl = in tg3_init_one()
17753 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17757 * are running in big-endian mode. in tg3_init_one()
17759 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17762 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17764 spin_lock_init(&tp->lock); in tg3_init_one()
17765 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17766 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17768 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17769 if (!tp->regs) { in tg3_init_one()
17770 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17771 err = -ENOMEM; in tg3_init_one()
17775 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17776 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17777 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17778 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17779 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17780 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17781 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17782 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17783 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17785 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17786 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17787 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17788 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17789 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17791 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17792 if (!tp->aperegs) { in tg3_init_one()
17793 dev_err(&pdev->dev, in tg3_init_one()
17795 err = -ENOMEM; in tg3_init_one()
17800 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17801 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17803 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17804 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17805 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17806 dev->irq = pdev->irq; in tg3_init_one()
17810 dev_err(&pdev->dev, in tg3_init_one()
17816 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17817 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17818 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17836 err = dma_set_mask(&pdev->dev, dma_mask); in tg3_init_one()
17839 err = dma_set_coherent_mask(&pdev->dev, in tg3_init_one()
17842 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17849 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in tg3_init_one()
17851 dev_err(&pdev->dev, in tg3_init_one()
17890 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17892 dev->vlan_features |= features; in tg3_init_one()
17896 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17904 dev->hw_features |= features; in tg3_init_one()
17905 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17907 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17908 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17909 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17915 tp->rx_pending = 63; in tg3_init_one()
17920 dev_err(&pdev->dev, in tg3_init_one()
17929 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17930 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17932 tnapi->tp = tp; in tg3_init_one()
17933 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17935 tnapi->int_mbox = intmbx; in tg3_init_one()
17938 tnapi->consmbox = rcvmbx; in tg3_init_one()
17939 tnapi->prodmbox = sndmbx; in tg3_init_one()
17942 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17944 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17962 sndmbx -= 0x4; in tg3_init_one()
17982 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
18001 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
18007 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
18008 &tp->pdev->dev); in tg3_init_one()
18009 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
18010 tp->ptp_clock = NULL; in tg3_init_one()
18014 tp->board_part_number, in tg3_init_one()
18017 dev->dev_addr); in tg3_init_one()
18019 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
18022 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
18023 ethtype = "10/100Base-TX"; in tg3_init_one()
18024 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
18025 ethtype = "1000Base-SX"; in tg3_init_one()
18027 ethtype = "10/100/1000Base-T"; in tg3_init_one()
18032 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
18033 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
18037 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
18039 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
18042 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
18043 tp->dma_rwctrl, in tg3_init_one()
18044 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
18045 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
18052 if (tp->aperegs) { in tg3_init_one()
18053 iounmap(tp->aperegs); in tg3_init_one()
18054 tp->aperegs = NULL; in tg3_init_one()
18058 if (tp->regs) { in tg3_init_one()
18059 iounmap(tp->regs); in tg3_init_one()
18060 tp->regs = NULL; in tg3_init_one()
18084 release_firmware(tp->fw); in tg3_remove_one()
18094 if (tp->aperegs) { in tg3_remove_one()
18095 iounmap(tp->aperegs); in tg3_remove_one()
18096 tp->aperegs = NULL; in tg3_remove_one()
18098 if (tp->regs) { in tg3_remove_one()
18099 iounmap(tp->regs); in tg3_remove_one()
18100 tp->regs = NULL; in tg3_remove_one()
18163 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18248 pdev->current_state != PCI_D3cold && in tg3_shutdown()
18249 pdev->current_state != PCI_UNKNOWN) { in tg3_shutdown()
18266 * tg3_io_error_detected - called when PCI error is detected
18288 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18293 tp->pcierr_recovery = true; in tg3_io_error_detected()
18303 /* Clean up software state, even if MMIO is blocked */ in tg3_io_error_detected()
18327 * tg3_io_slot_reset - called after the pci bus has been reset.
18330 * Restart the card from scratch, as if from a cold-boot.
18345 dev_err(&pdev->dev, in tg3_io_slot_reset()
18346 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18378 * tg3_io_resume - called when traffic can start flowing again.
18419 tp->pcierr_recovery = false; in tg3_io_resume()