Lines Matching +full:0 +full:x4a8
37 #define DMA_MAX_BURST_LENGTH 0x10
41 #define CLEAR_ALL_HFB 0xFF
56 #define STATUS_RX_EXT_MASK 0x1FFFFF
57 #define STATUS_RX_CSUM_MASK 0xFFFF
58 #define STATUS_RX_CSUM_OK 0x10000
59 #define STATUS_RX_CSUM_FR 0x20000
60 #define STATUS_RX_PROTO_TCP 0
66 #define STATUS_FILTER_INDEX_MASK 0xFFFF
68 #define STATUS_TX_CSUM_START_MASK 0X7FFF
70 #define STATUS_TX_CSUM_PROTO_UDP 0x8000
71 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF
72 #define STATUS_TX_CSUM_LV 0x80000000
75 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */
76 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */
77 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */
96 u32 pkt; /* RO (0x428) Received pkt count*/
114 u32 rcrc; /* RO (0x470),# of CRC match pkt */
120 u32 pkts; /* RO (0x4a8) Transmited pkt */
138 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */
182 #define UMAC_MIB_START 0x400
184 #define UMAC_MDIO_CMD 0x614
190 #define MDIO_PMD_MASK 0x1F
192 #define MDIO_REG_MASK 0x1F
194 #define UMAC_RBUF_OVFL_CNT_V1 0x61C
195 #define RBUF_OVFL_CNT_V2 0x80
196 #define RBUF_OVFL_CNT_V3PLUS 0x94
198 #define UMAC_MPD_CTRL 0x620
199 #define MPD_EN (1 << 0)
202 #define MPD_MSEQ_LEN_MASK 0xFF
204 #define UMAC_MPD_PW_MS 0x624
205 #define UMAC_MPD_PW_LS 0x628
206 #define UMAC_RBUF_ERR_CNT_V1 0x634
207 #define RBUF_ERR_CNT_V2 0x84
208 #define RBUF_ERR_CNT_V3PLUS 0x98
209 #define UMAC_MDF_ERR_CNT 0x638
210 #define UMAC_MDF_CTRL 0x650
211 #define UMAC_MDF_ADDR 0x654
212 #define UMAC_MIB_CTRL 0x580
213 #define MIB_RESET_RX (1 << 0)
217 #define RBUF_CTRL 0x00
218 #define RBUF_64B_EN (1 << 0)
222 #define RBUF_STATUS 0x0C
223 #define RBUF_STATUS_WOL (1 << 0)
227 #define RBUF_CHK_CTRL 0x14
228 #define RBUF_RXCHK_EN (1 << 0)
232 #define RBUF_ENERGY_CTRL 0x9c
233 #define RBUF_EEE_EN (1 << 0)
236 #define RBUF_TBUF_SIZE_CTRL 0xb4
238 #define RBUF_HFB_CTRL_V1 0x38
240 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000
241 #define RBUF_HFB_EN (1 << 0)
245 #define RBUF_HFB_LEN_V1 0x3C
246 #define RBUF_FLTR_LEN_MASK 0xFF
249 #define TBUF_CTRL 0x00
250 #define TBUF_64B_EN (1 << 0)
251 #define TBUF_BP_MC 0x0C
252 #define TBUF_ENERGY_CTRL 0x14
253 #define TBUF_EEE_EN (1 << 0)
256 #define TBUF_CTRL_V1 0x80
257 #define TBUF_BP_MC_V1 0xA0
259 #define HFB_CTRL 0x00
260 #define HFB_FLT_ENABLE_V3PLUS 0x04
261 #define HFB_FLT_LEN_V2 0x04
262 #define HFB_FLT_LEN_V3PLUS 0x1C
265 #define INTRL2_CPU_STAT 0x00
266 #define INTRL2_CPU_SET 0x04
267 #define INTRL2_CPU_CLEAR 0x08
268 #define INTRL2_CPU_MASK_STATUS 0x0C
269 #define INTRL2_CPU_MASK_SET 0x10
270 #define INTRL2_CPU_MASK_CLEAR 0x14
272 /* INTRL2 instance 0 definitions */
273 #define UMAC_IRQ_SCB (1 << 0)
305 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF
306 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF
310 #define GENET_SYS_OFF 0x0000
311 #define GENET_GR_BRIDGE_OFF 0x0040
312 #define GENET_EXT_OFF 0x0080
313 #define GENET_INTRL2_0_OFF 0x0200
314 #define GENET_INTRL2_1_OFF 0x0240
315 #define GENET_RBUF_OFF 0x0300
316 #define GENET_UMAC_OFF 0x0800
319 #define SYS_REV_CTRL 0x00
320 #define SYS_PORT_CTRL 0x04
321 #define PORT_MODE_INT_EPHY 0
329 #define SYS_RBUF_FLUSH_CTRL 0x08
330 #define SYS_TBUF_FLUSH_CTRL 0x0C
331 #define RBUF_FLUSH_CTRL_V1 0x04
334 #define EXT_EXT_PWR_MGMT 0x00
335 #define EXT_PWR_DOWN_BIAS (1 << 0)
350 #define EXT_RGMII_OOB_CTRL 0x0C
351 #define RGMII_MODE_EN_V123 (1 << 0)
357 #define EXT_GPHY_CTRL 0x1C
358 #define EXT_CFG_IDDQ_BIAS (1 << 0)
365 #define DMA_RING_SIZE (0x40)
369 #define DMA_RW_POINTER_MASK 0x1FF
370 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF
372 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF
374 #define DMA_P_INDEX_MASK 0xFFFF
375 #define DMA_C_INDEX_MASK 0xFFFF
378 #define DMA_RING_SIZE_MASK 0xFFFF
380 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF
383 #define DMA_INTR_THRESHOLD_MASK 0x01FF
386 #define DMA_XON_THREHOLD_MASK 0xFFFF
387 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF
391 #define DMA_FLOW_PERIOD_MASK 0xFFFF
392 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF
397 #define DMA_EN (1 << 0)
398 #define DMA_RING_BUF_EN_SHIFT 0x01
399 #define DMA_RING_BUF_EN_MASK 0xFFFF
403 #define DMA_DISABLED (1 << 0)
407 #define DMA_SCB_BURST_SIZE_MASK 0x1F
410 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF
413 #define DMA_BACKPRESSURE_MASK 0x1FFFF
417 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF
420 #define DMA_LITTLE_ENDIAN_MODE (1 << 0)
424 #define DMA_TIMEOUT_MASK 0xFFFF
428 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF
431 #define DMA_ARBITER_MODE_MASK 0x03
432 #define DMA_RING_BUF_PRIORITY_MASK 0x1F
436 #define DMA_RATE_ADJ_MASK 0xFF
439 #define DMA_BUFLENGTH_MASK 0x0fff
441 #define DMA_OWN 0x8000
442 #define DMA_EOP 0x4000
443 #define DMA_SOP 0x2000
444 #define DMA_WRAP 0x1000
446 #define DMA_TX_UNDERRUN 0x0200
447 #define DMA_TX_APPEND_CRC 0x0040
448 #define DMA_TX_OW_CRC 0x0020
449 #define DMA_TX_DO_CSUM 0x0010
453 #define DMA_RX_CHK_V3PLUS 0x8000
454 #define DMA_RX_CHK_V12 0x1000
455 #define DMA_RX_BRDCAST 0x0040
456 #define DMA_RX_MULT 0x0020
457 #define DMA_RX_LG 0x0010
458 #define DMA_RX_NO 0x0008
459 #define DMA_RX_RXER 0x0004
460 #define DMA_RX_CRC_ERROR 0x0002
461 #define DMA_RX_OV 0x0001
462 #define DMA_RX_FI_MASK 0x001F
463 #define DMA_RX_FI_SHIFT 0x0007
464 #define DMA_DESC_ALLOC_MASK 0x00FF
466 #define DMA_ARBITER_RR 0x00
467 #define DMA_ARBITER_WRR 0x01
468 #define DMA_ARBITER_SP 0x02
479 GENET_POWER_CABLE_SENSE = 0,
504 #define GENET_HAS_40BITS (1 << 0)
582 BCMGENET_RXNFC_STATE_UNUSED = 0,