Lines Matching +full:hsi +full:- +full:mac
1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
25 #include <linux/dma-mapping.h>
60 #include <linux/pci-tph.h>
61 #include <linux/bnxt/hsi.h>
95 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
96 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
97 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
98 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
100 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
101 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
102 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
103 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
104 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
105 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
106 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
107 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
108 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
109 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
110 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
111 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
112 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
113 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
114 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
115 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
116 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
117 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
118 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
119 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
120 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
121 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
122 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
123 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
124 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
125 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
126 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
127 [BCM57608] = { "Broadcom BCM57608 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb/400Gb Ethernet" },
128 [BCM57604] = { "Broadcom BCM57604 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
129 [BCM57602] = { "Broadcom BCM57602 NetXtreme-E 10Gb/25Gb/50Gb/100Gb Ethernet" },
130 [BCM57601] = { "Broadcom BCM57601 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb/400Gb Ethernet" },
131 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
132 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
133 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
134 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
135 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
136 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
137 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
138 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
139 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
140 [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" },
141 [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" },
142 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
143 [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" },
145 [NETXTREME_E_P7_VF_HV] = { "Broadcom BCM5760X Virtual Function for Hyper-V" },
330 writel(DB_CP_FLAGS | DB_RING_IDX(db, idx), (db)->doorbell)
333 bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ | DB_RING_IDX(db, idx),\
334 (db)->doorbell)
337 bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_MASK | \
338 DB_RING_IDX(db, idx), (db)->doorbell)
341 writel(DB_CP_REARM_FLAGS | DB_RING_IDX(db, idx), (db)->doorbell)
344 bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_ARM | \
345 DB_RING_IDX(db, idx), (db)->doorbell)
349 if (bp->flags & BNXT_FLAG_CHIP_P7)
351 else if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
359 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
367 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
368 bnxt_writeq(bp, db->db_key64 | DBR_TYPE_CQ_ARMALL |
369 DB_RING_IDX(db, idx), db->doorbell);
376 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
380 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
382 schedule_delayed_work(&bp->fw_reset_task, delay);
388 queue_work(bnxt_pf_wq, &bp->sp_task);
390 schedule_work(&bp->sp_task);
395 set_bit(event, &bp->sp_event);
401 if (!rxr->bnapi->in_reset) {
402 rxr->bnapi->in_reset = true;
403 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
404 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
406 set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
409 rxr->rx_next_cons = 0xffff;
415 struct bnxt_napi *bnapi = txr->bnapi;
417 if (bnapi->tx_fault)
420 netdev_err(bp->dev, "Invalid Tx completion (ring:%d tx_hw_cons:%u cons:%u prod:%u curr:%u)",
421 txr->txq_index, txr->tx_hw_cons,
422 txr->tx_cons, txr->tx_prod, curr);
424 bnapi->tx_fault = 1;
454 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
457 return md_dst->u.port_info.port_id;
465 bnxt_db_write(bp, &txr->tx_db, prod);
466 txr->kick_pending = 0;
479 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
480 struct pci_dev *pdev = bp->pdev;
488 if (unlikely(i >= bp->tx_nr_rings)) {
495 txr = &bp->tx_ring[bp->tx_ring_map[i]];
496 prod = txr->tx_prod;
499 if (skb_shinfo(skb)->nr_frags > TX_MAX_FRAGS) {
501 skb_shinfo(skb)->nr_frags, TX_MAX_FRAGS);
510 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
512 if (net_ratelimit() && txr->kick_pending)
516 bp->tx_wake_thresh))
523 length = skb->len;
525 last_frag = skb_shinfo(skb)->nr_frags;
527 txbd = &txr->tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];
529 tx_buf = &txr->tx_buf_ring[RING_TX(bp, prod)];
530 tx_buf->skb = skb;
531 tx_buf->nr_frags = last_frag;
541 if (skb->vlan_proto == htons(ETH_P_8021Q))
545 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && ptp &&
546 ptp->tx_tstamp_en) {
547 if (bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP) {
549 tx_buf->is_ts_pkt = 1;
550 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
559 tx_buf->is_ts_pkt = 1;
560 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
562 ptp->txts_req[txts_prod].tx_seqid = seq_id;
563 ptp->txts_req[txts_prod].tx_hdr_off = hdr_off;
564 tx_buf->txts_prod = txts_prod;
568 if (unlikely(skb->no_fcs))
571 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh &&
573 struct tx_push_buffer *tx_push_buf = txr->tx_push;
574 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
575 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
576 void __iomem *db = txr->tx_db.doorbell;
577 void *pdata = tx_push_buf->data;
582 tx_push->tx_bd_len_flags_type =
590 if (skb->ip_summed == CHECKSUM_PARTIAL)
591 tx_push1->tx_bd_hsize_lflags =
594 tx_push1->tx_bd_hsize_lflags = 0;
596 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
597 tx_push1->tx_bd_cfa_action =
601 end = PTR_ALIGN(end, 8) - 1;
609 frag = &skb_shinfo(skb)->frags[j];
618 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
619 txbd->tx_bd_haddr = txr->data_mapping;
620 txbd->tx_bd_opaque = SET_TX_OPAQUE(bp, txr, prod, 2);
622 tx_push->tx_bd_opaque = txbd->tx_bd_opaque;
623 txbd = &txr->tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];
626 tx_push->doorbell =
628 DB_RING_IDX(&txr->tx_db, prod));
629 WRITE_ONCE(txr->tx_prod, prod);
631 tx_buf->is_push = 1;
632 netdev_tx_sent_queue(txq, skb->len);
639 (push_len - 16) << 1);
649 pad = BNXT_MIN_PKT_SIZE - length;
656 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
658 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
665 txbd->tx_bd_haddr = cpu_to_le64(mapping);
666 txbd->tx_bd_opaque = SET_TX_OPAQUE(bp, txr, prod, 2 + last_frag);
670 &txr->tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];
672 txbd1->tx_bd_hsize_lflags = lflags;
674 bool udp_gso = !!(skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4);
677 if (skb->encapsulation) {
690 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO |
692 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
693 length = skb_shinfo(skb)->gso_size;
694 txbd1->tx_bd_mss = cpu_to_le32(length);
696 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
697 txbd1->tx_bd_hsize_lflags |=
699 txbd1->tx_bd_mss = 0;
704 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
705 skb->len);
710 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
712 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
713 txbd1->tx_bd_cfa_action =
717 frag = &skb_shinfo(skb)->frags[i];
719 txbd = &txr->tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];
722 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
725 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
728 tx_buf = &txr->tx_buf_ring[RING_TX(bp, prod)];
732 txbd->tx_bd_haddr = cpu_to_le64(mapping);
735 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
739 txbd->tx_bd_len_flags_type =
743 netdev_tx_sent_queue(txq, skb->len);
748 WRITE_ONCE(txr->tx_prod, prod);
753 if (free_size >= bp->tx_wake_thresh)
754 txbd0->tx_bd_len_flags_type |=
756 txr->kick_pending = 1;
762 if (netdev_xmit_more() && !tx_buf->is_push) {
763 txbd0->tx_bd_len_flags_type &=
769 bp->tx_wake_thresh);
777 prod = txr->tx_prod;
778 tx_buf = &txr->tx_buf_ring[RING_TX(bp, prod)];
779 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
786 tx_buf = &txr->tx_buf_ring[RING_TX(bp, prod)];
787 frag = &skb_shinfo(skb)->frags[i];
788 netmem_dma_unmap_page_attrs(&pdev->dev,
798 txr->tx_buf_ring[RING_TX(bp, txr->tx_prod)].is_ts_pkt = 0;
799 atomic64_inc(&bp->ptp_cfg->stats.ts_err);
800 if (!(bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP))
802 ptp->txts_req[txts_prod].tx_skb = ERR_PTR(-EIO);
804 if (txr->kick_pending)
805 bnxt_txr_db_kick(bp, txr, txr->tx_prod);
806 txr->tx_buf_ring[RING_TX(bp, txr->tx_prod)].skb = NULL;
815 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
816 struct pci_dev *pdev = bp->pdev;
817 u16 hw_cons = txr->tx_hw_cons;
819 u16 cons = txr->tx_cons;
830 tx_buf = &txr->tx_buf_ring[RING_TX(bp, cons)];
831 skb = tx_buf->skb;
838 is_ts_pkt = tx_buf->is_ts_pkt;
839 if (is_ts_pkt && (bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP)) {
846 tx_bytes += skb->len;
847 tx_buf->skb = NULL;
848 tx_buf->is_ts_pkt = 0;
850 if (tx_buf->is_push) {
851 tx_buf->is_push = 0;
855 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
857 last = tx_buf->nr_frags;
860 frag = &skb_shinfo(skb)->frags[j];
862 tx_buf = &txr->tx_buf_ring[RING_TX(bp, cons)];
863 netmem_dma_unmap_page_attrs(&pdev->dev,
872 bnxt_get_tx_ts_p5(bp, skb, tx_buf->txts_prod);
883 WRITE_ONCE(txr->tx_cons, cons);
886 bnxt_tx_avail(bp, txr), bp->tx_wake_thresh,
887 READ_ONCE(txr->dev_state) == BNXT_DEV_STATE_CLOSING);
899 if (txr->tx_hw_cons != RING_TX(bp, txr->tx_cons))
903 bnapi->events &= ~BNXT_TX_CMP_EVENT;
908 return rxr->need_head_pool || PAGE_SIZE > BNXT_RX_PAGE_SIZE;
919 page = page_pool_dev_alloc_frag(rxr->page_pool, offset,
922 page = page_pool_dev_alloc_pages(rxr->page_pool);
940 netmem = page_pool_alloc_frag_netmem(rxr->page_pool, offset, BNXT_RX_PAGE_SIZE, gfp);
942 netmem = page_pool_alloc_netmems(rxr->page_pool, gfp);
959 page = page_pool_alloc_frag(rxr->head_pool, &offset,
960 bp->rx_buf_size, gfp);
964 *mapping = page_pool_get_dma_addr(page) + bp->rx_dma_offset + offset;
971 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(bp, prod)][RX_IDX(prod)];
972 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[RING_RX(bp, prod)];
981 return -ENOMEM;
983 mapping += bp->rx_dma_offset;
984 rx_buf->data = page;
985 rx_buf->data_ptr = page_address(page) + offset + bp->rx_offset;
990 return -ENOMEM;
992 rx_buf->data = data;
993 rx_buf->data_ptr = data + bp->rx_offset;
995 rx_buf->mapping = mapping;
997 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
1003 u16 prod = rxr->rx_prod;
1005 struct bnxt *bp = rxr->bnapi->bp;
1008 prod_rx_buf = &rxr->rx_buf_ring[RING_RX(bp, prod)];
1009 cons_rx_buf = &rxr->rx_buf_ring[cons];
1011 prod_rx_buf->data = data;
1012 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
1014 prod_rx_buf->mapping = cons_rx_buf->mapping;
1016 prod_bd = &rxr->rx_desc_ring[RX_RING(bp, prod)][RX_IDX(prod)];
1017 cons_bd = &rxr->rx_desc_ring[RX_RING(bp, cons)][RX_IDX(cons)];
1019 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
1024 u16 next, max = rxr->rx_agg_bmap_size;
1026 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
1028 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
1036 &rxr->rx_agg_desc_ring[RX_AGG_RING(bp, prod)][RX_IDX(prod)];
1038 u16 sw_prod = rxr->rx_sw_agg_prod;
1045 return -ENOMEM;
1047 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
1050 __set_bit(sw_prod, rxr->rx_agg_bmap);
1051 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
1052 rxr->rx_sw_agg_prod = RING_RX_AGG(bp, NEXT_RX_AGG(sw_prod));
1054 rx_agg_buf->netmem = netmem;
1055 rx_agg_buf->offset = offset;
1056 rx_agg_buf->mapping = mapping;
1057 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
1058 rxbd->rx_bd_opaque = sw_prod;
1070 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1078 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
1080 return &tpa_info->agg_arr[curr];
1086 struct bnxt_napi *bnapi = cpr->bnapi;
1087 struct bnxt *bp = bnapi->bp;
1088 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1089 u16 prod = rxr->rx_agg_prod;
1090 u16 sw_prod = rxr->rx_sw_agg_prod;
1094 if ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) && tpa)
1108 cons = agg->rx_agg_cmp_opaque;
1109 __clear_bit(cons, rxr->rx_agg_bmap);
1111 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
1114 __set_bit(sw_prod, rxr->rx_agg_bmap);
1115 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
1116 cons_rx_buf = &rxr->rx_agg_ring[cons];
1119 * set cons_rx_buf->netmem to 0 first.
1121 netmem = cons_rx_buf->netmem;
1122 cons_rx_buf->netmem = 0;
1123 prod_rx_buf->netmem = netmem;
1124 prod_rx_buf->offset = cons_rx_buf->offset;
1126 prod_rx_buf->mapping = cons_rx_buf->mapping;
1128 prod_bd = &rxr->rx_agg_desc_ring[RX_AGG_RING(bp, prod)][RX_IDX(prod)];
1130 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
1131 prod_bd->rx_bd_opaque = sw_prod;
1136 rxr->rx_agg_prod = prod;
1137 rxr->rx_sw_agg_prod = sw_prod;
1148 u16 prod = rxr->rx_prod;
1157 dma_addr -= bp->rx_dma_offset;
1158 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, BNXT_RX_PAGE_SIZE,
1159 bp->rx_dir);
1160 skb = napi_build_skb(data_ptr - bp->rx_offset, BNXT_RX_PAGE_SIZE);
1162 page_pool_recycle_direct(rxr->page_pool, page);
1166 skb_reserve(skb, bp->rx_offset);
1182 u16 prod = rxr->rx_prod;
1191 dma_addr -= bp->rx_dma_offset;
1192 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, BNXT_RX_PAGE_SIZE,
1193 bp->rx_dir);
1196 payload = eth_get_headlen(bp->dev, data_ptr, len);
1198 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
1200 page_pool_recycle_direct(rxr->page_pool, page);
1205 off = (void *)data_ptr - page_address(page);
1207 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
1210 frag = &skb_shinfo(skb)->frags[0];
1213 skb->data_len -= payload;
1214 skb->tail += payload;
1225 u16 prod = rxr->rx_prod;
1235 skb = napi_build_skb(data, bp->rx_buf_size);
1236 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
1237 bp->rx_dir);
1239 page_pool_free_va(rxr->head_pool, data, true);
1244 skb_reserve(skb, bp->rx_offset);
1255 struct bnxt_napi *bnapi = cpr->bnapi;
1262 rxr = bnapi->rx_ring;
1263 prod = rxr->rx_agg_prod;
1265 if ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) && tpa)
1283 cons = agg->rx_agg_cmp_opaque;
1284 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1287 cons_rx_buf = &rxr->rx_agg_ring[cons];
1289 skb_add_rx_frag_netmem(skb, i, cons_rx_buf->netmem,
1290 cons_rx_buf->offset,
1293 skb_frag_t *frag = &shinfo->frags[i];
1295 skb_frag_fill_netmem_desc(frag, cons_rx_buf->netmem,
1296 cons_rx_buf->offset,
1298 shinfo->nr_frags = i + 1;
1300 __clear_bit(cons, rxr->rx_agg_bmap);
1306 netmem = cons_rx_buf->netmem;
1307 cons_rx_buf->netmem = 0;
1314 skb->len -= frag_len;
1315 skb->data_len -= frag_len;
1316 skb->truesize -= BNXT_RX_PAGE_SIZE;
1319 --shinfo->nr_frags;
1320 cons_rx_buf->netmem = netmem;
1325 rxr->rx_agg_prod = prod;
1326 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1330 page_pool_dma_sync_netmem_for_cpu(rxr->page_pool, netmem, 0,
1336 rxr->rx_agg_prod = prod;
1367 shinfo->nr_frags = 0;
1373 shinfo->nr_frags = agg_bufs;
1374 shinfo->xdp_frags_size = total_frag_len;
1388 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1396 struct bnxt *bp = bnapi->bp;
1397 struct pci_dev *pdev = bp->pdev;
1400 skb = napi_alloc_skb(&bnapi->napi, len);
1404 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copybreak,
1405 bp->rx_dir);
1407 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1410 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copybreak,
1411 bp->rx_dir);
1431 u8 *data = xdp->data;
1434 len = xdp->data_end - xdp->data_meta;
1435 metasize = xdp->data - xdp->data_meta;
1436 data = xdp->data_meta;
1460 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1466 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
1474 return -EBUSY;
1482 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1485 if (test_bit(idx, map->agg_idx_bmap))
1486 idx = find_first_zero_bit(map->agg_idx_bmap,
1488 __set_bit(idx, map->agg_idx_bmap);
1489 map->agg_id_tbl[agg_id] = idx;
1495 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1497 __clear_bit(idx, map->agg_idx_bmap);
1502 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1504 return map->agg_id_tbl[agg_id];
1511 tpa_info->cfa_code_valid = 1;
1512 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1513 tpa_info->vlan_valid = 0;
1514 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1515 tpa_info->vlan_valid = 1;
1516 tpa_info->metadata =
1517 le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1525 tpa_info->vlan_valid = 0;
1530 tpa_info->vlan_valid = 1;
1533 tpa_info->metadata = vlan_proto << 16 |
1548 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
1554 cons = tpa_start->rx_tpa_start_cmp_opaque;
1555 prod = rxr->rx_prod;
1556 cons_rx_buf = &rxr->rx_buf_ring[cons];
1557 prod_rx_buf = &rxr->rx_buf_ring[RING_RX(bp, prod)];
1558 tpa_info = &rxr->rx_tpa[agg_id];
1560 if (unlikely(cons != rxr->rx_next_cons ||
1562 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1563 cons, rxr->rx_next_cons,
1568 prod_rx_buf->data = tpa_info->data;
1569 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1571 mapping = tpa_info->mapping;
1572 prod_rx_buf->mapping = mapping;
1574 prod_bd = &rxr->rx_desc_ring[RX_RING(bp, prod)][RX_IDX(prod)];
1576 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1578 tpa_info->data = cons_rx_buf->data;
1579 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1580 cons_rx_buf->data = NULL;
1581 tpa_info->mapping = cons_rx_buf->mapping;
1583 tpa_info->len =
1584 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1587 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1588 tpa_info->gso_type = SKB_GSO_TCPV4;
1590 tpa_info->gso_type = SKB_GSO_TCPV6;
1591 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1594 tpa_info->gso_type = SKB_GSO_TCPV6;
1595 tpa_info->rss_hash =
1596 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1598 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1599 tpa_info->gso_type = 0;
1600 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1602 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1603 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1608 tpa_info->agg_count = 0;
1610 rxr->rx_prod = NEXT_RX(prod);
1612 rxr->rx_next_cons = RING_RX(bp, NEXT_RX(cons));
1613 cons_rx_buf = &rxr->rx_buf_ring[cons];
1615 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1616 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1617 cons_rx_buf->data = NULL;
1632 struct iphdr *iph = (struct iphdr *)skb->data;
1634 if (iph->protocol == IPPROTO_UDP)
1637 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1639 if (iph->nexthdr == IPPROTO_UDP)
1643 if (uh->check)
1644 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1646 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1659 u32 hdr_info = tpa_info->hdr_info;
1672 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1673 ETH_HLEN - 2));
1684 inner_ip_off -= 4;
1685 inner_mac_off -= 4;
1686 outer_ip_off -= 4;
1689 nw_off = inner_ip_off - ETH_HLEN;
1691 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1695 len = skb->len - skb_transport_offset(skb);
1697 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1702 len = skb->len - skb_transport_offset(skb);
1704 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1708 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1709 ETH_HLEN - 2));
1723 u32 hdr_info = tpa_info->hdr_info;
1730 nw_off = inner_ip_off - ETH_HLEN;
1732 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1737 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1738 ETH_HLEN - 2));
1760 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1763 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1768 len = skb->len - skb_transport_offset(skb);
1770 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1771 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1774 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1779 len = skb->len - skb_transport_offset(skb);
1781 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1788 bnxt_gro_tunnel(skb, skb->protocol);
1807 NAPI_GRO_CB(skb)->count = segs;
1808 skb_shinfo(skb)->gso_size =
1809 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1810 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1811 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
1815 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1823 * netdev (vf-rep or PF) the packet is destined to.
1829 /* if vf-rep dev is NULL, it must belong to the PF */
1830 return dev ? dev : bp->dev;
1840 struct bnxt_napi *bnapi = cpr->bnapi;
1841 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1842 struct net_device *dev = bp->dev;
1852 if (unlikely(bnapi->in_reset)) {
1856 return ERR_PTR(-EBUSY);
1860 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
1864 tpa_info = &rxr->rx_tpa[agg_id];
1865 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1866 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1867 agg_bufs, tpa_info->agg_count);
1868 agg_bufs = tpa_info->agg_count;
1870 tpa_info->agg_count = 0;
1874 gro = !!(bp->flags & BNXT_FLAG_GRO);
1878 tpa_info = &rxr->rx_tpa[agg_id];
1882 return ERR_PTR(-EBUSY);
1889 data = tpa_info->data;
1890 data_ptr = tpa_info->data_ptr;
1892 len = tpa_info->len;
1893 mapping = tpa_info->mapping;
1898 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1903 if (len <= bp->rx_copybreak) {
1907 cpr->sw_stats->rx.rx_oom_discards += 1;
1918 cpr->sw_stats->rx.rx_oom_discards += 1;
1922 tpa_info->data = new_data;
1923 tpa_info->data_ptr = new_data + bp->rx_offset;
1924 tpa_info->mapping = new_mapping;
1926 skb = napi_build_skb(data, bp->rx_buf_size);
1927 dma_sync_single_for_cpu(&bp->pdev->dev, mapping,
1928 bp->rx_buf_use_size, bp->rx_dir);
1931 page_pool_free_va(rxr->head_pool, data, true);
1933 cpr->sw_stats->rx.rx_oom_discards += 1;
1937 skb_reserve(skb, bp->rx_offset);
1946 cpr->sw_stats->rx.rx_oom_discards += 1;
1951 if (tpa_info->cfa_code_valid)
1952 dev = bnxt_get_pkt_dev(bp, tpa_info->cfa_code);
1953 skb->protocol = eth_type_trans(skb, dev);
1955 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1956 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1958 if (tpa_info->vlan_valid &&
1959 (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1960 __be16 vlan_proto = htons(tpa_info->metadata >>
1962 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1973 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1974 skb->ip_summed = CHECKSUM_UNNECESSARY;
1975 skb->csum_level =
1976 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1992 tpa_info = &rxr->rx_tpa[agg_id];
1993 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1994 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
2002 if (skb->dev != bp->dev) {
2003 /* this packet belongs to a vf-rep */
2007 skb_record_rx_queue(skb, bnapi->index);
2008 napi_gro_receive(&bnapi->napi, skb);
2014 u32 ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp);
2018 if (!bp->ptp_all_rx_tstamp || !ts || !BNXT_ALL_RX_TS_VALID(flags))
2034 __le32 flags2 = rxcmp1->rx_cmp_flags2;
2040 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
2086 * 1 - 1 packet successfully received
2087 * 0 - successful TPA_START, packet not completed yet
2088 * -EBUSY - completion ring does not have all the agg buffers yet
2089 * -ENOMEM - packet aborted due to out of memory
2090 * -EIO - packet aborted due to hw error indicated in BD
2095 struct bnxt_napi *bnapi = cpr->bnapi;
2096 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2097 struct net_device *dev = bp->dev;
2116 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2128 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2131 return -EBUSY;
2137 prod = rxr->rx_prod;
2154 return -EBUSY;
2156 rc = -ENOMEM;
2165 cons = rxcmp->rx_cmp_opaque;
2166 if (unlikely(cons != rxr->rx_next_cons)) {
2170 if (rxr->rx_next_cons != 0xffff)
2171 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
2172 cons, rxr->rx_next_cons);
2178 rx_buf = &rxr->rx_buf_ring[cons];
2179 data = rx_buf->data;
2180 data_ptr = rx_buf->data_ptr;
2183 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
2188 return -EBUSY;
2195 rx_buf->data = NULL;
2196 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
2197 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
2204 rc = -EIO;
2206 bnapi->cp_ring.sw_stats->rx.rx_buf_errors++;
2207 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&
2208 !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
2209 netdev_warn_once(bp->dev, "RX buffer error %x\n",
2217 flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type);
2219 dma_addr = rx_buf->mapping;
2242 agg_bufs = sinfo->nr_frags;
2248 if (len <= bp->rx_copybreak) {
2267 if (rx_buf->data_ptr == data_ptr)
2271 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
2285 rxr->page_pool, &xdp);
2308 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
2313 skb->protocol = eth_type_trans(skb, dev);
2315 if (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX) {
2323 if (dev->features & NETIF_F_RXCSUM) {
2324 skb->ip_summed = CHECKSUM_UNNECESSARY;
2325 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
2328 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
2329 if (dev->features & NETIF_F_RXCSUM)
2330 bnapi->cp_ring.sw_stats->rx.rx_l4_csum_errors++;
2335 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2339 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2344 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
2352 cpr->rx_packets += 1;
2353 cpr->rx_bytes += len;
2356 rxr->rx_prod = NEXT_RX(prod);
2357 rxr->rx_next_cons = RING_RX(bp, NEXT_RX(cons));
2365 cpr->sw_stats->rx.rx_oom_discards += 1;
2366 rc = -ENOMEM;
2386 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2391 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2394 return -EBUSY;
2403 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2409 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
2413 if (rc && rc != -EBUSY)
2414 cpr->sw_stats->rx.rx_netpoll_discards += 1;
2420 struct bnxt_fw_health *fw_health = bp->fw_health;
2421 u32 reg = fw_health->regs[reg_idx];
2428 pci_read_config_dword(bp->pdev, reg_off, &val);
2431 reg_off = fw_health->mapped_regs[reg_idx];
2434 val = readl(bp->bar0 + reg_off);
2437 val = readl(bp->bar1 + reg_off);
2441 val &= fw_health->fw_reset_inprog_reg_mask;
2449 for (i = 0; i < bp->rx_nr_rings; i++) {
2450 u16 grp_idx = bp->rx_ring[i].bnapi->index;
2453 grp_info = &bp->grp_info[grp_idx];
2454 if (grp_info->agg_fw_ring_id == ring_id)
2464 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2)
2465 return link_info->force_link_speed2;
2466 if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4)
2467 return link_info->force_pam4_link_speed;
2468 return link_info->force_link_speed;
2475 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2476 link_info->req_link_speed = link_info->force_link_speed2;
2477 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
2478 switch (link_info->req_link_speed) {
2483 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
2488 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4_112;
2491 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
2495 link_info->req_link_speed = link_info->force_link_speed;
2496 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
2497 if (link_info->force_pam4_link_speed) {
2498 link_info->req_link_speed = link_info->force_pam4_link_speed;
2499 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
2507 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2508 link_info->advertising = link_info->auto_link_speeds2;
2511 link_info->advertising = link_info->auto_link_speeds;
2512 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
2519 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2520 if (link_info->req_link_speed != link_info->force_link_speed2)
2524 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
2525 link_info->req_link_speed != link_info->force_link_speed)
2527 if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
2528 link_info->req_link_speed != link_info->force_pam4_link_speed)
2537 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2538 if (link_info->advertising != link_info->auto_link_speeds2)
2542 if (link_info->advertising != link_info->auto_link_speeds ||
2543 link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
2550 u32 flags = bp->ctx->ctx_arr[type].flags;
2560 u16 trace_type = bnxt_bstore_to_trace[ctxm->type];
2561 struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info;
2566 if (ctxm->instance_bmap && ctxm->instance_bmap > 1)
2569 mem_size = ctxm->max_entries * ctxm->entry_size;
2573 last_pg = (pages - 1) & (MAX_CTX_PAGES - 1);
2574 magic_byte_offset = (rem_bytes ? rem_bytes : BNXT_PAGE_SIZE) - 1;
2577 bs_trace = &bp->bs_trace[trace_type];
2578 bs_trace->ctx_type = ctxm->type;
2579 bs_trace->trace_type = trace_type;
2581 int last_pg_dir = rmem->nr_pages - 1;
2583 rmem_pg_tbl = &ctx_pg[0].ctx_pg_tbl[last_pg_dir]->ring_mem;
2584 bs_trace->magic_byte = rmem_pg_tbl->pg_arr[last_pg];
2586 bs_trace->magic_byte = rmem->pg_arr[last_pg];
2588 bs_trace->magic_byte += magic_byte_offset;
2589 *bs_trace->magic_byte = BNXT_TRACE_BUF_MAGIC_BYTE;
2626 netdev_err(bp->dev, "1PPS: Received invalid signal on pin%lu from the external source. Please fix the signal and reconfigure the pin\n",
2630 netdev_warn(bp->dev, "Pause Storm detected!\n");
2633 netdev_warn(bp->dev, "One or more MMIO doorbells dropped by the device!\n");
2655 netdev_err(bp->dev, "Unknown Thermal threshold type event\n");
2664 netdev_warn(bp->dev, "Chip temperature has gone %s the %s thermal threshold!\n",
2666 netdev_warn(bp->dev, "Temperature (In Celsius), Current: %lu, threshold: %lu\n",
2670 bp->thermal_threshold_type = type;
2671 set_bit(BNXT_THERMAL_THRESHOLD_SP_EVENT, &bp->sp_event);
2677 netdev_warn(bp->dev, "Speed change not supported with dual rate transceivers on this board\n");
2680 netdev_err(bp->dev, "FW reported unknown error type %u\n",
2712 u16 event_id = le16_to_cpu(cmpl->event_id);
2713 u32 data1 = le32_to_cpu(cmpl->event_data1);
2714 u32 data2 = le32_to_cpu(cmpl->event_data2);
2716 netdev_dbg(bp->dev, "hwrm event 0x%x {0x%x, 0x%x}\n",
2722 struct bnxt_link_info *link_info = &bp->link_info;
2728 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
2734 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
2737 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
2742 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2745 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2748 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2756 if (bp->pf.port_id != port_id)
2759 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2765 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2770 if (!bp->fw_health)
2773 bp->fw_reset_timestamp = jiffies;
2774 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2775 if (!bp->fw_reset_min_dsecs)
2776 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2777 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2778 if (!bp->fw_reset_max_dsecs)
2779 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2781 set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state);
2784 bp->fw_health->fatalities++;
2785 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2788 type_str = "Non-fatal";
2789 bp->fw_health->survivals++;
2790 set_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
2792 netif_warn(bp, hw, bp->dev,
2795 bp->fw_reset_min_dsecs * 100,
2796 bp->fw_reset_max_dsecs * 100);
2797 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2801 struct bnxt_fw_health *fw_health = bp->fw_health;
2809 fw_health->enabled = false;
2810 netif_info(bp, drv, bp->dev, "Driver recovery watchdog is disabled\n");
2813 fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2814 fw_health->tmr_multiplier =
2815 DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2816 bp->current_interval * 10);
2817 fw_health->tmr_counter = fw_health->tmr_multiplier;
2818 if (!fw_health->enabled)
2819 fw_health->last_fw_heartbeat =
2821 fw_health->last_fw_reset_cnt =
2826 netif_info(bp, drv, bp->dev,
2828 fw_health->primary ? "primary" : "backup", status,
2829 status_desc, fw_health->last_fw_reset_cnt);
2830 if (!fw_health->enabled) {
2835 fw_health->enabled = true;
2840 netif_notice(bp, hw, bp->dev,
2848 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
2851 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2858 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2862 rxr = bp->bnapi[grp_idx]->rx_ring;
2867 struct bnxt_fw_health *fw_health = bp->fw_health;
2869 netif_notice(bp, hw, bp->dev,
2873 fw_health->echo_req_data1 = data1;
2874 fw_health->echo_req_data2 = data2;
2875 set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event);
2893 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2902 BNXT_PHC_BITS) | ptp->current_time);
2903 write_seqlock_irqsave(&ptp->ptp_lock, flags);
2905 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
2912 u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff;
2921 bnxt_bs_trace_check_wrap(&bp->bs_trace[type], offset);
2942 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2947 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2949 if ((vf_id < bp->pf.first_vf_id) ||
2950 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2951 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2953 return -EINVAL;
2956 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2974 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
2976 return vnic->fw_vnic_id != INVALID_HW_RING_ID && vnic->mru > 0;
2982 struct bnxt *bp = bnapi->bp;
2983 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2984 u32 cons = RING_CMP(cpr->cp_raw_cons);
2986 cpr->event_ctr++;
2987 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2988 napi_schedule(&bnapi->napi);
2994 u32 raw_cons = cpr->cp_raw_cons;
2998 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3006 struct bnxt_napi *bnapi = cpr->bnapi;
3007 u32 raw_cons = cpr->cp_raw_cons;
3014 cpr->has_more_work = 0;
3015 cpr->had_work_done = 1;
3021 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3033 u32 opaque = txcmp->tx_cmp_opaque;
3037 txr = bnapi->tx_ring[TX_OPAQUE_RING(opaque)];
3040 txr->tx_hw_cons = TX_CMP_SQ_CONS_IDX(txcmp);
3042 txr->tx_hw_cons = TX_OPAQUE_PROD(bp, opaque);
3043 tx_freed = (txr->tx_hw_cons - txr->tx_cons) &
3044 bp->tx_ring_mask;
3046 if (unlikely(tx_freed >= bp->tx_wake_thresh)) {
3050 cpr->has_more_work = 1;
3066 /* Increment rx_pkts when rc is -ENOMEM to count towards
3071 else if (rc == -ENOMEM && budget)
3073 else if (rc == -EBUSY) /* partial completion */
3083 cpr->has_more_work = 1;
3094 struct bnxt_tx_ring_info *txr = bnapi->tx_ring[0];
3095 u16 prod = txr->tx_prod;
3100 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
3104 cpr->cp_raw_cons = raw_cons;
3105 bnapi->events |= event;
3112 if ((bnapi->events & BNXT_TX_CMP_EVENT) && !bnapi->tx_fault)
3113 bnapi->tx_int(bp, bnapi, budget);
3115 if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
3116 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
3118 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
3119 bnapi->events &= ~BNXT_RX_EVENT;
3121 if (bnapi->events & BNXT_AGG_EVENT) {
3122 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
3124 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
3125 bnapi->events &= ~BNXT_AGG_EVENT;
3132 struct bnxt_napi *bnapi = cpr->bnapi;
3141 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3150 struct bnxt *bp = bnapi->bp;
3151 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3152 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
3156 u32 raw_cons = cpr->cp_raw_cons;
3165 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3178 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3184 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
3188 if (likely(rc == -EIO) && budget)
3190 else if (rc == -EBUSY) /* partial completion */
3198 netdev_err(bp->dev,
3207 cpr->cp_raw_cons = raw_cons;
3208 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
3209 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
3212 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
3218 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
3226 struct bnxt *bp = bnapi->bp;
3227 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3230 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
3235 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
3239 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
3245 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
3249 if ((bp->flags & BNXT_FLAG_DIM) && bnxt_vnic_is_active(bp)) {
3252 dim_update_sample(cpr->event_ctr,
3253 cpr->rx_packets,
3254 cpr->rx_bytes,
3256 net_dim(&cpr->dim, &dim_sample);
3263 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3266 for (i = 0; i < cpr->cp_ring_count; i++) {
3267 struct bnxt_cp_ring_info *cpr2 = &cpr->cp_ring_arr[i];
3269 if (cpr2->had_nqe_notify) {
3271 budget - work_done);
3272 cpr->has_more_work |= cpr2->has_more_work;
3281 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3284 for (i = 0; i < cpr->cp_ring_count; i++) {
3285 struct bnxt_cp_ring_info *cpr2 = &cpr->cp_ring_arr[i];
3288 if (cpr2->had_work_done) {
3292 cpr2->had_nqe_notify = 0;
3293 tgl = cpr2->toggle;
3295 db = &cpr2->cp_db;
3297 db->db_key64 | dbr_type | DB_TOGGLE(tgl) |
3298 DB_RING_IDX(db, cpr2->cp_raw_cons),
3299 db->doorbell);
3300 cpr2->had_work_done = 0;
3309 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3311 u32 raw_cons = cpr->cp_raw_cons;
3312 struct bnxt *bp = bnapi->bp;
3317 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
3321 if (cpr->has_more_work) {
3322 cpr->has_more_work = 0;
3329 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3332 if (cpr->has_more_work)
3337 cpr->cp_raw_cons = raw_cons;
3339 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
3340 cpr->cp_raw_cons);
3349 type = le16_to_cpu(nqcmp->type);
3351 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
3361 cpr2 = &cpr->cp_ring_arr[idx];
3362 cpr2->had_nqe_notify = 1;
3363 cpr2->toggle = NQE_CN_TOGGLE(type);
3365 budget - work_done);
3366 cpr->has_more_work |= cpr2->has_more_work;
3373 if (raw_cons != cpr->cp_raw_cons) {
3374 cpr->cp_raw_cons = raw_cons;
3375 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
3378 cpr_rx = &cpr->cp_ring_arr[0];
3379 if (cpr_rx->cp_ring_type == BNXT_NQ_HDL_TYPE_RX &&
3380 (bp->flags & BNXT_FLAG_DIM) && bnxt_vnic_is_active(bp)) {
3383 dim_update_sample(cpr->event_ctr,
3384 cpr_rx->rx_packets,
3385 cpr_rx->rx_bytes,
3387 net_dim(&cpr->dim, &dim_sample);
3396 struct pci_dev *pdev = bp->pdev;
3398 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
3401 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[i];
3405 if (idx < bp->tx_nr_rings_xdp &&
3406 tx_buf->action == XDP_REDIRECT) {
3407 dma_unmap_single(&pdev->dev,
3411 xdp_return_frame(tx_buf->xdpf);
3412 tx_buf->action = 0;
3413 tx_buf->xdpf = NULL;
3418 skb = tx_buf->skb;
3424 tx_buf->skb = NULL;
3426 if (tx_buf->is_push) {
3432 dma_unmap_single(&pdev->dev,
3437 last = tx_buf->nr_frags;
3440 int ring_idx = i & bp->tx_ring_mask;
3441 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
3443 tx_buf = &txr->tx_buf_ring[ring_idx];
3444 netmem_dma_unmap_page_attrs(&pdev->dev,
3452 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, idx));
3459 if (!bp->tx_ring)
3462 for (i = 0; i < bp->tx_nr_rings; i++) {
3463 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3465 if (!txr->tx_buf_ring)
3471 if (bp->ptp_cfg && !(bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP))
3472 bnxt_ptp_free_txts_skbs(bp->ptp_cfg);
3479 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
3482 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
3483 void *data = rx_buf->data;
3488 rx_buf->data = NULL;
3490 page_pool_recycle_direct(rxr->page_pool, data);
3492 page_pool_free_va(rxr->head_pool, data, true);
3500 max_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
3503 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
3504 netmem_ref netmem = rx_agg_buf->netmem;
3509 rx_agg_buf->netmem = 0;
3510 __clear_bit(i, rxr->rx_agg_bmap);
3512 page_pool_recycle_direct_netmem(rxr->page_pool, netmem);
3521 for (i = 0; i < bp->max_tpa; i++) {
3522 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
3523 u8 *data = tpa_info->data;
3528 tpa_info->data = NULL;
3529 page_pool_free_va(rxr->head_pool, data, false);
3538 if (!rxr->rx_tpa)
3544 if (!rxr->rx_buf_ring)
3550 if (!rxr->rx_agg_ring)
3556 map = rxr->rx_tpa_idx_map;
3558 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
3565 if (!bp->rx_ring)
3568 for (i = 0; i < bp->rx_nr_rings; i++)
3569 bnxt_free_one_rx_ring_skbs(bp, &bp->rx_ring[i]);
3580 u8 init_val = ctxm->init_value;
3581 u16 offset = ctxm->init_offset;
3591 for (i = 0; i < len; i += ctxm->entry_size)
3602 head_page = head / rmem->page_size;
3603 source_offset = head % rmem->page_size;
3604 total_len = (tail - head) & MAX_CTX_BYTES_MASK;
3608 max_bytes = (rmem->nr_pages - start_idx) * rmem->page_size -
3614 len = min((size_t)(rmem->page_size - source_offset), rem_len);
3616 memcpy(buf + offset, rmem->pg_arr[i] + source_offset,
3619 rem_len -= len;
3626 struct pci_dev *pdev = bp->pdev;
3629 if (!rmem->pg_arr)
3632 for (i = 0; i < rmem->nr_pages; i++) {
3633 if (!rmem->pg_arr[i])
3636 dma_free_coherent(&pdev->dev, rmem->page_size,
3637 rmem->pg_arr[i], rmem->dma_arr[i]);
3639 rmem->pg_arr[i] = NULL;
3642 if (rmem->pg_tbl) {
3643 size_t pg_tbl_size = rmem->nr_pages * 8;
3645 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3646 pg_tbl_size = rmem->page_size;
3647 dma_free_coherent(&pdev->dev, pg_tbl_size,
3648 rmem->pg_tbl, rmem->pg_tbl_map);
3649 rmem->pg_tbl = NULL;
3651 if (rmem->vmem_size && *rmem->vmem) {
3652 vfree(*rmem->vmem);
3653 *rmem->vmem = NULL;
3659 struct pci_dev *pdev = bp->pdev;
3663 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
3665 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
3666 size_t pg_tbl_size = rmem->nr_pages * 8;
3668 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3669 pg_tbl_size = rmem->page_size;
3670 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
3671 &rmem->pg_tbl_map,
3673 if (!rmem->pg_tbl)
3674 return -ENOMEM;
3677 for (i = 0; i < rmem->nr_pages; i++) {
3680 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
3681 rmem->page_size,
3682 &rmem->dma_arr[i],
3684 if (!rmem->pg_arr[i])
3685 return -ENOMEM;
3687 if (rmem->ctx_mem)
3688 bnxt_init_ctx_mem(rmem->ctx_mem, rmem->pg_arr[i],
3689 rmem->page_size);
3690 if (rmem->nr_pages > 1 || rmem->depth > 0) {
3691 if (i == rmem->nr_pages - 2 &&
3692 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3694 else if (i == rmem->nr_pages - 1 &&
3695 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3697 rmem->pg_tbl[i] =
3698 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
3702 if (rmem->vmem_size) {
3703 *rmem->vmem = vzalloc(rmem->vmem_size);
3704 if (!(*rmem->vmem))
3705 return -ENOMEM;
3715 kfree(rxr->rx_tpa_idx_map);
3716 rxr->rx_tpa_idx_map = NULL;
3717 if (rxr->rx_tpa) {
3718 for (i = 0; i < bp->max_tpa; i++) {
3719 kfree(rxr->rx_tpa[i].agg_arr);
3720 rxr->rx_tpa[i].agg_arr = NULL;
3723 kfree(rxr->rx_tpa);
3724 rxr->rx_tpa = NULL;
3731 for (i = 0; i < bp->rx_nr_rings; i++) {
3732 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3744 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
3746 if (!rxr->rx_tpa)
3747 return -ENOMEM;
3749 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
3751 for (i = 0; i < bp->max_tpa; i++) {
3754 return -ENOMEM;
3755 rxr->rx_tpa[i].agg_arr = agg;
3757 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
3759 if (!rxr->rx_tpa_idx_map)
3760 return -ENOMEM;
3769 bp->max_tpa = MAX_TPA;
3770 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
3771 if (!bp->max_tpa_v2)
3773 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
3776 for (i = 0; i < bp->rx_nr_rings; i++) {
3777 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3790 if (!bp->rx_ring)
3794 for (i = 0; i < bp->rx_nr_rings; i++) {
3795 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3798 if (rxr->xdp_prog)
3799 bpf_prog_put(rxr->xdp_prog);
3801 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
3802 xdp_rxq_info_unreg(&rxr->xdp_rxq);
3804 page_pool_destroy(rxr->page_pool);
3805 page_pool_destroy(rxr->head_pool);
3806 rxr->page_pool = rxr->head_pool = NULL;
3808 kfree(rxr->rx_agg_bmap);
3809 rxr->rx_agg_bmap = NULL;
3811 ring = &rxr->rx_ring_struct;
3812 bnxt_free_ring(bp, &ring->ring_mem);
3814 ring = &rxr->rx_agg_ring_struct;
3815 bnxt_free_ring(bp, &ring->ring_mem);
3828 pp.pool_size = bp->rx_agg_ring_size / agg_size_fac;
3830 pp.pool_size += bp->rx_ring_size / rx_size_fac;
3832 pp.netdev = bp->dev;
3833 pp.dev = &bp->pdev->dev;
3834 pp.dma_dir = bp->rx_dir;
3838 pp.queue_idx = rxr->bnapi->index;
3843 rxr->page_pool = pool;
3845 rxr->need_head_pool = page_pool_is_unreadable(pool);
3847 pp.pool_size = min(bp->rx_ring_size / rx_size_fac, 1024);
3855 rxr->head_pool = pool;
3860 page_pool_destroy(rxr->page_pool);
3861 rxr->page_pool = NULL;
3867 page_pool_enable_direct_recycling(rxr->head_pool, &rxr->bnapi->napi);
3868 page_pool_enable_direct_recycling(rxr->page_pool, &rxr->bnapi->napi);
3875 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
3876 mem_size = rxr->rx_agg_bmap_size / 8;
3877 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
3878 if (!rxr->rx_agg_bmap)
3879 return -ENOMEM;
3886 int numa_node = dev_to_node(&bp->pdev->dev);
3889 if (!bp->rx_ring)
3890 return -ENOMEM;
3892 if (bp->flags & BNXT_FLAG_AGG_RINGS)
3895 for (i = 0; i < bp->rx_nr_rings; i++) {
3896 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3900 ring = &rxr->rx_ring_struct;
3904 netdev_dbg(bp->dev, "Allocating page pool for rx_ring[%d] on numa_node: %d\n",
3911 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
3915 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
3917 rxr->page_pool);
3919 xdp_rxq_info_unreg(&rxr->xdp_rxq);
3923 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3927 ring->grp_idx = i;
3929 ring = &rxr->rx_agg_ring_struct;
3930 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3934 ring->grp_idx = i;
3940 if (bp->flags & BNXT_FLAG_TPA)
3948 struct pci_dev *pdev = bp->pdev;
3950 if (!bp->tx_ring)
3953 for (i = 0; i < bp->tx_nr_rings; i++) {
3954 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3957 if (txr->tx_push) {
3958 dma_free_coherent(&pdev->dev, bp->tx_push_size,
3959 txr->tx_push, txr->tx_push_mapping);
3960 txr->tx_push = NULL;
3963 ring = &txr->tx_ring_struct;
3965 bnxt_free_ring(bp, &ring->ring_mem);
3970 ((tc) * (bp)->tx_nr_rings_per_tc)
3973 ((tx) % (bp)->tx_nr_rings_per_tc)
3976 ((tx) / (bp)->tx_nr_rings_per_tc)
3981 struct pci_dev *pdev = bp->pdev;
3983 bp->tx_push_size = 0;
3984 if (bp->tx_push_thresh) {
3988 bp->tx_push_thresh);
3992 bp->tx_push_thresh = 0;
3995 bp->tx_push_size = push_size;
3998 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3999 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4003 ring = &txr->tx_ring_struct;
4005 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
4009 ring->grp_idx = txr->bnapi->index;
4010 if (bp->tx_push_size) {
4013 /* One pre-allocated DMA buffer to backup
4016 txr->tx_push = dma_alloc_coherent(&pdev->dev,
4017 bp->tx_push_size,
4018 &txr->tx_push_mapping,
4021 if (!txr->tx_push)
4022 return -ENOMEM;
4024 mapping = txr->tx_push_mapping +
4026 txr->data_mapping = cpu_to_le64(mapping);
4028 qidx = bp->tc_to_qidx[j];
4029 ring->queue_id = bp->q_info[qidx].queue_id;
4030 spin_lock_init(&txr->xdp_tx_lock);
4031 if (i < bp->tx_nr_rings_xdp)
4033 if (BNXT_RING_TO_TC_OFF(bp, i) == (bp->tx_nr_rings_per_tc - 1))
4041 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4043 kfree(cpr->cp_desc_ring);
4044 cpr->cp_desc_ring = NULL;
4045 ring->ring_mem.pg_arr = NULL;
4046 kfree(cpr->cp_desc_mapping);
4047 cpr->cp_desc_mapping = NULL;
4048 ring->ring_mem.dma_arr = NULL;
4053 cpr->cp_desc_ring = kcalloc(n, sizeof(*cpr->cp_desc_ring), GFP_KERNEL);
4054 if (!cpr->cp_desc_ring)
4055 return -ENOMEM;
4056 cpr->cp_desc_mapping = kcalloc(n, sizeof(*cpr->cp_desc_mapping),
4058 if (!cpr->cp_desc_mapping)
4059 return -ENOMEM;
4067 if (!bp->bnapi)
4069 for (i = 0; i < bp->cp_nr_rings; i++) {
4070 struct bnxt_napi *bnapi = bp->bnapi[i];
4074 bnxt_free_cp_arrays(&bnapi->cp_ring);
4080 int i, n = bp->cp_nr_pages;
4082 for (i = 0; i < bp->cp_nr_rings; i++) {
4083 struct bnxt_napi *bnapi = bp->bnapi[i];
4088 rc = bnxt_alloc_cp_arrays(&bnapi->cp_ring, n);
4099 if (!bp->bnapi)
4102 for (i = 0; i < bp->cp_nr_rings; i++) {
4103 struct bnxt_napi *bnapi = bp->bnapi[i];
4111 cpr = &bnapi->cp_ring;
4112 ring = &cpr->cp_ring_struct;
4114 bnxt_free_ring(bp, &ring->ring_mem);
4116 if (!cpr->cp_ring_arr)
4119 for (j = 0; j < cpr->cp_ring_count; j++) {
4120 struct bnxt_cp_ring_info *cpr2 = &cpr->cp_ring_arr[j];
4122 ring = &cpr2->cp_ring_struct;
4123 bnxt_free_ring(bp, &ring->ring_mem);
4126 kfree(cpr->cp_ring_arr);
4127 cpr->cp_ring_arr = NULL;
4128 cpr->cp_ring_count = 0;
4139 rc = bnxt_alloc_cp_arrays(cpr, bp->cp_nr_pages);
4142 return -ENOMEM;
4144 ring = &cpr->cp_ring_struct;
4145 rmem = &ring->ring_mem;
4146 rmem->nr_pages = bp->cp_nr_pages;
4147 rmem->page_size = HW_CMPD_RING_SIZE;
4148 rmem->pg_arr = (void **)cpr->cp_desc_ring;
4149 rmem->dma_arr = cpr->cp_desc_mapping;
4150 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
4161 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
4163 int tcs = bp->num_tc;
4168 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4169 struct bnxt_napi *bnapi = bp->bnapi[i];
4178 cpr = &bnapi->cp_ring;
4179 cpr->bnapi = bnapi;
4180 ring = &cpr->cp_ring_struct;
4182 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
4186 ring->map_idx = ulp_msix + i;
4188 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
4191 if (i < bp->rx_nr_rings) {
4195 if (i < bp->tx_nr_rings_xdp) {
4198 } else if ((sh && i < bp->tx_nr_rings) ||
4199 (!sh && i >= bp->rx_nr_rings)) {
4204 cpr->cp_ring_arr = kcalloc(cp_count, sizeof(*cpr),
4206 if (!cpr->cp_ring_arr)
4207 return -ENOMEM;
4208 cpr->cp_ring_count = cp_count;
4211 cpr2 = &cpr->cp_ring_arr[k];
4215 cpr2->bnapi = bnapi;
4216 cpr2->sw_stats = cpr->sw_stats;
4217 cpr2->cp_idx = k;
4219 bp->rx_ring[i].rx_cpr = cpr2;
4220 cpr2->cp_ring_type = BNXT_NQ_HDL_TYPE_RX;
4222 int n, tc = k - rx;
4225 bp->tx_ring[n].tx_cpr = cpr2;
4226 cpr2->cp_ring_type = BNXT_NQ_HDL_TYPE_TX;
4241 ring = &rxr->rx_ring_struct;
4242 rmem = &ring->ring_mem;
4243 rmem->nr_pages = bp->rx_nr_pages;
4244 rmem->page_size = HW_RXBD_RING_SIZE;
4245 rmem->pg_arr = (void **)rxr->rx_desc_ring;
4246 rmem->dma_arr = rxr->rx_desc_mapping;
4247 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
4248 rmem->vmem = (void **)&rxr->rx_buf_ring;
4250 ring = &rxr->rx_agg_ring_struct;
4251 rmem = &ring->ring_mem;
4252 rmem->nr_pages = bp->rx_agg_nr_pages;
4253 rmem->page_size = HW_RXBD_RING_SIZE;
4254 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
4255 rmem->dma_arr = rxr->rx_agg_desc_mapping;
4256 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
4257 rmem->vmem = (void **)&rxr->rx_agg_ring;
4267 rxr->page_pool->p.napi = NULL;
4268 rxr->page_pool = NULL;
4269 rxr->head_pool->p.napi = NULL;
4270 rxr->head_pool = NULL;
4271 memset(&rxr->xdp_rxq, 0, sizeof(struct xdp_rxq_info));
4273 ring = &rxr->rx_ring_struct;
4274 rmem = &ring->ring_mem;
4275 rmem->pg_tbl = NULL;
4276 rmem->pg_tbl_map = 0;
4277 for (i = 0; i < rmem->nr_pages; i++) {
4278 rmem->pg_arr[i] = NULL;
4279 rmem->dma_arr[i] = 0;
4281 *rmem->vmem = NULL;
4283 ring = &rxr->rx_agg_ring_struct;
4284 rmem = &ring->ring_mem;
4285 rmem->pg_tbl = NULL;
4286 rmem->pg_tbl_map = 0;
4287 for (i = 0; i < rmem->nr_pages; i++) {
4288 rmem->pg_arr[i] = NULL;
4289 rmem->dma_arr[i] = 0;
4291 *rmem->vmem = NULL;
4298 for (i = 0; i < bp->cp_nr_rings; i++) {
4299 struct bnxt_napi *bnapi = bp->bnapi[i];
4309 cpr = &bnapi->cp_ring;
4310 ring = &cpr->cp_ring_struct;
4311 rmem = &ring->ring_mem;
4312 rmem->nr_pages = bp->cp_nr_pages;
4313 rmem->page_size = HW_CMPD_RING_SIZE;
4314 rmem->pg_arr = (void **)cpr->cp_desc_ring;
4315 rmem->dma_arr = cpr->cp_desc_mapping;
4316 rmem->vmem_size = 0;
4318 rxr = bnapi->rx_ring;
4322 ring = &rxr->rx_ring_struct;
4323 rmem = &ring->ring_mem;
4324 rmem->nr_pages = bp->rx_nr_pages;
4325 rmem->page_size = HW_RXBD_RING_SIZE;
4326 rmem->pg_arr = (void **)rxr->rx_desc_ring;
4327 rmem->dma_arr = rxr->rx_desc_mapping;
4328 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
4329 rmem->vmem = (void **)&rxr->rx_buf_ring;
4331 ring = &rxr->rx_agg_ring_struct;
4332 rmem = &ring->ring_mem;
4333 rmem->nr_pages = bp->rx_agg_nr_pages;
4334 rmem->page_size = HW_RXBD_RING_SIZE;
4335 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
4336 rmem->dma_arr = rxr->rx_agg_desc_mapping;
4337 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
4338 rmem->vmem = (void **)&rxr->rx_agg_ring;
4342 ring = &txr->tx_ring_struct;
4343 rmem = &ring->ring_mem;
4344 rmem->nr_pages = bp->tx_nr_pages;
4345 rmem->page_size = HW_TXBD_RING_SIZE;
4346 rmem->pg_arr = (void **)txr->tx_desc_ring;
4347 rmem->dma_arr = txr->tx_desc_mapping;
4348 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
4349 rmem->vmem = (void **)&txr->tx_buf_ring;
4360 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
4361 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
4370 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
4371 rxbd->rx_bd_opaque = prod;
4383 prod = rxr->rx_prod;
4384 for (i = 0; i < bp->rx_ring_size; i++) {
4386 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
4387 ring_nr, i, bp->rx_ring_size);
4392 rxr->rx_prod = prod;
4402 prod = rxr->rx_agg_prod;
4403 for (i = 0; i < bp->rx_agg_ring_size; i++) {
4405 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d pages only\n",
4406 ring_nr, i, bp->rx_agg_ring_size);
4411 rxr->rx_agg_prod = prod;
4421 for (i = 0; i < bp->max_tpa; i++) {
4425 return -ENOMEM;
4427 rxr->rx_tpa[i].data = data;
4428 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
4429 rxr->rx_tpa[i].mapping = mapping;
4437 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
4442 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
4447 if (rxr->rx_tpa) {
4461 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
4467 ring = &rxr->rx_ring_struct;
4469 ring->fw_ring_id = INVALID_HW_RING_ID;
4478 ring = &rxr->rx_agg_ring_struct;
4479 ring->fw_ring_id = INVALID_HW_RING_ID;
4480 if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
4492 rxr = &bp->rx_ring[ring_nr];
4495 netif_queue_set_napi(bp->dev, ring_nr, NETDEV_QUEUE_TYPE_RX,
4496 &rxr->bnapi->napi);
4498 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
4499 bpf_prog_add(bp->xdp_prog, 1);
4500 rxr->xdp_prog = bp->xdp_prog;
4512 for (i = 0; i < bp->cp_nr_rings; i++) {
4513 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
4514 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4516 ring->fw_ring_id = INVALID_HW_RING_ID;
4517 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
4518 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
4519 if (!cpr->cp_ring_arr)
4521 for (j = 0; j < cpr->cp_ring_count; j++) {
4522 struct bnxt_cp_ring_info *cpr2 = &cpr->cp_ring_arr[j];
4524 ring = &cpr2->cp_ring_struct;
4525 ring->fw_ring_id = INVALID_HW_RING_ID;
4526 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
4527 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
4537 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
4538 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
4540 bp->rx_offset = BNXT_RX_OFFSET;
4541 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
4544 for (i = 0; i < bp->rx_nr_rings; i++) {
4557 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
4560 for (i = 0; i < bp->tx_nr_rings; i++) {
4561 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4562 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4564 ring->fw_ring_id = INVALID_HW_RING_ID;
4566 if (i >= bp->tx_nr_rings_xdp)
4567 netif_queue_set_napi(bp->dev, i - bp->tx_nr_rings_xdp,
4569 &txr->bnapi->napi);
4577 kfree(bp->grp_info);
4578 bp->grp_info = NULL;
4586 bp->grp_info = kcalloc(bp->cp_nr_rings,
4589 if (!bp->grp_info)
4590 return -ENOMEM;
4592 for (i = 0; i < bp->cp_nr_rings; i++) {
4594 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
4595 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4596 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
4597 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
4598 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4605 kfree(bp->vnic_info);
4606 bp->vnic_info = NULL;
4607 bp->nr_vnics = 0;
4615 if (bp->flags & BNXT_FLAG_RFS) {
4618 else if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
4619 num_vnics += bp->rx_nr_rings;
4626 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
4628 if (!bp->vnic_info)
4629 return -ENOMEM;
4631 bp->nr_vnics = num_vnics;
4637 struct bnxt_vnic_info *vnic0 = &bp->vnic_info[BNXT_VNIC_DEFAULT];
4640 for (i = 0; i < bp->nr_vnics; i++) {
4641 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4644 vnic->fw_vnic_id = INVALID_HW_RING_ID;
4645 vnic->vnic_id = i;
4647 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
4649 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
4651 if (bp->vnic_info[i].rss_hash_key) {
4653 u8 *key = (void *)vnic->rss_hash_key;
4656 if (!bp->rss_hash_key_valid &&
4657 !bp->rss_hash_key_updated) {
4658 get_random_bytes(bp->rss_hash_key,
4660 bp->rss_hash_key_updated = true;
4663 memcpy(vnic->rss_hash_key, bp->rss_hash_key,
4666 if (!bp->rss_hash_key_updated)
4669 bp->rss_hash_key_updated = false;
4670 bp->rss_hash_key_valid = true;
4672 bp->toeplitz_prefix = 0;
4674 bp->toeplitz_prefix <<= 8;
4675 bp->toeplitz_prefix |= key[k];
4678 memcpy(vnic->rss_hash_key, vnic0->rss_hash_key,
4696 while (pages & (pages - 1))
4704 bp->flags &= ~BNXT_FLAG_TPA;
4705 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
4707 if (bp->dev->features & NETIF_F_LRO)
4708 bp->flags |= BNXT_FLAG_LRO;
4709 else if (bp->dev->features & NETIF_F_GRO_HW)
4710 bp->flags |= BNXT_FLAG_GRO;
4717 bp->rx_copybreak = BNXT_DEFAULT_RX_COPYBREAK;
4719 rx_size = SZ_1K -
4720 NET_SKB_PAD - SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
4721 bp->dev->cfg->hds_thresh = max(BNXT_DEFAULT_RX_COPYBREAK, rx_size);
4724 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
4733 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
4738 ring_size = bp->rx_ring_size;
4739 bp->rx_agg_ring_size = 0;
4740 bp->rx_agg_nr_pages = 0;
4742 if (bp->flags & BNXT_FLAG_TPA || bp->flags & BNXT_FLAG_HDS)
4745 bp->flags &= ~BNXT_FLAG_JUMBO;
4746 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
4749 bp->flags |= BNXT_FLAG_JUMBO;
4750 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4757 netdev_warn(bp->dev, "RX ring size reduced from %d to %d because the jumbo ring is now enabled\n",
4758 bp->rx_ring_size, ring_size);
4759 bp->rx_ring_size = ring_size;
4763 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
4765 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
4768 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
4769 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
4770 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
4773 bp->rx_agg_ring_size = agg_ring_size;
4774 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
4778 rx_size = PAGE_SIZE -
4779 ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) -
4783 bp->rx_copybreak,
4784 bp->dev->cfg_pending->hds_thresh);
4791 bp->rx_buf_use_size = rx_size;
4792 bp->rx_buf_size = rx_space;
4794 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
4795 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
4797 ring_size = bp->tx_ring_size;
4798 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
4799 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
4801 max_rx_cmpl = bp->rx_ring_size;
4806 if (bp->flags & BNXT_FLAG_TPA)
4807 max_rx_cmpl += bp->max_tpa;
4808 /* RX and TPA completions are 32-byte, all others are 16-byte */
4809 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
4810 bp->cp_ring_size = ring_size;
4812 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
4813 if (bp->cp_nr_pages > MAX_CP_PAGES) {
4814 bp->cp_nr_pages = MAX_CP_PAGES;
4815 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
4816 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
4817 ring_size, bp->cp_ring_size);
4819 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
4820 bp->cp_ring_mask = bp->cp_bit - 1;
4828 struct net_device *dev = bp->dev;
4831 bp->flags &= ~(BNXT_FLAG_AGG_RINGS | BNXT_FLAG_NO_AGG_RINGS);
4832 bp->flags |= BNXT_FLAG_RX_PAGE_MODE;
4834 if (bp->xdp_prog->aux->xdp_has_frags)
4835 dev->max_mtu = min_t(u16, bp->max_mtu, BNXT_MAX_MTU);
4837 dev->max_mtu =
4838 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
4839 if (dev->mtu > BNXT_MAX_PAGE_MODE_MTU) {
4840 bp->flags |= BNXT_FLAG_JUMBO;
4841 bp->rx_skb_func = bnxt_rx_multi_page_skb;
4843 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4844 bp->rx_skb_func = bnxt_rx_page_skb;
4846 bp->rx_dir = DMA_BIDIRECTIONAL;
4848 dev->max_mtu = bp->max_mtu;
4849 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
4850 bp->rx_dir = DMA_FROM_DEVICE;
4851 bp->rx_skb_func = bnxt_rx_skb;
4864 bp->flags &= ~BNXT_FLAG_NO_AGG_RINGS;
4865 bp->dev->hw_features |= NETIF_F_LRO;
4870 netdev_update_features(bp->dev);
4877 struct pci_dev *pdev = bp->pdev;
4879 if (!bp->vnic_info)
4882 for (i = 0; i < bp->nr_vnics; i++) {
4883 vnic = &bp->vnic_info[i];
4885 kfree(vnic->fw_grp_ids);
4886 vnic->fw_grp_ids = NULL;
4888 kfree(vnic->uc_list);
4889 vnic->uc_list = NULL;
4891 if (vnic->mc_list) {
4892 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
4893 vnic->mc_list, vnic->mc_list_mapping);
4894 vnic->mc_list = NULL;
4897 if (vnic->rss_table) {
4898 dma_free_coherent(&pdev->dev, vnic->rss_table_size,
4899 vnic->rss_table,
4900 vnic->rss_table_dma_addr);
4901 vnic->rss_table = NULL;
4904 vnic->rss_hash_key = NULL;
4905 vnic->flags = 0;
4913 struct pci_dev *pdev = bp->pdev;
4916 for (i = 0; i < bp->nr_vnics; i++) {
4917 vnic = &bp->vnic_info[i];
4919 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
4920 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
4923 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
4924 if (!vnic->uc_list) {
4925 rc = -ENOMEM;
4931 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
4932 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
4933 vnic->mc_list =
4934 dma_alloc_coherent(&pdev->dev,
4935 vnic->mc_list_size,
4936 &vnic->mc_list_mapping,
4938 if (!vnic->mc_list) {
4939 rc = -ENOMEM;
4944 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
4947 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4948 max_rings = bp->rx_nr_rings;
4952 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
4953 if (!vnic->fw_grp_ids) {
4954 rc = -ENOMEM;
4958 if ((bp->rss_cap & BNXT_RSS_CAP_NEW_RSS_CAP) &&
4959 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
4964 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
4967 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
4968 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
4969 vnic->rss_table_size,
4970 &vnic->rss_table_dma_addr,
4972 if (!vnic->rss_table) {
4973 rc = -ENOMEM;
4977 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
4978 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
4990 dma_pool_destroy(bp->hwrm_dma_pool);
4991 bp->hwrm_dma_pool = NULL;
4994 hlist_for_each_entry_rcu(token, &bp->hwrm_pending_list, node)
4995 WRITE_ONCE(token->state, BNXT_HWRM_CANCELLED);
5001 bp->hwrm_dma_pool = dma_pool_create("bnxt_hwrm", &bp->pdev->dev,
5004 if (!bp->hwrm_dma_pool)
5005 return -ENOMEM;
5007 INIT_HLIST_HEAD(&bp->hwrm_pending_list);
5014 kfree(stats->hw_masks);
5015 stats->hw_masks = NULL;
5016 kfree(stats->sw_stats);
5017 stats->sw_stats = NULL;
5018 if (stats->hw_stats) {
5019 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
5020 stats->hw_stats_map);
5021 stats->hw_stats = NULL;
5028 stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
5029 &stats->hw_stats_map, GFP_KERNEL);
5030 if (!stats->hw_stats)
5031 return -ENOMEM;
5033 stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
5034 if (!stats->sw_stats)
5038 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
5039 if (!stats->hw_masks)
5046 return -ENOMEM;
5073 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
5074 !(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
5075 return -EOPNOTSUPP;
5081 req->fid = cpu_to_le16(0xffff);
5082 req->flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
5087 hw_masks = &resp->rx_ucast_pkts;
5088 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
5099 struct bnxt_napi *bnapi = bp->bnapi[0];
5108 cpr = &bnapi->cp_ring;
5109 stats = &cpr->stats;
5112 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
5113 mask = (1ULL << 48) - 1;
5115 mask = -1ULL;
5116 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
5118 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5119 stats = &bp->port_stats;
5120 rx_stats = stats->hw_stats;
5121 rx_masks = stats->hw_masks;
5130 mask = (1ULL << 40) - 1;
5140 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
5141 stats = &bp->rx_port_stats_ext;
5142 rx_stats = stats->hw_stats;
5143 rx_masks = stats->hw_masks;
5145 stats = &bp->tx_port_stats_ext;
5146 tx_stats = stats->hw_stats;
5147 tx_masks = stats->hw_masks;
5153 mask = (1ULL << 40) - 1;
5170 bp->flags &= ~BNXT_FLAG_PORT_STATS;
5171 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
5173 bnxt_free_stats_mem(bp, &bp->port_stats);
5174 bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
5175 bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
5182 if (!bp->bnapi)
5185 for (i = 0; i < bp->cp_nr_rings; i++) {
5186 struct bnxt_napi *bnapi = bp->bnapi[i];
5187 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5189 bnxt_free_stats_mem(bp, &cpr->stats);
5191 kfree(cpr->sw_stats);
5192 cpr->sw_stats = NULL;
5201 size = bp->hw_ring_stats_size;
5203 for (i = 0; i < bp->cp_nr_rings; i++) {
5204 struct bnxt_napi *bnapi = bp->bnapi[i];
5205 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5207 cpr->sw_stats = kzalloc(sizeof(*cpr->sw_stats), GFP_KERNEL);
5208 if (!cpr->sw_stats)
5209 return -ENOMEM;
5211 cpr->stats.len = size;
5212 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
5216 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5219 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
5222 if (bp->port_stats.hw_stats)
5225 bp->port_stats.len = BNXT_PORT_STATS_SIZE;
5226 rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
5230 bp->flags |= BNXT_FLAG_PORT_STATS;
5234 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
5235 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
5238 if (bp->rx_port_stats_ext.hw_stats)
5241 bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
5242 rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
5248 if (bp->tx_port_stats_ext.hw_stats)
5251 if (bp->hwrm_spec_code >= 0x10902 ||
5252 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
5253 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
5254 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
5259 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
5267 if (!bp->bnapi)
5270 for (i = 0; i < bp->cp_nr_rings; i++) {
5271 struct bnxt_napi *bnapi = bp->bnapi[i];
5279 cpr = &bnapi->cp_ring;
5280 cpr->cp_raw_cons = 0;
5283 txr->tx_prod = 0;
5284 txr->tx_cons = 0;
5285 txr->tx_hw_cons = 0;
5288 rxr = bnapi->rx_ring;
5290 rxr->rx_prod = 0;
5291 rxr->rx_agg_prod = 0;
5292 rxr->rx_sw_agg_prod = 0;
5293 rxr->rx_next_cons = 0;
5295 bnapi->events = 0;
5301 u8 type = fltr->type, flags = fltr->flags;
5303 INIT_LIST_HEAD(&fltr->list);
5306 list_add_tail(&fltr->list, &bp->usr_fltr_list);
5311 if (!list_empty(&fltr->list))
5312 list_del_init(&fltr->list);
5319 list_for_each_entry_safe(usr_fltr, tmp, &bp->usr_fltr_list, list) {
5320 if (!all && usr_fltr->type == BNXT_FLTR_TYPE_L2)
5328 hlist_del(&fltr->hash);
5330 if (fltr->flags) {
5331 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5332 bp->ntp_fltr_count--;
5341 netdev_assert_locked_or_invisible(bp->dev);
5351 head = &bp->ntp_fltr_hash_tbl[i];
5353 bnxt_del_l2_filter(bp, fltr->l2_fltr);
5354 if (!all && ((fltr->base.flags & BNXT_ACT_FUNC_DST) ||
5355 !list_empty(&fltr->base.list)))
5357 bnxt_del_fltr(bp, &fltr->base);
5363 bitmap_free(bp->ntp_fltr_bmap);
5364 bp->ntp_fltr_bmap = NULL;
5365 bp->ntp_fltr_count = 0;
5372 if (!(bp->flags & BNXT_FLAG_RFS) || bp->ntp_fltr_bmap)
5376 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
5378 bp->ntp_fltr_count = 0;
5379 bp->ntp_fltr_bmap = bitmap_zalloc(bp->max_fltr, GFP_KERNEL);
5381 if (!bp->ntp_fltr_bmap)
5382 rc = -ENOMEM;
5396 head = &bp->l2_fltr_hash_tbl[i];
5398 if (!all && ((fltr->base.flags & BNXT_ACT_FUNC_DST) ||
5399 !list_empty(&fltr->base.list)))
5401 bnxt_del_fltr(bp, &fltr->base);
5411 INIT_HLIST_HEAD(&bp->l2_fltr_hash_tbl[i]);
5412 get_random_bytes(&bp->hash_seed, sizeof(bp->hash_seed));
5426 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) ||
5427 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
5431 kfree(bp->tx_ring_map);
5432 bp->tx_ring_map = NULL;
5433 kfree(bp->tx_ring);
5434 bp->tx_ring = NULL;
5435 kfree(bp->rx_ring);
5436 bp->rx_ring = NULL;
5437 kfree(bp->bnapi);
5438 bp->bnapi = NULL;
5454 bp->cp_nr_rings);
5456 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
5458 return -ENOMEM;
5460 bp->bnapi = bnapi;
5462 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
5463 bp->bnapi[i] = bnapi;
5464 bp->bnapi[i]->index = i;
5465 bp->bnapi[i]->bp = bp;
5466 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
5468 &bp->bnapi[i]->cp_ring;
5470 cpr->cp_ring_struct.ring_mem.flags =
5475 bp->rx_ring = kcalloc(bp->rx_nr_rings,
5478 if (!bp->rx_ring)
5479 return -ENOMEM;
5481 for (i = 0; i < bp->rx_nr_rings; i++) {
5482 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5484 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
5485 rxr->rx_ring_struct.ring_mem.flags =
5487 rxr->rx_agg_ring_struct.ring_mem.flags =
5490 rxr->rx_cpr = &bp->bnapi[i]->cp_ring;
5492 rxr->bnapi = bp->bnapi[i];
5493 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
5496 bp->tx_ring = kcalloc(bp->tx_nr_rings,
5499 if (!bp->tx_ring)
5500 return -ENOMEM;
5502 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
5505 if (!bp->tx_ring_map)
5506 return -ENOMEM;
5508 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5511 j = bp->rx_nr_rings;
5513 for (i = 0; i < bp->tx_nr_rings; i++) {
5514 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5517 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
5518 txr->tx_ring_struct.ring_mem.flags =
5520 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
5521 if (i >= bp->tx_nr_rings_xdp) {
5524 bnapi2 = bp->bnapi[k];
5525 txr->txq_index = i - bp->tx_nr_rings_xdp;
5526 txr->tx_napi_idx =
5527 BNXT_RING_TO_TC(bp, txr->txq_index);
5528 bnapi2->tx_ring[txr->tx_napi_idx] = txr;
5529 bnapi2->tx_int = bnxt_tx_int;
5531 bnapi2 = bp->bnapi[j];
5532 bnapi2->flags |= BNXT_NAPI_FLAG_XDP;
5533 bnapi2->tx_ring[0] = txr;
5534 bnapi2->tx_int = bnxt_tx_int_xdp;
5537 txr->bnapi = bnapi2;
5538 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
5539 txr->tx_cpr = &bnapi2->cp_ring;
5574 bp->vnic_info[BNXT_VNIC_DEFAULT].flags |= BNXT_VNIC_RSS_FLAG |
5577 if (BNXT_SUPPORTS_NTUPLE_VNIC(bp) && (bp->flags & BNXT_FLAG_RFS))
5578 bp->vnic_info[BNXT_VNIC_NTUPLE].flags |=
5595 if (!bp->bnapi)
5598 for (i = 0; i < bp->cp_nr_rings; i++) {
5599 struct bnxt_napi *bnapi = bp->bnapi[i];
5600 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5601 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5603 if (ring->fw_ring_id != INVALID_HW_RING_ID)
5604 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5610 struct bnxt_napi *bnapi = bp->bnapi[n];
5613 cpr = &bnapi->cp_ring;
5614 return cpr->cp_ring_struct.map_idx;
5621 if (!bp->irq_tbl)
5624 atomic_inc(&bp->intr_sem);
5627 for (i = 0; i < bp->cp_nr_rings; i++) {
5630 synchronize_irq(bp->irq_tbl[map_idx].vector);
5638 atomic_set(&bp->intr_sem, 0);
5639 for (i = 0; i < bp->cp_nr_rings; i++) {
5640 struct bnxt_napi *bnapi = bp->bnapi[i];
5641 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5643 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
5661 req->enables = cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
5665 req->os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
5667 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
5669 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
5672 if (bp->fw_cap & BNXT_FW_CAP_NPAR_1_2)
5674 req->flags = cpu_to_le32(flags);
5675 req->ver_maj_8b = DRV_VER_MAJ;
5676 req->ver_min_8b = DRV_VER_MIN;
5677 req->ver_upd_8b = DRV_VER_UPD;
5678 req->ver_maj = cpu_to_le16(DRV_VER_MAJ);
5679 req->ver_min = cpu_to_le16(DRV_VER_MIN);
5680 req->ver_upd = cpu_to_le16(DRV_VER_UPD);
5697 req->vf_req_fwd[i] = cpu_to_le32(data[i]);
5699 req->enables |=
5703 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
5704 req->flags |= cpu_to_le32(
5712 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5715 !bp->ptp_cfg)
5726 req->async_event_fwd[i] |= cpu_to_le32(events[i]);
5729 req->enables =
5735 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
5736 if (resp->flags &
5738 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
5749 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
5766 bp->vxlan_fw_dst_port_id == INVALID_HW_RING_ID)
5769 bp->nge_fw_dst_port_id == INVALID_HW_RING_ID)
5776 req->tunnel_type = tunnel_type;
5780 req->tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
5781 bp->vxlan_port = 0;
5782 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
5785 req->tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
5786 bp->nge_port = 0;
5787 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
5790 req->tunnel_dst_port_id = cpu_to_le16(bp->vxlan_gpe_fw_dst_port_id);
5791 bp->vxlan_gpe_port = 0;
5792 bp->vxlan_gpe_fw_dst_port_id = INVALID_HW_RING_ID;
5800 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
5802 if (bp->flags & BNXT_FLAG_TPA)
5818 req->tunnel_type = tunnel_type;
5819 req->tunnel_dst_port_val = port;
5824 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
5831 bp->vxlan_port = port;
5832 bp->vxlan_fw_dst_port_id =
5833 le16_to_cpu(resp->tunnel_dst_port_id);
5836 bp->nge_port = port;
5837 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
5840 bp->vxlan_gpe_port = port;
5841 bp->vxlan_gpe_fw_dst_port_id =
5842 le16_to_cpu(resp->tunnel_dst_port_id);
5847 if (bp->flags & BNXT_FLAG_TPA)
5858 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5865 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5866 if (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST) {
5867 req->num_mc_entries = cpu_to_le32(vnic->mc_list_count);
5868 req->mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
5870 req->mask = cpu_to_le32(vnic->rx_mask);
5876 if (!atomic_dec_and_test(&fltr->refcnt))
5878 spin_lock_bh(&bp->ntp_fltr_lock);
5879 if (!test_and_clear_bit(BNXT_FLTR_INSERTED, &fltr->base.state)) {
5880 spin_unlock_bh(&bp->ntp_fltr_lock);
5883 hlist_del_rcu(&fltr->base.hash);
5884 bnxt_del_one_usr_fltr(bp, &fltr->base);
5885 if (fltr->base.flags) {
5886 clear_bit(fltr->base.sw_id, bp->ntp_fltr_bmap);
5887 bp->ntp_fltr_count--;
5889 spin_unlock_bh(&bp->ntp_fltr_lock);
5897 struct hlist_head *head = &bp->l2_fltr_hash_tbl[idx];
5901 struct bnxt_l2_key *l2_key = &fltr->l2_key;
5903 if (ether_addr_equal(l2_key->dst_mac_addr, key->dst_mac_addr) &&
5904 l2_key->vlan == key->vlan)
5919 atomic_inc(&fltr->refcnt);
5925 (((fkeys)->basic.ip_proto == IPPROTO_TCP && \
5926 (bp)->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) || \
5927 ((fkeys)->basic.ip_proto == IPPROTO_UDP && \
5928 (bp)->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4))
5931 (((fkeys)->basic.ip_proto == IPPROTO_TCP && \
5932 (bp)->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) || \
5933 ((fkeys)->basic.ip_proto == IPPROTO_UDP && \
5934 (bp)->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6))
5938 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
5940 return sizeof(fkeys->addrs.v4addrs) +
5941 sizeof(fkeys->ports);
5943 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
5944 return sizeof(fkeys->addrs.v4addrs);
5947 if (fkeys->basic.n_proto == htons(ETH_P_IPV6)) {
5949 return sizeof(fkeys->addrs.v6addrs) +
5950 sizeof(fkeys->ports);
5952 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
5953 return sizeof(fkeys->addrs.v6addrs);
5962 u64 prefix = bp->toeplitz_prefix, hash = 0;
5972 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
5973 tuple4.v4addrs = fkeys->addrs.v4addrs;
5974 tuple4.ports = fkeys->ports;
5977 tuple6.v6addrs = fkeys->addrs.v6addrs;
5978 tuple6.ports = fkeys->ports;
6004 idx = jhash2(&key->filter_key, BNXT_L2_KEY_SIZE, bp->hash_seed) &
6016 ether_addr_copy(fltr->l2_key.dst_mac_addr, key->dst_mac_addr);
6017 fltr->l2_key.vlan = key->vlan;
6018 fltr->base.type = BNXT_FLTR_TYPE_L2;
6019 if (fltr->base.flags) {
6022 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6023 bp->max_fltr, 0);
6025 return -ENOMEM;
6026 fltr->base.sw_id = (u16)bit_id;
6027 bp->ntp_fltr_count++;
6029 head = &bp->l2_fltr_hash_tbl[idx];
6030 hlist_add_head_rcu(&fltr->base.hash, head);
6031 bnxt_insert_usr_fltr(bp, &fltr->base);
6032 set_bit(BNXT_FLTR_INSERTED, &fltr->base.state);
6033 atomic_set(&fltr->refcnt, 1);
6045 idx = jhash2(&key->filter_key, BNXT_L2_KEY_SIZE, bp->hash_seed) &
6053 return ERR_PTR(-ENOMEM);
6054 spin_lock_bh(&bp->ntp_fltr_lock);
6056 spin_unlock_bh(&bp->ntp_fltr_lock);
6072 idx = jhash2(&key->filter_key, BNXT_L2_KEY_SIZE, bp->hash_seed) &
6074 spin_lock_bh(&bp->ntp_fltr_lock);
6077 fltr = ERR_PTR(-EEXIST);
6082 fltr = ERR_PTR(-ENOMEM);
6085 fltr->base.flags = flags;
6088 spin_unlock_bh(&bp->ntp_fltr_lock);
6094 spin_unlock_bh(&bp->ntp_fltr_lock);
6101 struct bnxt_vf_info *vf = &pf->vf[vf_idx];
6103 return vf->fw_fid;
6115 if (fltr->base.flags & BNXT_ACT_FUNC_DST) {
6116 struct bnxt_pf_info *pf = &bp->pf;
6118 if (fltr->base.vf_idx >= pf->active_vfs)
6119 return -EINVAL;
6121 target_id = bnxt_vf_target_id(pf, fltr->base.vf_idx);
6123 return -EINVAL;
6130 req->target_id = cpu_to_le16(target_id);
6131 req->l2_filter_id = fltr->base.filter_id;
6142 if (fltr->base.flags & BNXT_ACT_FUNC_DST) {
6143 struct bnxt_pf_info *pf = &bp->pf;
6145 if (fltr->base.vf_idx >= pf->active_vfs)
6146 return -EINVAL;
6148 target_id = bnxt_vf_target_id(pf, fltr->base.vf_idx);
6154 req->target_id = cpu_to_le16(target_id);
6155 req->flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
6158 req->flags |=
6160 req->dst_id = cpu_to_le16(fltr->base.fw_vnic_id);
6161 req->enables =
6165 ether_addr_copy(req->l2_addr, fltr->l2_key.dst_mac_addr);
6166 eth_broadcast_addr(req->l2_addr_mask);
6168 if (fltr->l2_key.vlan) {
6169 req->enables |=
6173 req->num_vlans = 1;
6174 req->l2_ivlan = cpu_to_le16(fltr->l2_key.vlan);
6175 req->l2_ivlan_mask = cpu_to_le16(0xfff);
6181 fltr->base.filter_id = resp->l2_filter_id;
6182 set_bit(BNXT_FLTR_VALID, &fltr->base.state);
6194 set_bit(BNXT_FLTR_FW_DELETED, &fltr->base.state);
6199 req->ntuple_filter_id = fltr->base.filter_id;
6234 u16 rxq = fltr->base.rxq;
6236 if (fltr->base.flags & BNXT_ACT_RSS_CTX) {
6241 ctx = xa_load(&bp->dev->ethtool->rss_ctx,
6242 fltr->base.fw_vnic_id);
6245 vnic = &rss_ctx->vnic;
6247 req->dst_id = cpu_to_le16(vnic->fw_vnic_id);
6255 vnic = &bp->vnic_info[BNXT_VNIC_NTUPLE];
6256 req->dst_id = cpu_to_le16(vnic->fw_vnic_id);
6258 req->enables |= cpu_to_le32(enables);
6259 req->rfs_ring_tbl_idx = cpu_to_le16(rxq);
6264 req->flags |= cpu_to_le32(flags);
6265 req->dst_id = cpu_to_le16(rxq);
6274 struct bnxt_flow_masks *masks = &fltr->fmasks;
6275 struct flow_keys *keys = &fltr->fkeys;
6284 l2_fltr = fltr->l2_fltr;
6285 req->l2_filter_id = l2_fltr->base.filter_id;
6287 if (fltr->base.flags & BNXT_ACT_DROP) {
6288 req->flags =
6290 } else if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
6293 vnic = &bp->vnic_info[fltr->base.rxq + 1];
6294 req->dst_id = cpu_to_le16(vnic->fw_vnic_id);
6296 req->enables |= cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
6298 req->ethertype = htons(ETH_P_IP);
6299 req->ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
6300 req->ip_protocol = keys->basic.ip_proto;
6302 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
6303 req->ethertype = htons(ETH_P_IPV6);
6304 req->ip_addr_type =
6306 *(struct in6_addr *)&req->src_ipaddr[0] = keys->addrs.v6addrs.src;
6307 *(struct in6_addr *)&req->src_ipaddr_mask[0] = masks->addrs.v6addrs.src;
6308 *(struct in6_addr *)&req->dst_ipaddr[0] = keys->addrs.v6addrs.dst;
6309 *(struct in6_addr *)&req->dst_ipaddr_mask[0] = masks->addrs.v6addrs.dst;
6311 req->src_ipaddr[0] = keys->addrs.v4addrs.src;
6312 req->src_ipaddr_mask[0] = masks->addrs.v4addrs.src;
6313 req->dst_ipaddr[0] = keys->addrs.v4addrs.dst;
6314 req->dst_ipaddr_mask[0] = masks->addrs.v4addrs.dst;
6316 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
6317 req->enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
6318 req->tunnel_type =
6322 req->src_port = keys->ports.src;
6323 req->src_port_mask = masks->ports.src;
6324 req->dst_port = keys->ports.dst;
6325 req->dst_port_mask = masks->ports.dst;
6330 fltr->base.filter_id = resp->ntuple_filter_id;
6348 fltr->base.fw_vnic_id = bp->vnic_info[vnic_id].fw_vnic_id;
6353 bp->vnic_info[vnic_id].l2_filters[idx] = fltr;
6363 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
6365 for (j = 0; j < vnic->uc_filter_count; j++) {
6366 struct bnxt_l2_filter *fltr = vnic->l2_filters[j];
6371 vnic->uc_filter_count = 0;
6385 if (!(bp->fw_cap & BNXT_FW_CAP_VNIC_TUNNEL_TPA))
6388 if (bp->vxlan_port)
6390 if (bp->vxlan_gpe_port)
6392 if (bp->nge_port)
6395 req->enables |= cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN);
6396 req->tnl_tpa_en_bitmap = cpu_to_le32(tunl_tpa_bmap);
6406 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
6414 u16 mss = bp->dev->mtu - 40;
6425 req->flags = cpu_to_le32(flags);
6427 req->enables =
6437 nsegs = (MAX_SKB_FRAGS - 1) * n;
6440 if (mss & (BNXT_RX_PAGE_SIZE - 1))
6442 nsegs = (MAX_SKB_FRAGS - n) / n;
6445 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
6447 max_aggs = bp->max_tpa;
6451 req->max_agg_segs = cpu_to_le16(segs);
6452 req->max_aggs = cpu_to_le16(max_aggs);
6454 req->min_agg_len = cpu_to_le32(512);
6457 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
6466 grp_info = &bp->grp_info[ring->grp_idx];
6467 return grp_info->cp_fw_ring_id;
6472 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
6473 return rxr->rx_cpr->cp_ring_struct.fw_ring_id;
6475 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
6480 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
6481 return txr->tx_cpr->cp_ring_struct.fw_ring_id;
6483 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
6490 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
6495 bp->rss_indir_tbl_entries = entries;
6496 bp->rss_indir_tbl =
6497 kmalloc_array(entries, sizeof(*bp->rss_indir_tbl), GFP_KERNEL);
6498 if (!bp->rss_indir_tbl)
6499 return -ENOMEM;
6510 if (!bp->rx_nr_rings)
6514 max_rings = bp->rx_nr_rings - 1;
6516 max_rings = bp->rx_nr_rings;
6518 max_entries = bnxt_get_rxfh_indir_size(bp->dev);
6522 rss_indir_tbl = &bp->rss_indir_tbl[0];
6527 pad = bp->rss_indir_tbl_entries - max_entries;
6536 if (!bp->rss_indir_tbl)
6539 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
6541 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
6547 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
6550 return bnxt_calc_nr_ring_pages(rx_rings - 1,
6560 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
6566 j = bp->rss_indir_tbl[i];
6567 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
6574 __le16 *ring_tbl = vnic->rss_table;
6578 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
6583 if (vnic->flags & BNXT_VNIC_NTUPLE_FLAG)
6584 j = ethtool_rxfh_indir_default(i, bp->rx_nr_rings);
6585 else if (vnic->flags & BNXT_VNIC_RSSCTX_FLAG)
6586 j = ethtool_rxfh_context_indir(vnic->rss_ctx)[i];
6588 j = bp->rss_indir_tbl[i];
6589 rxr = &bp->rx_ring[j];
6591 ring_id = rxr->rx_ring_struct.fw_ring_id;
6602 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
6604 if (bp->flags & BNXT_FLAG_CHIP_P7)
6605 req->flags |= VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT;
6610 if (bp->rss_hash_delta) {
6611 req->hash_type = cpu_to_le32(bp->rss_hash_delta);
6612 if (bp->rss_hash_cfg & bp->rss_hash_delta)
6613 req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE;
6615 req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE;
6617 req->hash_type = cpu_to_le32(bp->rss_hash_cfg);
6619 req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
6620 req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
6621 req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
6630 if ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ||
6631 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
6640 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
6656 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
6661 ring_tbl_map = vnic->rss_table_dma_addr;
6662 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
6666 req->ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
6667 req->ring_table_pair_index = i;
6668 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
6681 struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
6688 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
6690 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
6693 bp->rss_hash_cfg = le32_to_cpu(resp->hash_type) ?: bp->rss_hash_cfg;
6694 bp->rss_hash_delta = 0;
6701 u16 hds_thresh = (u16)bp->dev->cfg_pending->hds_thresh;
6709 req->flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT);
6710 req->enables = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID);
6711 req->jumbo_thresh = cpu_to_le16(bp->rx_buf_use_size);
6713 if (!BNXT_RX_PAGE_MODE(bp) && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
6714 req->flags |= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
6716 req->enables |=
6718 req->hds_threshold = cpu_to_le16(hds_thresh);
6720 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
6733 req->rss_cos_lb_ctx_id =
6734 cpu_to_le16(vnic->fw_rss_cos_lb_ctx[ctx_idx]);
6737 vnic->fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
6744 for (i = 0; i < bp->nr_vnics; i++) {
6745 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
6748 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
6752 bp->rsscos_nr_ctxs = 0;
6769 vnic->fw_rss_cos_lb_ctx[ctx_idx] =
6770 le16_to_cpu(resp->rss_cos_lb_ctx_id);
6778 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
6785 struct bnxt_vnic_info *vnic0 = &bp->vnic_info[BNXT_VNIC_DEFAULT];
6795 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
6796 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
6798 req->default_rx_ring_id =
6799 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
6800 req->default_cmpl_ring_id =
6802 req->enables =
6807 req->enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
6809 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
6810 req->rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
6811 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
6813 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
6814 req->rss_rule = cpu_to_le16(vnic0->fw_rss_cos_lb_ctx[0]);
6815 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
6817 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
6819 req->rss_rule = cpu_to_le16(0xffff);
6823 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
6824 req->cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
6825 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
6827 req->cos_rule = cpu_to_le16(0xffff);
6830 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
6832 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
6833 ring = vnic->vnic_id - 1;
6834 else if ((vnic->vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
6835 ring = bp->rx_nr_rings - 1;
6837 grp_idx = bp->rx_ring[ring].bnapi->index;
6838 req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
6839 req->lb_rule = cpu_to_le16(0xffff);
6841 vnic->mru = bp->dev->mtu + VLAN_ETH_HLEN;
6842 req->mru = cpu_to_le16(vnic->mru);
6844 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
6847 def_vlan = bp->vf.vlan;
6849 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
6850 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
6851 if (vnic->vnic_id == BNXT_VNIC_DEFAULT && bnxt_ulp_registered(bp->edev))
6852 req->flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
6860 if (vnic->fw_vnic_id != INVALID_HW_RING_ID) {
6866 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
6869 vnic->fw_vnic_id = INVALID_HW_RING_ID;
6877 for (i = 0; i < bp->nr_vnics; i++)
6878 bnxt_hwrm_vnic_free_one(bp, &bp->vnic_info[i]);
6894 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
6899 grp_idx = bp->rx_ring[i].bnapi->index;
6900 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
6901 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
6905 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
6910 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
6911 if (vnic->vnic_id == BNXT_VNIC_DEFAULT)
6912 req->flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
6917 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
6928 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
6929 bp->flags &= ~BNXT_FLAG_ROCE_MIRROR_CAP;
6930 bp->rss_cap &= ~BNXT_RSS_CAP_NEW_RSS_CAP;
6931 if (bp->hwrm_spec_code < 0x10600)
6941 u32 flags = le32_to_cpu(resp->flags);
6943 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&
6945 bp->rss_cap |= BNXT_RSS_CAP_NEW_RSS_CAP;
6948 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
6955 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
6956 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
6958 bp->rss_cap |= BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA;
6960 bp->rss_cap |= BNXT_RSS_CAP_RSS_TCAM;
6961 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
6962 if (bp->max_tpa_v2) {
6964 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
6966 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P7;
6969 bp->fw_cap |= BNXT_FW_CAP_VNIC_TUNNEL_TPA;
6971 bp->rss_cap |= BNXT_RSS_CAP_AH_V4_RSS_CAP;
6973 bp->rss_cap |= BNXT_RSS_CAP_AH_V6_RSS_CAP;
6975 bp->rss_cap |= BNXT_RSS_CAP_ESP_V4_RSS_CAP;
6977 bp->rss_cap |= BNXT_RSS_CAP_ESP_V6_RSS_CAP;
6979 bp->rss_cap |= BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP;
6981 bp->fw_cap |= BNXT_FW_CAP_VNIC_RE_FLUSH;
6994 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
7002 for (i = 0; i < bp->rx_nr_rings; i++) {
7003 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
7005 req->cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
7006 req->rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
7007 req->ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
7008 req->sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
7015 bp->grp_info[grp_idx].fw_grp_id =
7016 le32_to_cpu(resp->ring_group_id);
7027 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
7034 for (i = 0; i < bp->cp_nr_rings; i++) {
7035 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
7037 req->ring_group_id =
7038 cpu_to_le32(bp->grp_info[i].fw_grp_id);
7041 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
7050 struct bnxt_ring_grp_info *grp_info = &bp->grp_info[ring->grp_idx];
7055 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
7056 req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
7057 req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
7060 req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
7062 req->flags =
7065 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
7066 req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
7067 req->enables |= cpu_to_le32(enables);
7076 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
7085 req->enables = 0;
7086 if (rmem->nr_pages > 1) {
7087 req->page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
7089 req->page_size = BNXT_PAGE_SHIFT;
7090 req->page_tbl_depth = 1;
7092 req->page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
7094 req->fbo = 0;
7096 req->logical_id = cpu_to_le16(map_index);
7105 req->ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
7107 grp_info = &bp->grp_info[ring->grp_idx];
7108 req->cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
7109 req->length = cpu_to_le32(bp->tx_ring_mask + 1);
7110 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
7111 req->queue_id = cpu_to_le16(ring->queue_id);
7112 if (bp->flags & BNXT_FLAG_TX_COAL_CMPL)
7113 req->cmpl_coal_cnt =
7115 if ((bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP) && bp->ptp_cfg)
7117 req->flags = cpu_to_le16(flags);
7122 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
7123 req->length = (ring_type == HWRM_RING_ALLOC_RX) ?
7124 cpu_to_le32(bp->rx_ring_mask + 1) :
7125 cpu_to_le32(bp->rx_agg_ring_mask + 1);
7126 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
7130 req->ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
7131 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
7132 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7134 grp_info = &bp->grp_info[map_index];
7135 req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
7136 req->cq_handle = cpu_to_le64(ring->handle);
7137 req->enables |= cpu_to_le32(
7140 req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
7144 req->ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
7145 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
7146 req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
7149 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
7151 return -EINVAL;
7156 err = le16_to_cpu(resp->error_code);
7157 ring_id = le16_to_cpu(resp->ring_id);
7162 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
7164 return -EIO;
7166 ring->fw_ring_id = ring_id;
7181 req->fid = cpu_to_le16(0xffff);
7182 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
7183 req->async_event_cr = cpu_to_le16(idx);
7192 req->enables =
7194 req->async_event_cr = cpu_to_le16(idx);
7204 db->db_ring_mask = bp->tx_ring_mask;
7207 db->db_ring_mask = bp->rx_ring_mask;
7210 db->db_ring_mask = bp->rx_agg_ring_mask;
7214 db->db_ring_mask = bp->cp_ring_mask;
7217 if (bp->flags & BNXT_FLAG_CHIP_P7) {
7218 db->db_epoch_mask = db->db_ring_mask + 1;
7219 db->db_epoch_shift = DBR_EPOCH_SFT - ilog2(db->db_epoch_mask);
7226 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7229 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
7233 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
7236 db->db_key64 = DBR_PATH_L2;
7239 db->db_key64 = DBR_PATH_L2;
7242 db->db_key64 |= (u64)xid << DBR_XID_SFT;
7244 if (bp->flags & BNXT_FLAG_CHIP_P7)
7245 db->db_key64 |= DBR_VALID;
7247 db->doorbell = bp->bar1 + bp->db_offset;
7249 db->doorbell = bp->bar1 + map_idx * 0x80;
7252 db->db_key32 = DB_KEY_TX;
7256 db->db_key32 = DB_KEY_RX;
7259 db->db_key32 = DB_KEY_CP;
7269 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
7270 struct bnxt_napi *bnapi = rxr->bnapi;
7272 u32 map_idx = bnapi->index;
7279 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
7280 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
7288 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
7290 u32 grp_idx = ring->grp_idx;
7294 map_idx = grp_idx + bp->rx_nr_rings;
7299 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
7300 ring->fw_ring_id);
7301 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
7302 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
7303 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
7312 struct bnxt_napi *bnapi = cpr->bnapi;
7314 u32 map_idx = bnapi->index;
7317 ring = &cpr->cp_ring_struct;
7318 ring->handle = BNXT_SET_NQ_HDL(cpr);
7322 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
7323 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
7330 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
7337 bnxt_set_db(bp, &txr->tx_db, type, tx_idx, ring->fw_ring_id);
7343 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
7347 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
7351 for (i = 0; i < bp->cp_nr_rings; i++) {
7352 struct bnxt_napi *bnapi = bp->bnapi[i];
7353 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7354 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
7355 u32 map_idx = ring->map_idx;
7358 vector = bp->irq_tbl[map_idx].vector;
7365 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
7366 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
7368 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
7371 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
7373 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
7377 for (i = 0; i < bp->tx_nr_rings; i++) {
7378 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
7380 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7381 rc = bnxt_hwrm_cp_ring_alloc_p5(bp, txr->tx_cpr);
7390 for (i = 0; i < bp->rx_nr_rings; i++) {
7391 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
7398 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
7399 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7400 rc = bnxt_hwrm_cp_ring_alloc_p5(bp, rxr->rx_cpr);
7407 for (i = 0; i < bp->rx_nr_rings; i++) {
7408 rc = bnxt_hwrm_rx_agg_ring_alloc(bp, &bp->rx_ring[i]);
7424 if (!bp->bnapi || test_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
7429 for (i = 0; i < bp->rx_nr_rings; i++) {
7430 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
7431 struct bnxt_napi *bnapi = rxr->bnapi;
7433 cancel_work_sync(&bnapi->cp_ring.dim.work);
7453 req->cmpl_ring = cpu_to_le16(cmpl_ring_id);
7454 req->ring_type = ring_type;
7455 req->ring_id = cpu_to_le16(ring->fw_ring_id);
7459 error_code = le16_to_cpu(resp->error_code);
7463 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
7465 return -EIO;
7474 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
7477 if (ring->fw_ring_id == INVALID_HW_RING_ID)
7484 ring->fw_ring_id = INVALID_HW_RING_ID;
7491 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
7492 u32 grp_idx = rxr->bnapi->index;
7495 if (ring->fw_ring_id == INVALID_HW_RING_ID)
7503 ring->fw_ring_id = INVALID_HW_RING_ID;
7504 bp->grp_info[grp_idx].rx_fw_ring_id = INVALID_HW_RING_ID;
7511 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
7512 u32 grp_idx = rxr->bnapi->index;
7515 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
7520 if (ring->fw_ring_id == INVALID_HW_RING_ID)
7527 ring->fw_ring_id = INVALID_HW_RING_ID;
7528 bp->grp_info[grp_idx].agg_fw_ring_id = INVALID_HW_RING_ID;
7536 ring = &cpr->cp_ring_struct;
7537 if (ring->fw_ring_id == INVALID_HW_RING_ID)
7542 ring->fw_ring_id = INVALID_HW_RING_ID;
7547 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
7548 int i, size = ring->ring_mem.page_size;
7550 cpr->cp_raw_cons = 0;
7551 cpr->toggle = 0;
7553 for (i = 0; i < bp->cp_nr_pages; i++)
7554 if (cpr->cp_desc_ring[i])
7555 memset(cpr->cp_desc_ring[i], 0, size);
7563 if (!bp->bnapi)
7566 for (i = 0; i < bp->tx_nr_rings; i++)
7567 bnxt_hwrm_tx_ring_free(bp, &bp->tx_ring[i], close_path);
7570 for (i = 0; i < bp->rx_nr_rings; i++) {
7571 bnxt_hwrm_rx_ring_free(bp, &bp->rx_ring[i], close_path);
7572 bnxt_hwrm_rx_agg_ring_free(bp, &bp->rx_ring[i], close_path);
7581 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
7585 for (i = 0; i < bp->cp_nr_rings; i++) {
7586 struct bnxt_napi *bnapi = bp->bnapi[i];
7587 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7591 for (j = 0; j < cpr->cp_ring_count && cpr->cp_ring_arr; j++)
7592 bnxt_hwrm_cp_ring_free(bp, &cpr->cp_ring_arr[j]);
7594 ring = &cpr->cp_ring_struct;
7595 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
7598 ring->fw_ring_id = INVALID_HW_RING_ID;
7599 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
7611 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7616 if (bp->hwrm_spec_code < 0x10601)
7623 req->fid = cpu_to_le16(0xffff);
7631 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
7635 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
7636 hw_resc->resv_hw_ring_grps =
7637 le32_to_cpu(resp->alloc_hw_ring_grps);
7638 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
7639 hw_resc->resv_rsscos_ctxs = le16_to_cpu(resp->alloc_rsscos_ctx);
7640 cp = le16_to_cpu(resp->alloc_cmpl_rings);
7641 stats = le16_to_cpu(resp->alloc_stat_ctx);
7642 hw_resc->resv_irqs = cp;
7643 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7644 int rx = hw_resc->resv_rx_rings;
7645 int tx = hw_resc->resv_tx_rings;
7647 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7653 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7655 hw_resc->resv_rx_rings = rx;
7656 hw_resc->resv_tx_rings = tx;
7658 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
7659 hw_resc->resv_hw_ring_grps = rx;
7661 hw_resc->resv_cp_rings = cp;
7662 hw_resc->resv_stat_ctxs = stats;
7675 if (bp->hwrm_spec_code < 0x10601)
7682 req->fid = cpu_to_le16(fid);
7686 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
7703 req->fid = cpu_to_le16(0xffff);
7704 enables |= hwr->tx ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
7705 req->num_tx_rings = cpu_to_le16(hwr->tx);
7707 enables |= hwr->rx ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
7708 enables |= hwr->stat ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
7709 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7710 enables |= hwr->cp ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
7711 enables |= hwr->cp_p5 ?
7714 enables |= hwr->cp ?
7716 enables |= hwr->grp ?
7719 enables |= hwr->vnic ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
7720 enables |= hwr->rss_ctx ? FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS :
7722 req->num_rx_rings = cpu_to_le16(hwr->rx);
7723 req->num_rsscos_ctxs = cpu_to_le16(hwr->rss_ctx);
7724 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7725 req->num_cmpl_rings = cpu_to_le16(hwr->cp_p5);
7726 req->num_msix = cpu_to_le16(hwr->cp);
7728 req->num_cmpl_rings = cpu_to_le16(hwr->cp);
7729 req->num_hw_ring_grps = cpu_to_le16(hwr->grp);
7731 req->num_stat_ctxs = cpu_to_le16(hwr->stat);
7732 req->num_vnics = cpu_to_le16(hwr->vnic);
7734 req->enables = cpu_to_le32(enables);
7747 enables |= hwr->tx ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
7748 enables |= hwr->rx ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
7750 enables |= hwr->stat ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
7751 enables |= hwr->rss_ctx ? FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
7752 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7753 enables |= hwr->cp_p5 ?
7756 enables |= hwr->cp ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
7757 enables |= hwr->grp ?
7760 enables |= hwr->vnic ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
7763 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
7764 req->num_tx_rings = cpu_to_le16(hwr->tx);
7765 req->num_rx_rings = cpu_to_le16(hwr->rx);
7766 req->num_rsscos_ctxs = cpu_to_le16(hwr->rss_ctx);
7767 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7768 req->num_cmpl_rings = cpu_to_le16(hwr->cp_p5);
7770 req->num_cmpl_rings = cpu_to_le16(hwr->cp);
7771 req->num_hw_ring_grps = cpu_to_le16(hwr->grp);
7773 req->num_stat_ctxs = cpu_to_le16(hwr->stat);
7774 req->num_vnics = cpu_to_le16(hwr->vnic);
7776 req->enables = cpu_to_le32(enables);
7788 return -ENOMEM;
7790 if (!req->enables) {
7799 if (bp->hwrm_spec_code < 0x10601)
7800 bp->hw_resc.resv_tx_rings = hwr->tx;
7812 bp->hw_resc.resv_tx_rings = hwr->tx;
7818 return -ENOMEM;
7837 return bp->cp_nr_rings + bnxt_get_ulp_msix_num(bp);
7844 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
7847 cp = bp->tx_nr_rings + bp->rx_nr_rings;
7853 return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp);
7858 if (!hwr->grp)
7860 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
7861 int rss_ctx = bnxt_get_nr_rss_ctxs(bp, hwr->grp);
7864 rss_ctx *= hwr->vnic;
7869 if (!(bp->rss_cap & BNXT_RSS_CAP_NEW_RSS_CAP) && bnxt_rfs_supported(bp))
7870 return hwr->grp + 1;
7879 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7882 if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
7883 hw_resc->resv_rx_rings = bp->rx_nr_rings;
7884 if (!netif_is_rxfh_configured(bp->dev))
7891 if (bp->flags & BNXT_FLAG_RFS) {
7893 return 2 + bp->num_rss_ctx;
7894 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
7902 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7905 int rx = bp->rx_nr_rings, stat;
7916 if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
7917 bp->hwrm_spec_code >= 0x10601)
7925 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7928 if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
7929 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
7930 (hw_resc->resv_hw_ring_grps != grp &&
7931 !(bp->flags & BNXT_FLAG_CHIP_P5_PLUS)))
7933 if ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) && BNXT_PF(bp) &&
7934 hw_resc->resv_irqs != nq)
7941 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7943 hwr->tx = hw_resc->resv_tx_rings;
7945 hwr->rx = hw_resc->resv_rx_rings;
7946 hwr->cp = hw_resc->resv_irqs;
7947 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
7948 hwr->cp_p5 = hw_resc->resv_cp_rings;
7949 hwr->grp = hw_resc->resv_hw_ring_grps;
7950 hwr->vnic = hw_resc->resv_vnics;
7951 hwr->stat = hw_resc->resv_stat_ctxs;
7952 hwr->rss_ctx = hw_resc->resv_rsscos_ctxs;
7958 return hwr->tx && hwr->rx && hwr->cp && hwr->grp && hwr->vnic &&
7959 hwr->stat && (hwr->cp_p5 || !(bp->flags & BNXT_FLAG_CHIP_P5_PLUS));
7968 int cp = bp->cp_nr_rings;
7976 if (BNXT_NEW_RM(bp) && !bnxt_ulp_registered(bp->edev)) {
7977 ulp_msix = bnxt_get_avail_msix(bp, bp->ulp_num_msix_want);
7981 if (ulp_msix > bp->ulp_num_msix_want)
7982 ulp_msix = bp->ulp_num_msix_want;
7988 hwr.tx = bp->tx_nr_rings;
7989 hwr.rx = bp->rx_nr_rings;
7990 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7992 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
7997 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7999 hwr.grp = bp->rx_nr_rings;
8002 old_rx_rings = bp->hw_resc.resv_rx_rings;
8011 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8015 if (netif_running(bp->dev))
8016 return -ENOMEM;
8018 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8019 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8020 bp->dev->hw_features &= ~NETIF_F_LRO;
8021 bp->dev->features &= ~NETIF_F_LRO;
8026 hwr.cp = min_t(int, hwr.cp, bp->cp_nr_rings);
8027 if (bnxt_ulp_registered(bp->edev) &&
8029 hwr.stat -= bnxt_get_ulp_stat_ctxs(bp);
8032 if (bp->flags & BNXT_FLAG_AGG_RINGS)
8036 if (hwr.tx != bp->tx_nr_rings) {
8037 netdev_warn(bp->dev,
8039 hwr.tx, bp->tx_nr_rings);
8041 bp->tx_nr_rings = hwr.tx;
8046 if (rx_rings != bp->rx_nr_rings) {
8047 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
8048 rx_rings, bp->rx_nr_rings);
8049 if (netif_is_rxfh_configured(bp->dev) &&
8050 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
8053 netdev_warn(bp->dev, "RSS table entries reverting to default\n");
8054 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
8057 bp->rx_nr_rings = rx_rings;
8058 bp->cp_nr_rings = hwr.cp;
8061 return -ENOMEM;
8063 if (old_rx_rings != bp->hw_resc.resv_rx_rings &&
8064 !netif_is_rxfh_configured(bp->dev))
8067 if (!bnxt_ulp_registered(bp->edev) && BNXT_NEW_RM(bp)) {
8071 hw_resc = &bp->hw_resc;
8072 resv_msix = hw_resc->resv_irqs - bp->cp_nr_rings;
8075 resv_ctx = hw_resc->resv_stat_ctxs - bp->cp_nr_rings;
8098 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
8101 req->flags = cpu_to_le32(flags);
8117 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
8124 req->flags = cpu_to_le32(flags);
8130 if (bp->hwrm_spec_code < 0x10801)
8141 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
8146 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
8147 coal_cap->num_cmpl_dma_aggr_max = 63;
8148 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
8149 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
8150 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
8151 coal_cap->int_lat_tmr_min_max = 65535;
8152 coal_cap->int_lat_tmr_max_max = 65535;
8153 coal_cap->num_cmpl_aggr_int_max = 65535;
8154 coal_cap->timer_units = 80;
8156 if (bp->hwrm_spec_code < 0x10902)
8165 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
8166 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
8167 coal_cap->num_cmpl_dma_aggr_max =
8168 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
8169 coal_cap->num_cmpl_dma_aggr_during_int_max =
8170 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
8171 coal_cap->cmpl_aggr_dma_tmr_max =
8172 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
8173 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
8174 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
8175 coal_cap->int_lat_tmr_min_max =
8176 le16_to_cpu(resp->int_lat_tmr_min_max);
8177 coal_cap->int_lat_tmr_max_max =
8178 le16_to_cpu(resp->int_lat_tmr_max_max);
8179 coal_cap->num_cmpl_aggr_int_max =
8180 le16_to_cpu(resp->num_cmpl_aggr_int_max);
8181 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
8188 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
8190 return usec * 1000 / coal_cap->timer_units;
8197 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
8198 u16 val, tmr, max, flags = hw_coal->flags;
8199 u32 cmpl_params = coal_cap->cmpl_params;
8201 max = hw_coal->bufs_per_record * 128;
8202 if (hw_coal->budget)
8203 max = hw_coal->bufs_per_record * hw_coal->budget;
8204 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
8206 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
8207 req->num_cmpl_aggr_int = cpu_to_le16(val);
8209 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
8210 req->num_cmpl_dma_aggr = cpu_to_le16(val);
8212 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
8213 coal_cap->num_cmpl_dma_aggr_during_int_max);
8214 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
8216 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
8217 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
8218 req->int_lat_tmr_max = cpu_to_le16(tmr);
8223 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
8224 req->int_lat_tmr_min = cpu_to_le16(val);
8225 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
8229 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
8230 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
8234 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
8236 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
8237 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
8238 req->enables |=
8243 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
8245 req->flags = cpu_to_le16(flags);
8246 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
8253 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8254 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
8255 u32 nq_params = coal_cap->nq_params;
8266 req->ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
8267 req->flags =
8270 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
8271 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
8272 req->int_lat_tmr_min = cpu_to_le16(tmr);
8273 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
8280 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8287 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
8289 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
8290 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
8292 if (!bnapi->rx_ring)
8293 return -ENODEV;
8301 req_rx->ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
8310 u16 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
8312 req->ring_id = cpu_to_le16(ring_id);
8327 req->ring_id = cpu_to_le16(ring_id);
8331 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
8352 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, req_rx);
8353 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, req_tx);
8357 for (i = 0; i < bp->cp_nr_rings; i++) {
8358 struct bnxt_napi *bnapi = bp->bnapi[i];
8361 if (!bnapi->rx_ring)
8368 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
8371 if (bnapi->rx_ring && bnapi->tx_ring[0]) {
8376 if (bnapi->rx_ring)
8377 hw_coal = &bp->rx_coal;
8379 hw_coal = &bp->tx_coal;
8393 if (!bp->bnapi)
8409 for (i = 0; i < bp->cp_nr_rings; i++) {
8410 struct bnxt_napi *bnapi = bp->bnapi[i];
8411 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8413 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
8414 req->stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
8416 req0->stat_ctx_id = req->stat_ctx_id;
8421 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
8442 req->stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
8443 req->update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
8446 for (i = 0; i < bp->cp_nr_rings; i++) {
8447 struct bnxt_napi *bnapi = bp->bnapi[i];
8448 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8450 req->stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
8456 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
8458 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
8475 req->fid = cpu_to_le16(0xffff);
8481 flags = le16_to_cpu(resp->flags);
8484 struct bnxt_vf_info *vf = &bp->vf;
8486 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
8488 vf->flags |= BNXT_VF_TRUST;
8490 vf->flags &= ~BNXT_VF_TRUST;
8492 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
8497 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
8499 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
8502 bp->flags |= BNXT_FLAG_MULTI_HOST;
8505 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
8508 bp->fw_cap |= BNXT_FW_CAP_ENABLE_RDMA_SRIOV;
8510 switch (resp->port_partition_type) {
8515 bp->port_partition_type = resp->port_partition_type;
8518 if (bp->hwrm_spec_code < 0x10707 ||
8519 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
8520 bp->br_mode = BRIDGE_MODE_VEB;
8521 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
8522 bp->br_mode = BRIDGE_MODE_VEPA;
8524 bp->br_mode = BRIDGE_MODE_UNDEF;
8526 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
8527 if (!bp->max_mtu)
8528 bp->max_mtu = BNXT_MAX_MTU;
8530 if (bp->db_size)
8533 bp->db_offset = le16_to_cpu(resp->legacy_l2_db_size_kb) * 1024;
8536 bp->db_offset = DB_PF_OFFSET_P5;
8538 bp->db_offset = DB_VF_OFFSET_P5;
8540 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
8542 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
8543 bp->db_size <= bp->db_offset)
8544 bp->db_size = pci_resource_len(bp->pdev, 2);
8555 ctxm->init_value = init_val;
8556 ctxm->init_offset = BNXT_CTX_INIT_INVALID_OFFSET;
8558 ctxm->init_offset = init_offset * 4;
8560 ctxm->init_value = 0;
8565 struct bnxt_ctx_mem_info *ctx = bp->ctx;
8569 struct bnxt_ctx_mem_type *ctxm = &ctx->ctx_arr[type];
8572 if (!ctxm->max_entries || ctxm->pg_info)
8575 if (ctxm->instance_bmap)
8576 n = hweight32(ctxm->instance_bmap);
8577 ctxm->pg_info = kcalloc(n, sizeof(*ctxm->pg_info), GFP_KERNEL);
8578 if (!ctxm->pg_info)
8579 return -ENOMEM;
8595 struct bnxt_ctx_mem_info *ctx = bp->ctx;
8606 return -ENOMEM;
8607 bp->ctx = ctx;
8613 struct bnxt_ctx_mem_type *ctxm = &ctx->ctx_arr[type];
8620 req->type = cpu_to_le16(type);
8624 flags = le32_to_cpu(resp->flags);
8625 type = le16_to_cpu(resp->next_valid_type);
8630 entry_size = le16_to_cpu(resp->entry_size);
8631 max_entries = le32_to_cpu(resp->max_num_entries);
8632 if (ctxm->mem_valid) {
8634 ctxm->entry_size != entry_size ||
8635 ctxm->max_entries != max_entries)
8640 ctxm->type = le16_to_cpu(resp->type);
8641 ctxm->entry_size = entry_size;
8642 ctxm->flags = flags;
8643 ctxm->instance_bmap = le32_to_cpu(resp->instance_bit_map);
8644 ctxm->entry_multiple = resp->entry_multiple;
8645 ctxm->max_entries = max_entries;
8646 ctxm->min_entries = le32_to_cpu(resp->min_num_entries);
8647 init_val = resp->ctx_init_value;
8648 init_off = resp->ctx_init_offset;
8651 ctxm->split_entry_cnt = min_t(u8, resp->subtype_valid_cnt,
8653 for (i = 0, p = &resp->split_entry_0; i < ctxm->split_entry_cnt;
8655 ctxm->split[i] = le32_to_cpu(*p);
8670 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) ||
8671 (bp->ctx && bp->ctx->flags & BNXT_CTX_FLAG_INITED))
8674 if (bp->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2)
8689 ctx = bp->ctx;
8693 rc = -ENOMEM;
8696 bp->ctx = ctx;
8698 init_val = resp->ctx_kind_initializer;
8699 init_mask = le16_to_cpu(resp->ctx_init_mask);
8701 ctxm = &ctx->ctx_arr[BNXT_CTX_QP];
8702 ctxm->max_entries = le32_to_cpu(resp->qp_max_entries);
8703 ctxm->qp_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
8704 ctxm->qp_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
8705 ctxm->qp_fast_qpmd_entries = le16_to_cpu(resp->fast_qpmd_qp_num_entries);
8706 ctxm->entry_size = le16_to_cpu(resp->qp_entry_size);
8707 bnxt_init_ctx_initializer(ctxm, init_val, resp->qp_init_offset,
8710 ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ];
8711 ctxm->srq_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
8712 ctxm->max_entries = le32_to_cpu(resp->srq_max_entries);
8713 ctxm->entry_size = le16_to_cpu(resp->srq_entry_size);
8714 bnxt_init_ctx_initializer(ctxm, init_val, resp->srq_init_offset,
8717 ctxm = &ctx->ctx_arr[BNXT_CTX_CQ];
8718 ctxm->cq_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
8719 ctxm->max_entries = le32_to_cpu(resp->cq_max_entries);
8720 ctxm->entry_size = le16_to_cpu(resp->cq_entry_size);
8721 bnxt_init_ctx_initializer(ctxm, init_val, resp->cq_init_offset,
8724 ctxm = &ctx->ctx_arr[BNXT_CTX_VNIC];
8725 ctxm->vnic_entries = le16_to_cpu(resp->vnic_max_vnic_entries);
8726 ctxm->max_entries = ctxm->vnic_entries +
8727 le16_to_cpu(resp->vnic_max_ring_table_entries);
8728 ctxm->entry_size = le16_to_cpu(resp->vnic_entry_size);
8730 resp->vnic_init_offset,
8733 ctxm = &ctx->ctx_arr[BNXT_CTX_STAT];
8734 ctxm->max_entries = le32_to_cpu(resp->stat_max_entries);
8735 ctxm->entry_size = le16_to_cpu(resp->stat_entry_size);
8737 resp->stat_init_offset,
8740 ctxm = &ctx->ctx_arr[BNXT_CTX_STQM];
8741 ctxm->entry_size = le16_to_cpu(resp->tqm_entry_size);
8742 ctxm->min_entries = le32_to_cpu(resp->tqm_min_entries_per_ring);
8743 ctxm->max_entries = le32_to_cpu(resp->tqm_max_entries_per_ring);
8744 ctxm->entry_multiple = resp->tqm_entries_multiple;
8745 if (!ctxm->entry_multiple)
8746 ctxm->entry_multiple = 1;
8748 memcpy(&ctx->ctx_arr[BNXT_CTX_FTQM], ctxm, sizeof(*ctxm));
8750 ctxm = &ctx->ctx_arr[BNXT_CTX_MRAV];
8751 ctxm->max_entries = le32_to_cpu(resp->mrav_max_entries);
8752 ctxm->entry_size = le16_to_cpu(resp->mrav_entry_size);
8753 ctxm->mrav_num_entries_units =
8754 le16_to_cpu(resp->mrav_num_entries_units);
8756 resp->mrav_init_offset,
8759 ctxm = &ctx->ctx_arr[BNXT_CTX_TIM];
8760 ctxm->entry_size = le16_to_cpu(resp->tim_entry_size);
8761 ctxm->max_entries = le32_to_cpu(resp->tim_max_entries);
8763 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
8764 if (!ctx->tqm_fp_rings_count)
8765 ctx->tqm_fp_rings_count = bp->max_q;
8766 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
8767 ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
8769 ctxm = &ctx->ctx_arr[BNXT_CTX_FTQM];
8770 memcpy(ctxm, &ctx->ctx_arr[BNXT_CTX_STQM], sizeof(*ctxm));
8771 ctxm->instance_bmap = (1 << ctx->tqm_fp_rings_count) - 1;
8785 if (!rmem->nr_pages)
8789 if (rmem->depth >= 1) {
8790 if (rmem->depth == 2)
8794 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
8796 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
8810 struct bnxt_ctx_mem_info *ctx = bp->ctx;
8826 if (req_len > bp->hwrm_max_ext_req_len)
8832 req->enables = cpu_to_le32(enables);
8834 ctxm = &ctx->ctx_arr[BNXT_CTX_QP];
8835 ctx_pg = ctxm->pg_info;
8836 req->qp_num_entries = cpu_to_le32(ctx_pg->entries);
8837 req->qp_num_qp1_entries = cpu_to_le16(ctxm->qp_qp1_entries);
8838 req->qp_num_l2_entries = cpu_to_le16(ctxm->qp_l2_entries);
8839 req->qp_entry_size = cpu_to_le16(ctxm->entry_size);
8840 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
8841 &req->qpc_pg_size_qpc_lvl,
8842 &req->qpc_page_dir);
8845 req->qp_num_fast_qpmd_entries = cpu_to_le16(ctxm->qp_fast_qpmd_entries);
8848 ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ];
8849 ctx_pg = ctxm->pg_info;
8850 req->srq_num_entries = cpu_to_le32(ctx_pg->entries);
8851 req->srq_num_l2_entries = cpu_to_le16(ctxm->srq_l2_entries);
8852 req->srq_entry_size = cpu_to_le16(ctxm->entry_size);
8853 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
8854 &req->srq_pg_size_srq_lvl,
8855 &req->srq_page_dir);
8858 ctxm = &ctx->ctx_arr[BNXT_CTX_CQ];
8859 ctx_pg = ctxm->pg_info;
8860 req->cq_num_entries = cpu_to_le32(ctx_pg->entries);
8861 req->cq_num_l2_entries = cpu_to_le16(ctxm->cq_l2_entries);
8862 req->cq_entry_size = cpu_to_le16(ctxm->entry_size);
8863 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
8864 &req->cq_pg_size_cq_lvl,
8865 &req->cq_page_dir);
8868 ctxm = &ctx->ctx_arr[BNXT_CTX_VNIC];
8869 ctx_pg = ctxm->pg_info;
8870 req->vnic_num_vnic_entries = cpu_to_le16(ctxm->vnic_entries);
8871 req->vnic_num_ring_table_entries =
8872 cpu_to_le16(ctxm->max_entries - ctxm->vnic_entries);
8873 req->vnic_entry_size = cpu_to_le16(ctxm->entry_size);
8874 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
8875 &req->vnic_pg_size_vnic_lvl,
8876 &req->vnic_page_dir);
8879 ctxm = &ctx->ctx_arr[BNXT_CTX_STAT];
8880 ctx_pg = ctxm->pg_info;
8881 req->stat_num_entries = cpu_to_le32(ctxm->max_entries);
8882 req->stat_entry_size = cpu_to_le16(ctxm->entry_size);
8883 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
8884 &req->stat_pg_size_stat_lvl,
8885 &req->stat_page_dir);
8890 ctxm = &ctx->ctx_arr[BNXT_CTX_MRAV];
8891 ctx_pg = ctxm->pg_info;
8892 req->mrav_num_entries = cpu_to_le32(ctx_pg->entries);
8893 units = ctxm->mrav_num_entries_units;
8895 u32 num_mr, num_ah = ctxm->mrav_av_entries;
8898 num_mr = ctx_pg->entries - num_ah;
8900 req->mrav_num_entries = cpu_to_le32(entries);
8903 req->mrav_entry_size = cpu_to_le16(ctxm->entry_size);
8904 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
8905 &req->mrav_pg_size_mrav_lvl,
8906 &req->mrav_page_dir);
8909 ctxm = &ctx->ctx_arr[BNXT_CTX_TIM];
8910 ctx_pg = ctxm->pg_info;
8911 req->tim_num_entries = cpu_to_le32(ctx_pg->entries);
8912 req->tim_entry_size = cpu_to_le16(ctxm->entry_size);
8913 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
8914 &req->tim_pg_size_tim_lvl,
8915 &req->tim_page_dir);
8917 ctxm = &ctx->ctx_arr[BNXT_CTX_STQM];
8918 for (i = 0, num_entries = &req->tqm_sp_num_entries,
8919 pg_attr = &req->tqm_sp_pg_size_tqm_sp_lvl,
8920 pg_dir = &req->tqm_sp_page_dir,
8922 ctx_pg = ctxm->pg_info;
8924 ctx_pg = &ctx->ctx_arr[BNXT_CTX_FTQM].pg_info[i],
8929 req->tqm_entry_size = cpu_to_le16(ctxm->entry_size);
8930 *num_entries = cpu_to_le32(ctx_pg->entries);
8931 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
8933 req->flags = cpu_to_le32(flags);
8940 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
8942 rmem->page_size = BNXT_PAGE_SIZE;
8943 rmem->pg_arr = ctx_pg->ctx_pg_arr;
8944 rmem->dma_arr = ctx_pg->ctx_dma_arr;
8945 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
8946 if (rmem->depth >= 1)
8947 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
8955 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
8959 return -EINVAL;
8961 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
8962 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
8963 ctx_pg->nr_pages = 0;
8964 return -EINVAL;
8966 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
8969 rmem->depth = 2;
8970 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
8972 if (!ctx_pg->ctx_pg_tbl)
8973 return -ENOMEM;
8974 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
8975 rmem->nr_pages = nr_tbls;
8984 return -ENOMEM;
8985 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
8986 rmem = &pg_tbl->ring_mem;
8987 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
8988 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
8989 rmem->depth = 1;
8990 rmem->nr_pages = MAX_CTX_PAGES;
8991 rmem->ctx_mem = ctxm;
8992 if (i == (nr_tbls - 1)) {
8993 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
8996 rmem->nr_pages = rem;
9003 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
9004 if (rmem->nr_pages > 1 || depth)
9005 rmem->depth = 1;
9006 rmem->ctx_mem = ctxm;
9017 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
9018 size_t nr_pages = ctx_pg->nr_pages;
9019 int page_size = rmem->page_size;
9021 u16 depth = rmem->depth;
9029 pg_tbl = ctx_pg->ctx_pg_tbl[i];
9030 rmem = &pg_tbl->ring_mem;
9045 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
9047 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
9048 ctx_pg->ctx_pg_tbl) {
9049 int i, nr_tbls = rmem->nr_pages;
9055 pg_tbl = ctx_pg->ctx_pg_tbl[i];
9058 rmem2 = &pg_tbl->ring_mem;
9060 ctx_pg->ctx_pg_arr[i] = NULL;
9062 ctx_pg->ctx_pg_tbl[i] = NULL;
9064 kfree(ctx_pg->ctx_pg_tbl);
9065 ctx_pg->ctx_pg_tbl = NULL;
9068 ctx_pg->nr_pages = 0;
9075 struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info;
9079 if (!ctxm->entry_size || !ctx_pg)
9080 return -EINVAL;
9081 if (ctxm->instance_bmap)
9082 n = hweight32(ctxm->instance_bmap);
9083 if (ctxm->entry_multiple)
9084 entries = roundup(entries, ctxm->entry_multiple);
9085 entries = clamp_t(u32, entries, ctxm->min_entries, ctxm->max_entries);
9086 mem_size = entries * ctxm->entry_size;
9090 ctxm->init_value ? ctxm : NULL);
9093 ctxm->mem_valid = 1;
9102 u32 instance_bmap = ctxm->instance_bmap;
9106 if (!(ctxm->flags & BNXT_CTX_MEM_TYPE_VALID) || !ctxm->pg_info)
9110 n = hweight32(ctxm->instance_bmap);
9118 req->type = cpu_to_le16(ctxm->type);
9119 req->entry_size = cpu_to_le16(ctxm->entry_size);
9120 if ((ctxm->flags & BNXT_CTX_MEM_PERSIST) &&
9121 bnxt_bs_trace_avail(bp, ctxm->type)) {
9126 req->enables = cpu_to_le32(enables);
9127 bs_trace = &bp->bs_trace[bnxt_bstore_to_trace[ctxm->type]];
9128 req->next_bs_offset = cpu_to_le32(bs_trace->last_offset);
9130 req->subtype_valid_cnt = ctxm->split_entry_cnt;
9131 for (i = 0, p = &req->split_entry_0; i < ctxm->split_entry_cnt; i++)
9132 p[i] = cpu_to_le32(ctxm->split[i]);
9138 req->instance = cpu_to_le16(i);
9139 ctx_pg = &ctxm->pg_info[j++];
9140 if (!ctx_pg->entries)
9142 req->num_entries = cpu_to_le32(ctx_pg->entries);
9143 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
9144 &req->page_size_pbl_level,
9145 &req->page_dir);
9147 req->flags =
9157 struct bnxt_ctx_mem_info *ctx = bp->ctx;
9164 ctxm = &ctx->ctx_arr[type];
9167 if (!ctxm->mem_valid) {
9169 ctxm->max_entries, 1);
9171 netdev_warn(bp->dev, "Unable to setup ctx page for type:0x%x.\n",
9182 ctxm = &ctx->ctx_arr[type];
9183 if (ctxm->mem_valid)
9189 ctx->ctx_arr[last_type].last = 1;
9192 ctxm = &ctx->ctx_arr[type];
9194 if (!ctxm->mem_valid)
9196 rc = bnxt_hwrm_func_backing_store_cfg_v2(bp, ctxm, ctxm->last);
9204 * __bnxt_copy_ctx_mem - copy host context memory
9221 struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info;
9228 if (ctxm->instance_bmap)
9229 n = hweight32(ctxm->instance_bmap);
9242 size_t tail = ctxm->max_entries * ctxm->entry_size;
9253 ctxm->last = 0;
9255 if (ctxm->mem_valid && !force && (ctxm->flags & BNXT_CTX_MEM_PERSIST))
9258 ctx_pg = ctxm->pg_info;
9260 if (ctxm->instance_bmap)
9261 n = hweight32(ctxm->instance_bmap);
9266 ctxm->pg_info = NULL;
9267 ctxm->mem_valid = 0;
9274 struct bnxt_ctx_mem_info *ctx = bp->ctx;
9281 bnxt_free_one_ctx_mem(bp, &ctx->ctx_arr[type], force);
9283 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
9286 bp->ctx = NULL;
9306 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
9310 ctx = bp->ctx;
9311 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
9315 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
9318 ctxm = &ctx->ctx_arr[BNXT_CTX_QP];
9319 l2_qps = ctxm->qp_l2_entries;
9320 qp1_qps = ctxm->qp_qp1_entries;
9321 fast_qpmd_qps = ctxm->qp_fast_qpmd_entries;
9322 max_qps = ctxm->max_entries;
9323 ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ];
9324 srqs = ctxm->srq_l2_entries;
9325 max_srqs = ctxm->max_entries;
9326 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
9329 extra_qps = max_qps - l2_qps - qp1_qps;
9330 extra_srqs = max_srqs - srqs;
9333 max_qps - l2_qps - qp1_qps);
9338 extra_srqs = min_t(u32, 8192, max_srqs - srqs);
9344 ctxm = &ctx->ctx_arr[BNXT_CTX_QP];
9350 ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ];
9355 ctxm = &ctx->ctx_arr[BNXT_CTX_CQ];
9356 rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, ctxm->cq_l2_entries +
9361 ctxm = &ctx->ctx_arr[BNXT_CTX_VNIC];
9362 rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, ctxm->max_entries, 1);
9366 ctxm = &ctx->ctx_arr[BNXT_CTX_STAT];
9367 rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, ctxm->max_entries, 1);
9371 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
9374 ctxm = &ctx->ctx_arr[BNXT_CTX_MRAV];
9376 ctxm->split_entry_cnt == BNXT_CTX_MRAV_AV_SPLIT_ENTRY + 1) {
9377 num_ah = ctxm->mrav_av_entries;
9378 num_mr = ctxm->max_entries - num_ah;
9383 num_mr = min_t(u32, ctxm->max_entries / 2, 1024 * 256);
9385 ctxm->split_entry_cnt = BNXT_CTX_MRAV_AV_SPLIT_ENTRY + 1;
9386 if (!ctxm->mrav_av_entries || ctxm->mrav_av_entries > num_ah)
9387 ctxm->mrav_av_entries = num_ah;
9395 ctxm = &ctx->ctx_arr[BNXT_CTX_TIM];
9402 ctxm = &ctx->ctx_arr[BNXT_CTX_STQM];
9403 min = ctxm->min_entries;
9404 entries_sp = ctx->ctx_arr[BNXT_CTX_VNIC].vnic_entries + l2_qps +
9410 ctxm = &ctx->ctx_arr[BNXT_CTX_FTQM];
9415 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
9420 if (bp->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2)
9425 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
9429 ctx->flags |= BNXT_CTX_FLAG_INITED;
9439 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR))
9452 req->pg_size_lvl = cpu_to_le16(page_attr |
9453 bp->fw_crash_mem->ring_mem.depth);
9454 req->pbl = cpu_to_le64(bp->fw_crash_mem->ring_mem.pg_tbl_map);
9455 req->size = cpu_to_le32(bp->fw_crash_len);
9456 req->output_dest_flags = cpu_to_le16(BNXT_DBG_CR_DUMP_MDM_CFG_DDR);
9462 if (bp->fw_crash_mem) {
9463 bnxt_free_ctx_pg_tbls(bp, bp->fw_crash_mem);
9464 kfree(bp->fw_crash_mem);
9465 bp->fw_crash_mem = NULL;
9474 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR))
9484 if (bp->fw_crash_mem &&
9485 mem_size <= bp->fw_crash_mem->nr_pages * BNXT_PAGE_SIZE)
9488 if (bp->fw_crash_mem)
9489 bnxt_free_ctx_pg_tbls(bp, bp->fw_crash_mem);
9491 bp->fw_crash_mem = kzalloc(sizeof(*bp->fw_crash_mem),
9493 if (!bp->fw_crash_mem)
9494 return -ENOMEM;
9496 rc = bnxt_alloc_ctx_pg_tbls(bp, bp->fw_crash_mem, mem_size, 1, NULL);
9503 bp->fw_crash_len = mem_size;
9511 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9518 req->fid = cpu_to_le16(0xffff);
9524 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
9528 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
9529 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
9530 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
9531 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
9532 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
9533 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
9534 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
9535 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
9536 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
9537 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
9538 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
9539 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
9540 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
9541 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
9542 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
9543 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
9545 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
9546 u16 max_msix = le16_to_cpu(resp->max_msix);
9548 hw_resc->max_nqs = max_msix;
9549 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
9553 struct bnxt_pf_info *pf = &bp->pf;
9555 pf->vf_resv_strategy =
9556 le16_to_cpu(resp->vf_reservation_strategy);
9557 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
9558 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
9569 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
9573 if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5_PLUS(bp)) {
9574 rc = -ENODEV;
9582 req->port_id = cpu_to_le16(bp->pf.port_id);
9588 flags = resp->flags;
9591 rc = -ENODEV;
9597 rc = -ENOMEM;
9600 ptp->bp = bp;
9601 bp->ptp_cfg = ptp;
9607 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
9608 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
9610 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
9611 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
9613 rc = -ENODEV;
9616 ptp->rtc_configured =
9620 netdev_warn(bp->dev, "PTP initialization failed.\n");
9629 bp->ptp_cfg = NULL;
9636 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9645 req->fid = cpu_to_le16(0xffff);
9651 flags = le32_to_cpu(resp->flags);
9653 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
9655 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
9657 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
9659 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
9661 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
9663 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
9665 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
9667 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
9669 bp->fw_cap |= BNXT_FW_CAP_DBG_QCAPS;
9671 flags_ext = le32_to_cpu(resp->flags_ext);
9673 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
9675 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS;
9677 bp->fw_cap |= BNXT_FW_CAP_PTP_RTC;
9679 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF;
9681 bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH;
9683 bp->fw_cap |= BNXT_FW_CAP_NPAR_1_2;
9685 bp->fw_cap |= BNXT_FW_CAP_DFLT_VLAN_TPID_PCP;
9687 bp->fw_cap |= BNXT_FW_CAP_BACKING_STORE_V2;
9689 bp->flags |= BNXT_FLAG_TX_COAL_CMPL;
9691 flags_ext2 = le32_to_cpu(resp->flags_ext2);
9693 bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS;
9695 bp->flags |= BNXT_FLAG_UDP_GSO_CAP;
9697 bp->fw_cap |= BNXT_FW_CAP_TX_TS_CMP;
9700 bp->fw_cap |= BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS;
9703 bp->fw_cap |= BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED;
9705 flags_ext3 = le32_to_cpu(resp->flags_ext3);
9707 bp->fw_cap |= BNXT_FW_CAP_ROCE_VF_DYN_ALLOC_SUPPORT;
9709 bp->fw_cap |= BNXT_FW_CAP_MIRROR_ON_ROCE;
9711 bp->tx_push_thresh = 0;
9714 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
9716 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
9717 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
9718 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
9719 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
9720 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
9721 if (!hw_resc->max_hw_ring_grps)
9722 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
9723 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
9724 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
9725 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
9727 hw_resc->max_encap_records = le32_to_cpu(resp->max_encap_records);
9728 hw_resc->max_decap_records = le32_to_cpu(resp->max_decap_records);
9729 hw_resc->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
9730 hw_resc->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
9731 hw_resc->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
9732 hw_resc->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
9735 struct bnxt_pf_info *pf = &bp->pf;
9737 pf->fw_fid = le16_to_cpu(resp->fid);
9738 pf->port_id = le16_to_cpu(resp->port_id);
9739 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
9740 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
9741 pf->max_vfs = le16_to_cpu(resp->max_vfs);
9742 bp->flags &= ~BNXT_FLAG_WOL_CAP;
9744 bp->flags |= BNXT_FLAG_WOL_CAP;
9746 bp->fw_cap |= BNXT_FW_CAP_PTP;
9749 kfree(bp->ptp_cfg);
9750 bp->ptp_cfg = NULL;
9754 struct bnxt_vf_info *vf = &bp->vf;
9756 vf->fw_fid = le16_to_cpu(resp->fid);
9757 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
9760 bp->tso_max_segs = le16_to_cpu(resp->max_tso_segs);
9773 bp->fw_dbg_cap = 0;
9774 if (!(bp->fw_cap & BNXT_FW_CAP_DBG_QCAPS))
9781 req->fid = cpu_to_le16(0xffff);
9787 bp->fw_dbg_cap = le32_to_cpu(resp->flags);
9807 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
9810 if (bp->hwrm_spec_code >= 0x10803) {
9816 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
9828 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
9840 flags = le32_to_cpu(resp->flags);
9843 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
9847 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3;
9851 bp->fw_cap |= BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO;
9860 if (bp->fw_health)
9863 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
9864 if (!bp->fw_health)
9865 return -ENOMEM;
9867 mutex_init(&bp->fw_health->lock);
9875 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
9876 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
9881 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
9882 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
9891 writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
9898 struct bnxt_fw_health *fw_health = bp->fw_health;
9904 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]);
9906 fw_health->status_reliable = false;
9908 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]);
9910 fw_health->resets_reliable = false;
9920 if (bp->fw_health)
9921 bp->fw_health->status_reliable = false;
9924 hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
9928 if (!bp->chip_num) {
9930 bp->chip_num = readl(bp->bar0 +
9945 netdev_warn(bp->dev, "no memory for firmware status checks\n");
9949 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
9953 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
9957 bp->fw_health->status_reliable = true;
9962 struct bnxt_fw_health *fw_health = bp->fw_health;
9966 bp->fw_health->status_reliable = false;
9967 bp->fw_health->resets_reliable = false;
9968 /* Only pre-map the monitoring GRC registers using window 3 */
9970 u32 reg = fw_health->regs[i];
9977 return -ERANGE;
9978 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
9980 bp->fw_health->status_reliable = true;
9981 bp->fw_health->resets_reliable = true;
9991 if (!bp->fw_health)
9994 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) {
9995 bp->fw_health->status_reliable = true;
9996 bp->fw_health->resets_reliable = true;
10004 struct bnxt_fw_health *fw_health = bp->fw_health;
10009 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
10020 fw_health->flags = le32_to_cpu(resp->flags);
10021 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
10022 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
10023 rc = -EINVAL;
10026 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
10027 fw_health->master_func_wait_dsecs =
10028 le32_to_cpu(resp->master_func_wait_period);
10029 fw_health->normal_func_wait_dsecs =
10030 le32_to_cpu(resp->normal_func_wait_period);
10031 fw_health->post_reset_wait_dsecs =
10032 le32_to_cpu(resp->master_func_wait_period_after_reset);
10033 fw_health->post_reset_max_wait_dsecs =
10034 le32_to_cpu(resp->max_bailout_time_after_reset);
10035 fw_health->regs[BNXT_FW_HEALTH_REG] =
10036 le32_to_cpu(resp->fw_health_status_reg);
10037 fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
10038 le32_to_cpu(resp->fw_heartbeat_reg);
10039 fw_health->regs[BNXT_FW_RESET_CNT_REG] =
10040 le32_to_cpu(resp->fw_reset_cnt_reg);
10041 fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
10042 le32_to_cpu(resp->reset_inprogress_reg);
10043 fw_health->fw_reset_inprog_reg_mask =
10044 le32_to_cpu(resp->reset_inprogress_reg_mask);
10045 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
10046 if (fw_health->fw_reset_seq_cnt >= 16) {
10047 rc = -EINVAL;
10050 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
10051 fw_health->fw_reset_seq_regs[i] =
10052 le32_to_cpu(resp->reset_reg[i]);
10053 fw_health->fw_reset_seq_vals[i] =
10054 le32_to_cpu(resp->reset_reg_val[i]);
10055 fw_health->fw_reset_seq_delay_msec[i] =
10056 resp->delay_after_reset[i];
10063 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
10076 req->enables = 0;
10086 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
10108 if (!resp->max_configurable_queues) {
10109 rc = -EINVAL;
10112 bp->max_tc = resp->max_configurable_queues;
10113 bp->max_lltc = resp->max_configurable_lossless_queues;
10114 if (bp->max_tc > BNXT_MAX_QUEUE)
10115 bp->max_tc = BNXT_MAX_QUEUE;
10117 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
10118 qptr = &resp->queue_id0;
10119 for (i = 0, j = 0; i < bp->max_tc; i++) {
10120 bp->q_info[j].queue_id = *qptr;
10121 bp->q_ids[i] = *qptr++;
10122 bp->q_info[j].queue_profile = *qptr++;
10123 bp->tc_to_qidx[j] = j;
10124 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
10128 bp->max_q = bp->max_tc;
10129 bp->max_tc = max_t(u8, j, 1);
10131 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
10132 bp->max_tc = 1;
10134 if (bp->max_lltc > bp->max_tc)
10135 bp->max_lltc = bp->max_tc;
10151 req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
10152 req->hwrm_intf_min = HWRM_VERSION_MINOR;
10153 req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
10173 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
10174 req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
10175 req->hwrm_intf_min = HWRM_VERSION_MINOR;
10176 req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
10183 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
10185 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
10186 resp->hwrm_intf_min_8b << 8 |
10187 resp->hwrm_intf_upd_8b;
10188 if (resp->hwrm_intf_maj_8b < 1) {
10189 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
10190 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
10191 resp->hwrm_intf_upd_8b);
10192 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
10198 if (bp->hwrm_spec_code > hwrm_ver)
10199 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
10203 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
10204 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
10205 resp->hwrm_intf_upd_8b);
10207 fw_maj = le16_to_cpu(resp->hwrm_fw_major);
10208 if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
10209 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
10210 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
10211 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
10214 fw_maj = resp->hwrm_fw_maj_8b;
10215 fw_min = resp->hwrm_fw_min_8b;
10216 fw_bld = resp->hwrm_fw_bld_8b;
10217 fw_rsv = resp->hwrm_fw_rsvd_8b;
10220 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
10221 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
10224 if (strlen(resp->active_pkg_name)) {
10225 int fw_ver_len = strlen(bp->fw_ver_str);
10227 snprintf(bp->fw_ver_str + fw_ver_len,
10228 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
10229 resp->active_pkg_name);
10230 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
10233 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
10234 if (!bp->hwrm_cmd_timeout)
10235 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
10236 bp->hwrm_cmd_max_timeout = le16_to_cpu(resp->max_req_timeout) * 1000;
10237 if (!bp->hwrm_cmd_max_timeout)
10238 bp->hwrm_cmd_max_timeout = HWRM_CMD_MAX_TIMEOUT;
10239 max_tmo_secs = bp->hwrm_cmd_max_timeout / 1000;
10241 if (bp->hwrm_cmd_max_timeout > HWRM_CMD_MAX_TIMEOUT ||
10243 netdev_warn(bp->dev, "Device requests max timeout of %d seconds, may trigger hung task watchdog (kernel default %ds)\n",
10248 if (resp->hwrm_intf_maj_8b >= 1) {
10249 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
10250 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
10252 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
10253 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
10255 bp->chip_num = le16_to_cpu(resp->chip_num);
10256 bp->chip_rev = resp->chip_rev;
10257 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
10258 !resp->chip_metal)
10259 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
10261 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
10264 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
10267 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
10271 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
10275 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
10279 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
10293 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
10294 bp->hwrm_spec_code < 0x10400)
10295 return -EOPNOTSUPP;
10302 req->year = cpu_to_le16(1900 + tm.tm_year);
10303 req->month = 1 + tm.tm_mon;
10304 req->day = tm.tm_mday;
10305 req->hour = tm.tm_hour;
10306 req->minute = tm.tm_min;
10307 req->second = tm.tm_sec;
10333 if (masks[i] == -1ULL)
10342 if (!stats->hw_stats)
10345 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
10346 stats->hw_masks, stats->len / 8, false);
10356 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
10359 for (i = 0; i < bp->cp_nr_rings; i++) {
10360 struct bnxt_napi *bnapi = bp->bnapi[i];
10364 cpr = &bnapi->cp_ring;
10365 stats = &cpr->stats;
10368 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
10369 ring0_stats->hw_masks,
10370 ring0_stats->len / 8, ignore_zero);
10372 if (bp->flags & BNXT_FLAG_PORT_STATS) {
10373 struct bnxt_stats_mem *stats = &bp->port_stats;
10374 __le64 *hw_stats = stats->hw_stats;
10375 u64 *sw_stats = stats->sw_stats;
10376 u64 *masks = stats->hw_masks;
10388 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
10389 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
10390 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
10397 struct bnxt_pf_info *pf = &bp->pf;
10400 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
10403 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
10404 return -EOPNOTSUPP;
10410 req->flags = flags;
10411 req->port_id = cpu_to_le16(pf->port_id);
10412 req->tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
10414 req->rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
10424 struct bnxt_pf_info *pf = &bp->pf;
10428 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
10431 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
10432 return -EOPNOTSUPP;
10438 req_qs->flags = flags;
10439 req_qs->port_id = cpu_to_le16(pf->port_id);
10440 req_qs->rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
10441 req_qs->rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
10442 tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
10444 req_qs->tx_stat_size = cpu_to_le16(tx_stat_size);
10445 req_qs->tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
10449 bp->fw_rx_stats_ext_size =
10450 le16_to_cpu(resp_qs->rx_stat_size) / 8;
10452 bp->fw_rx_stats_ext_size > BNXT_RX_STATS_EXT_NUM_LEGACY)
10453 bp->fw_rx_stats_ext_size = BNXT_RX_STATS_EXT_NUM_LEGACY;
10455 bp->fw_tx_stats_ext_size = tx_stat_size ?
10456 le16_to_cpu(resp_qs->tx_stat_size) / 8 : 0;
10458 bp->fw_rx_stats_ext_size = 0;
10459 bp->fw_tx_stats_ext_size = 0;
10466 if (bp->fw_tx_stats_ext_size <=
10468 bp->pri2cos_valid = 0;
10476 req_qc->flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
10484 pri2cos = &resp_qc->pri0_cos_queue_id;
10492 bp->pri2cos_valid = false;
10496 for (j = 0; j < bp->max_q; j++) {
10497 if (bp->q_ids[j] == queue_id)
10498 bp->pri2cos_idx[i] = queue_idx;
10501 bp->pri2cos_valid = true;
10522 tpa_flags = bp->flags & BNXT_FLAG_TPA;
10525 for (i = 0; i < bp->nr_vnics; i++) {
10526 rc = bnxt_hwrm_vnic_set_tpa(bp, &bp->vnic_info[i], tpa_flags);
10528 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
10540 for (i = 0; i < bp->nr_vnics; i++)
10541 bnxt_hwrm_vnic_set_rss(bp, &bp->vnic_info[i], false);
10546 if (!bp->vnic_info)
10550 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS)) {
10556 if (bp->flags & BNXT_FLAG_TPA)
10559 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
10586 return -EINVAL;
10592 req->fid = cpu_to_le16(0xffff);
10593 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
10594 req->evb_mode = evb_mode;
10603 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
10610 req->fid = cpu_to_le16(0xffff);
10611 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
10612 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
10614 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
10623 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
10629 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
10630 vnic->vnic_id, rc);
10633 bp->rsscos_nr_ctxs++;
10638 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
10639 vnic->vnic_id, rc);
10642 bp->rsscos_nr_ctxs++;
10649 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
10650 vnic->vnic_id, rc);
10657 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
10658 vnic->vnic_id, rc);
10662 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
10665 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
10666 vnic->vnic_id, rc);
10684 req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
10687 req->mru = cpu_to_le16(vnic->mru);
10689 req->enables = cpu_to_le32(valid);
10700 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
10701 vnic->vnic_id, rc);
10706 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
10707 vnic->vnic_id, rc);
10715 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
10719 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
10720 vnic->vnic_id, i, rc);
10723 bp->rsscos_nr_ctxs++;
10726 return -ENOMEM;
10732 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
10735 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
10736 vnic->vnic_id, rc);
10744 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
10758 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
10759 vnic->vnic_id, rc);
10771 vnic = &bp->vnic_info[BNXT_VNIC_NTUPLE];
10772 return bnxt_alloc_and_setup_vnic(bp, vnic, 0, bp->rx_nr_rings);
10775 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
10778 for (i = 0; i < bp->rx_nr_rings; i++) {
10782 if (vnic_id >= bp->nr_vnics)
10785 vnic = &bp->vnic_info[vnic_id];
10786 vnic->flags |= BNXT_VNIC_RFS_FLAG;
10787 if (bp->rss_cap & BNXT_RSS_CAP_NEW_RSS_CAP)
10788 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
10789 if (bnxt_alloc_and_setup_vnic(bp, &bp->vnic_info[vnic_id], ring_id, 1))
10798 struct bnxt_vnic_info *vnic = &rss_ctx->vnic;
10803 if (netif_running(bp->dev)) {
10804 bnxt_hwrm_vnic_free_one(bp, &rss_ctx->vnic);
10806 if (vnic->fw_rss_cos_lb_ctx[i] != INVALID_HW_RING_ID)
10813 list_for_each_entry_safe(usr_fltr, tmp, &bp->usr_fltr_list, list) {
10814 if ((usr_fltr->flags & BNXT_ACT_RSS_CTX) &&
10815 usr_fltr->fw_vnic_id == rss_ctx->index) {
10825 if (vnic->rss_table)
10826 dma_free_coherent(&bp->pdev->dev, vnic->rss_table_size,
10827 vnic->rss_table,
10828 vnic->rss_table_dma_addr);
10829 bp->num_rss_ctx--;
10835 u16 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
10841 if (vnic->flags & BNXT_VNIC_NTUPLE_FLAG)
10845 if (vnic->flags & BNXT_VNIC_RSSCTX_FLAG)
10846 vnic_rx = ethtool_rxfh_context_indir(vnic->rss_ctx)[i];
10848 vnic_rx = bp->rss_indir_tbl[i];
10868 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
10869 vnic->vnic_id, rc);
10873 vnic->mru = mru;
10886 xa_for_each(&bp->dev->ethtool->rss_ctx, context, ctx) {
10888 struct bnxt_vnic_info *vnic = &rss_ctx->vnic;
10900 bool set_tpa = !!(bp->flags & BNXT_FLAG_TPA);
10904 xa_for_each(&bp->dev->ethtool->rss_ctx, context, ctx) {
10906 struct bnxt_vnic_info *vnic = &rss_ctx->vnic;
10908 if (bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings) ||
10911 netdev_err(bp->dev, "Failed to restore RSS ctx %d\n",
10912 rss_ctx->index);
10914 ethtool_rxfh_context_lost(bp->dev, rss_ctx->index);
10924 xa_for_each(&bp->dev->ethtool->rss_ctx, context, ctx) {
10935 if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf))
10943 struct bnxt_vnic_info *vnic = &bp->vnic_info[1];
10946 rc = bnxt_hwrm_vnic_alloc(bp, vnic, bp->rx_nr_rings - 1, 1);
10948 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
10955 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
10967 struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
10969 unsigned int rx_nr_rings = bp->rx_nr_rings;
10974 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
10982 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
10988 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
10993 rx_nr_rings--;
10998 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
11008 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)
11011 if (bp->flags & BNXT_FLAG_RFS) {
11017 if (bp->flags & BNXT_FLAG_TPA) {
11027 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
11029 if (BNXT_VF(bp) && rc == -ENODEV)
11030 netdev_err(bp->dev, "Cannot configure L2 filter while PF is unavailable\n");
11032 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
11035 vnic->uc_filter_count = 1;
11037 vnic->rx_mask = 0;
11038 if (test_bit(BNXT_STATE_HALF_OPEN, &bp->state))
11041 if (bp->dev->flags & IFF_BROADCAST)
11042 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
11044 if (bp->dev->flags & IFF_PROMISC)
11045 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11047 if (bp->dev->flags & IFF_ALLMULTI) {
11048 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
11049 vnic->mc_list_count = 0;
11050 } else if (bp->dev->flags & IFF_MULTICAST) {
11054 vnic->rx_mask |= mask;
11064 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
11070 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
11076 netdev_update_features(bp->dev);
11107 struct net_device *dev = bp->dev;
11109 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
11110 bp->tx_nr_rings_xdp);
11114 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
11119 if (bp->flags & BNXT_FLAG_RFS)
11120 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
11136 return -ENOMEM;
11140 _rx--;
11142 _tx--;
11152 return (tx - tx_xdp) / tx_sets + tx_xdp;
11157 int tcs = bp->num_tc;
11161 return __bnxt_num_tx_to_cp(bp, tx, tcs, bp->tx_nr_rings_xdp);
11166 int tcs = bp->num_tc;
11168 return (tx_cp - bp->tx_nr_rings_xdp) * tcs +
11169 bp->tx_nr_rings_xdp;
11192 const int len = sizeof(bp->irq_tbl[0].name);
11193 struct net_device *dev = bp->dev;
11196 tcs = bp->num_tc;
11201 count = bp->tx_nr_rings_per_tc;
11207 for (i = 0; i < bp->cp_nr_rings; i++) {
11211 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
11213 else if (i < bp->rx_nr_rings)
11218 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
11220 bp->irq_tbl[map_idx].handler = bnxt_msix;
11232 for (i = bp->total_irqs; i < total; i++) {
11233 map = pci_msix_alloc_irq_at(bp->pdev, i, NULL);
11235 return bp->total_irqs;
11236 bp->irq_tbl[i].vector = map.virq;
11237 bp->total_irqs++;
11241 for (i = bp->total_irqs; i > total; i--) {
11242 map.index = i - 1;
11243 map.virq = bp->irq_tbl[i - 1].vector;
11244 pci_msix_free_irq(bp->pdev, map);
11245 bp->total_irqs--;
11247 return bp->total_irqs;
11254 if (!bp->irq_tbl) {
11256 if (rc || !bp->irq_tbl)
11257 return rc ?: -ENODEV;
11268 return bp->hw_resc.max_rsscos_ctxs;
11273 return bp->hw_resc.max_vnics;
11278 return bp->hw_resc.max_stat_ctxs;
11283 return bp->hw_resc.max_cp_rings;
11288 unsigned int cp = bp->hw_resc.max_cp_rings;
11290 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
11291 cp -= bnxt_get_ulp_msix_num(bp);
11298 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
11300 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
11301 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
11303 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
11308 bp->hw_resc.max_irqs = max_irqs;
11316 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
11317 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
11319 return cp - bp->cp_nr_rings;
11324 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
11330 int total_req = bp->cp_nr_rings + num;
11333 num = max_irq - bp->cp_nr_rings;
11360 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
11363 total_vecs = pci_alloc_irq_vectors(bp->pdev, min, total_vecs,
11367 rc = -ENODEV;
11372 if (pci_msix_can_alloc_dyn(bp->pdev))
11374 bp->irq_tbl = kcalloc(tbl_size, sizeof(*bp->irq_tbl), GFP_KERNEL);
11375 if (bp->irq_tbl) {
11377 bp->irq_tbl[i].vector = pci_irq_vector(bp->pdev, i);
11379 bp->total_irqs = total_vecs;
11381 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
11382 total_vecs - ulp_msix, min == 1);
11386 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings);
11387 bp->cp_nr_rings = (min == 1) ?
11388 max_t(int, tx_cp, bp->rx_nr_rings) :
11389 tx_cp + bp->rx_nr_rings;
11392 rc = -ENOMEM;
11398 netdev_err(bp->dev, "bnxt_init_int_mode err: %x\n", rc);
11399 kfree(bp->irq_tbl);
11400 bp->irq_tbl = NULL;
11401 pci_free_irq_vectors(bp->pdev);
11407 pci_free_irq_vectors(bp->pdev);
11409 kfree(bp->irq_tbl);
11410 bp->irq_tbl = NULL;
11417 int tcs = bp->num_tc;
11424 if (BNXT_NEW_RM(bp) && !bnxt_ulp_registered(bp->edev)) {
11425 int ulp_msix = bnxt_get_avail_msix(bp, bp->ulp_num_msix_want);
11427 if (ulp_msix > bp->ulp_num_msix_want)
11428 ulp_msix = bp->ulp_num_msix_want;
11429 irqs_required = ulp_msix + bp->cp_nr_rings;
11434 if (irq_re_init && BNXT_NEW_RM(bp) && irqs_required != bp->total_irqs) {
11436 if (!pci_msix_can_alloc_dyn(bp->pdev)) {
11449 rc = -ENOSPC;
11452 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
11455 if (tcs && (bp->tx_nr_rings_per_tc * tcs !=
11456 bp->tx_nr_rings - bp->tx_nr_rings_xdp)) {
11457 netdev_err(bp->dev, "tx ring reservation failure\n");
11458 netdev_reset_tc(bp->dev);
11459 bp->num_tc = 0;
11460 if (bp->tx_nr_rings_xdp)
11461 bp->tx_nr_rings_per_tc = bp->tx_nr_rings_xdp;
11463 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
11464 return -ENOMEM;
11476 bnapi = bp->bnapi[idx];
11478 WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
11481 if (!(bnapi->flags & BNXT_NAPI_FLAG_XDP)) {
11482 txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
11490 if (!bp->tph_mode)
11494 bnxt_hwrm_cp_ring_free(bp, txr->tx_cpr);
11495 bnxt_free_one_tx_ring_skbs(bp, txr, txr->txq_index);
11496 bnxt_clear_one_cp_ring(bp, txr->tx_cpr);
11507 bnapi = bp->bnapi[idx];
11512 if (!bp->tph_mode)
11515 rc = bnxt_hwrm_cp_ring_alloc_p5(bp, txr->tx_cpr);
11523 txr->tx_prod = 0;
11524 txr->tx_cons = 0;
11525 txr->tx_hw_cons = 0;
11527 WRITE_ONCE(txr->dev_state, 0);
11530 if (bnapi->flags & BNXT_NAPI_FLAG_XDP)
11533 txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
11550 if (!irq->bp->tph_mode)
11553 cpumask_copy(irq->cpu_mask, mask);
11555 if (irq->ring_nr >= irq->bp->rx_nr_rings)
11558 if (pcie_tph_get_cpu_st(irq->bp->pdev, TPH_MEM_TYPE_VM,
11559 cpumask_first(irq->cpu_mask), &tag))
11562 if (pcie_tph_set_st_entry(irq->bp->pdev, irq->msix_nr, tag))
11565 netdev_lock(irq->bp->dev);
11566 if (netif_running(irq->bp->dev)) {
11567 err = netdev_rx_queue_restart(irq->bp->dev, irq->ring_nr);
11569 netdev_err(irq->bp->dev,
11572 netdev_unlock(irq->bp->dev);
11583 if (!irq->bp->tph_mode)
11586 if (pcie_tph_set_st_entry(irq->bp->pdev, irq->msix_nr, 0)) {
11587 netdev_err(irq->bp->dev,
11589 irq->msix_nr);
11596 irq_set_affinity_notifier(irq->vector, NULL);
11603 irq->bp = bp;
11606 if (!bp->tph_mode)
11610 notify = &irq->affinity_notify;
11611 notify->irq = irq->vector;
11612 notify->notify = bnxt_irq_affinity_notify;
11613 notify->release = bnxt_irq_affinity_release;
11615 irq_set_affinity_notifier(irq->vector, notify);
11624 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
11625 bp->dev->rx_cpu_rmap = NULL;
11627 if (!bp->irq_tbl || !bp->bnapi)
11630 for (i = 0; i < bp->cp_nr_rings; i++) {
11633 irq = &bp->irq_tbl[map_idx];
11634 if (irq->requested) {
11635 if (irq->have_cpumask) {
11636 irq_update_affinity_hint(irq->vector, NULL);
11637 free_cpumask_var(irq->cpu_mask);
11638 irq->have_cpumask = 0;
11643 free_irq(irq->vector, bp->bnapi[i]);
11646 irq->requested = 0;
11650 pcie_disable_tph(bp->pdev);
11651 bp->tph_mode = 0;
11662 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
11667 rmap = bp->dev->rx_cpu_rmap;
11671 rc = pcie_enable_tph(bp->pdev, PCI_TPH_ST_IV_MODE);
11673 bp->tph_mode = PCI_TPH_ST_IV_MODE;
11675 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
11677 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
11680 rmap && bp->bnapi[i]->rx_ring) {
11681 rc = irq_cpu_rmap_add(rmap, irq->vector);
11683 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
11688 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
11689 bp->bnapi[i]);
11693 netif_napi_set_irq_locked(&bp->bnapi[i]->napi, irq->vector);
11694 irq->requested = 1;
11696 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
11697 int numa_node = dev_to_node(&bp->pdev->dev);
11700 irq->have_cpumask = 1;
11701 irq->msix_nr = map_idx;
11702 irq->ring_nr = i;
11704 irq->cpu_mask);
11705 rc = irq_update_affinity_hint(irq->vector, irq->cpu_mask);
11707 netdev_warn(bp->dev,
11709 irq->vector);
11716 if (pcie_tph_get_cpu_st(irq->bp->pdev, TPH_MEM_TYPE_VM,
11717 cpumask_first(irq->cpu_mask),
11721 pcie_tph_set_st_entry(irq->bp->pdev, irq->msix_nr, tag);
11731 if (!bp->bnapi)
11734 for (i = 0; i < bp->rx_nr_rings; i++)
11735 netif_queue_set_napi(bp->dev, i, NETDEV_QUEUE_TYPE_RX, NULL);
11736 for (i = 0; i < bp->tx_nr_rings - bp->tx_nr_rings_xdp; i++)
11737 netif_queue_set_napi(bp->dev, i, NETDEV_QUEUE_TYPE_TX, NULL);
11739 for (i = 0; i < bp->cp_nr_rings; i++) {
11740 struct bnxt_napi *bnapi = bp->bnapi[i];
11742 __netif_napi_del_locked(&bnapi->napi);
11753 unsigned int cp_nr_rings = bp->cp_nr_rings;
11757 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
11760 cp_nr_rings--;
11762 set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
11765 bnapi = bp->bnapi[i];
11766 netif_napi_add_config_locked(bp->dev, &bnapi->napi, poll_fn,
11767 bnapi->index);
11770 bnapi = bp->bnapi[cp_nr_rings];
11771 netif_napi_add_locked(bp->dev, &bnapi->napi, bnxt_poll_nitroa0);
11779 if (!bp->bnapi ||
11780 test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
11783 for (i = 0; i < bp->cp_nr_rings; i++) {
11784 struct bnxt_napi *bnapi = bp->bnapi[i];
11787 cpr = &bnapi->cp_ring;
11788 if (bnapi->tx_fault)
11789 cpr->sw_stats->tx.tx_resets++;
11790 if (bnapi->in_reset)
11791 cpr->sw_stats->rx.rx_resets++;
11792 napi_disable_locked(&bnapi->napi);
11800 clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
11801 for (i = 0; i < bp->cp_nr_rings; i++) {
11802 struct bnxt_napi *bnapi = bp->bnapi[i];
11805 bnapi->tx_fault = 0;
11807 cpr = &bnapi->cp_ring;
11808 bnapi->in_reset = false;
11810 if (bnapi->rx_ring) {
11811 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
11812 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
11814 napi_enable_locked(&bnapi->napi);
11823 if (bp->tx_ring) {
11824 for (i = 0; i < bp->tx_nr_rings; i++) {
11825 txr = &bp->tx_ring[i];
11826 WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
11832 netif_carrier_off(bp->dev);
11834 netif_tx_disable(bp->dev);
11842 for (i = 0; i < bp->tx_nr_rings; i++) {
11843 txr = &bp->tx_ring[i];
11844 WRITE_ONCE(txr->dev_state, 0);
11848 netif_tx_wake_all_queues(bp->dev);
11850 netif_carrier_on(bp->dev);
11855 u8 active_fec = link_info->active_fec_sig_mode &
11886 netif_carrier_on(bp->dev);
11887 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
11889 netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
11892 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
11896 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
11897 flow_ctrl = "ON - receive & transmit";
11898 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
11899 flow_ctrl = "ON - transmit";
11900 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
11901 flow_ctrl = "ON - receive";
11904 if (bp->link_info.phy_qcfg_resp.option_flags &
11906 u8 sig_mode = bp->link_info.active_fec_sig_mode &
11922 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n",
11924 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP)
11925 netdev_info(bp->dev, "EEE is %s\n",
11926 bp->eee.eee_active ? "active" :
11928 fec = bp->link_info.fec_cfg;
11930 netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
11932 bnxt_report_fec(&bp->link_info));
11934 netif_carrier_off(bp->dev);
11935 netdev_err(bp->dev, "NIC Link is Down\n");
11941 if (!resp->supported_speeds_auto_mode &&
11942 !resp->supported_speeds_force_mode &&
11943 !resp->supported_pam4_speeds_auto_mode &&
11944 !resp->supported_pam4_speeds_force_mode &&
11945 !resp->supported_speeds2_auto_mode &&
11946 !resp->supported_speeds2_force_mode)
11953 struct bnxt_link_info *link_info = &bp->link_info;
11958 if (bp->hwrm_spec_code < 0x10201)
11970 bp->phy_flags = resp->flags | (le16_to_cpu(resp->flags2) << 8);
11971 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
11972 struct ethtool_keee *eee = &bp->eee;
11973 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
11975 _bnxt_fw_to_linkmode(eee->supported, fw_speeds);
11976 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
11978 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
11982 if (bp->hwrm_spec_code >= 0x10a01) {
11984 link_info->phy_state = BNXT_PHY_STATE_DISABLED;
11985 netdev_warn(bp->dev, "Ethernet link disabled\n");
11986 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
11987 link_info->phy_state = BNXT_PHY_STATE_ENABLED;
11988 netdev_info(bp->dev, "Ethernet link enabled\n");
11989 /* Phy re-enabled, reprobe the speeds */
11990 link_info->support_auto_speeds = 0;
11991 link_info->support_pam4_auto_speeds = 0;
11992 link_info->support_auto_speeds2 = 0;
11995 if (resp->supported_speeds_auto_mode)
11996 link_info->support_auto_speeds =
11997 le16_to_cpu(resp->supported_speeds_auto_mode);
11998 if (resp->supported_pam4_speeds_auto_mode)
11999 link_info->support_pam4_auto_speeds =
12000 le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
12001 if (resp->supported_speeds2_auto_mode)
12002 link_info->support_auto_speeds2 =
12003 le16_to_cpu(resp->supported_speeds2_auto_mode);
12005 bp->port_count = resp->port_cnt;
12018 if (bp->hwrm_spec_code < 0x10a03)
12028 bp->mac_flags = resp->flags;
12046 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
12047 if (bnxt_support_dropped(link_info->advertising,
12048 link_info->support_auto_speeds2)) {
12049 link_info->advertising = link_info->support_auto_speeds2;
12054 if (bnxt_support_dropped(link_info->advertising,
12055 link_info->support_auto_speeds)) {
12056 link_info->advertising = link_info->support_auto_speeds;
12059 if (bnxt_support_dropped(link_info->advertising_pam4,
12060 link_info->support_pam4_auto_speeds)) {
12061 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
12069 struct bnxt_link_info *link_info = &bp->link_info;
12072 u8 link_state = link_info->link_state;
12084 if (BNXT_VF(bp) && rc == -ENODEV) {
12085 netdev_warn(bp->dev, "Cannot obtain link state while PF unavailable.\n");
12091 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
12092 link_info->phy_link_status = resp->link;
12093 link_info->duplex = resp->duplex_cfg;
12094 if (bp->hwrm_spec_code >= 0x10800)
12095 link_info->duplex = resp->duplex_state;
12096 link_info->pause = resp->pause;
12097 link_info->auto_mode = resp->auto_mode;
12098 link_info->auto_pause_setting = resp->auto_pause;
12099 link_info->lp_pause = resp->link_partner_adv_pause;
12100 link_info->force_pause_setting = resp->force_pause;
12101 link_info->duplex_setting = resp->duplex_cfg;
12102 if (link_info->phy_link_status == BNXT_LINK_LINK) {
12103 link_info->link_speed = le16_to_cpu(resp->link_speed);
12104 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2)
12105 link_info->active_lanes = resp->active_lanes;
12107 link_info->link_speed = 0;
12108 link_info->active_lanes = 0;
12110 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
12111 link_info->force_pam4_link_speed =
12112 le16_to_cpu(resp->force_pam4_link_speed);
12113 link_info->force_link_speed2 = le16_to_cpu(resp->force_link_speeds2);
12114 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
12115 link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
12116 link_info->support_speeds2 = le16_to_cpu(resp->support_speeds2);
12117 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
12118 link_info->auto_pam4_link_speeds =
12119 le16_to_cpu(resp->auto_pam4_link_speed_mask);
12120 link_info->auto_link_speeds2 = le16_to_cpu(resp->auto_link_speeds2);
12121 link_info->lp_auto_link_speeds =
12122 le16_to_cpu(resp->link_partner_adv_speeds);
12123 link_info->lp_auto_pam4_link_speeds =
12124 resp->link_partner_pam4_adv_speeds;
12125 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
12126 link_info->phy_ver[0] = resp->phy_maj;
12127 link_info->phy_ver[1] = resp->phy_min;
12128 link_info->phy_ver[2] = resp->phy_bld;
12129 link_info->media_type = resp->media_type;
12130 link_info->phy_type = resp->phy_type;
12131 link_info->transceiver = resp->xcvr_pkg_type;
12132 link_info->phy_addr = resp->eee_config_phy_addr &
12134 link_info->module_status = resp->module_status;
12136 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) {
12137 struct ethtool_keee *eee = &bp->eee;
12140 eee->eee_active = 0;
12141 if (resp->eee_config_phy_addr &
12143 eee->eee_active = 1;
12145 resp->link_partner_adv_eee_link_speed_mask);
12146 _bnxt_fw_to_linkmode(eee->lp_advertised, fw_speeds);
12151 if (resp->eee_config_phy_addr &
12153 eee->eee_enabled = 1;
12155 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
12156 _bnxt_fw_to_linkmode(eee->advertised, fw_speeds);
12158 if (resp->eee_config_phy_addr &
12162 eee->tx_lpi_enabled = 1;
12163 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
12164 eee->tx_lpi_timer = le32_to_cpu(tmr) &
12170 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
12171 if (bp->hwrm_spec_code >= 0x10504) {
12172 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
12173 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
12177 if (link_info->phy_link_status == BNXT_LINK_LINK)
12178 link_info->link_state = BNXT_LINK_STATE_UP;
12180 link_info->link_state = BNXT_LINK_STATE_DOWN;
12181 if (link_state != link_info->link_state)
12185 link_info->link_state = BNXT_LINK_STATE_DOWN;
12193 if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
12200 struct bnxt_link_info *link_info = &bp->link_info;
12201 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
12207 module_status = link_info->module_status;
12212 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
12213 bp->pf.port_id);
12214 if (bp->hwrm_spec_code >= 0x10201) {
12215 netdev_warn(bp->dev, "Module part number %s\n",
12216 resp->phy_vendor_partnumber);
12219 netdev_warn(bp->dev, "TX is disabled\n");
12221 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
12228 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
12229 if (bp->hwrm_spec_code >= 0x10201)
12230 req->auto_pause =
12232 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
12233 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
12234 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
12235 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
12236 req->enables |=
12239 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
12240 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
12241 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
12242 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
12243 req->enables |=
12245 if (bp->hwrm_spec_code >= 0x10201) {
12246 req->auto_pause = req->force_pause;
12247 req->enables |= cpu_to_le32(
12255 if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
12256 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
12257 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
12258 req->enables |=
12260 req->auto_link_speeds2_mask = cpu_to_le16(bp->link_info.advertising);
12261 } else if (bp->link_info.advertising) {
12262 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
12263 req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
12265 if (bp->link_info.advertising_pam4) {
12266 req->enables |=
12268 req->auto_link_pam4_speed_mask =
12269 cpu_to_le16(bp->link_info.advertising_pam4);
12271 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
12272 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
12274 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
12275 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
12276 req->force_link_speeds2 = cpu_to_le16(bp->link_info.req_link_speed);
12277 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2);
12278 netif_info(bp, link, bp->dev, "Forcing FW speed2: %d\n",
12279 (u32)bp->link_info.req_link_speed);
12280 } else if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
12281 req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
12282 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
12284 req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
12289 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
12303 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
12304 bp->link_info.force_link_chng)
12308 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
12313 bp->link_info.pause =
12314 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
12315 bp->link_info.auto_pause_setting = 0;
12316 if (!bp->link_info.force_link_chng)
12319 bp->link_info.force_link_chng = false;
12326 struct ethtool_keee *eee = &bp->eee;
12328 if (eee->eee_enabled) {
12332 if (eee->tx_lpi_enabled)
12337 req->flags |= cpu_to_le32(flags);
12338 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
12339 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
12340 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
12342 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
12373 if (pci_num_vf(bp->pdev) &&
12374 !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN))
12381 req->flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
12384 mutex_lock(&bp->link_lock);
12390 bp->link_info.link_state = BNXT_LINK_STATE_UNKNOWN;
12391 mutex_unlock(&bp->link_lock);
12402 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
12406 netdev_err(bp->dev, "OP-TEE not supported\n");
12407 return -ENODEV;
12413 if (bp->fw_health && bp->fw_health->status_reliable) {
12424 } while (rc == -EBUSY && retry < BNXT_FW_RETRY);
12427 netdev_err(bp->dev,
12430 rc = -ENODEV;
12433 netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
12439 return -ENODEV;
12444 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
12449 hw_resc->resv_cp_rings = 0;
12450 hw_resc->resv_stat_ctxs = 0;
12451 hw_resc->resv_irqs = 0;
12452 hw_resc->resv_tx_rings = 0;
12453 hw_resc->resv_rx_rings = 0;
12454 hw_resc->resv_hw_ring_grps = 0;
12455 hw_resc->resv_vnics = 0;
12456 hw_resc->resv_rsscos_ctxs = 0;
12458 bp->tx_nr_rings = 0;
12459 bp->rx_nr_rings = 0;
12472 netdev_err(bp->dev, "resc_qcaps failed\n");
12489 fw_reset = (bp->fw_reset_state == BNXT_FW_RESET_STATE_ABORT);
12490 bp->fw_reset_state = 0;
12492 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
12500 req->flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
12506 if (rc != -EAGAIN)
12513 if (rc == -EAGAIN) {
12517 flags = le32_to_cpu(resp->flags);
12534 test_bit(BNXT_STATE_FW_RESET_DET, &bp->state))
12539 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
12540 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
12541 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
12542 return -ENODEV;
12549 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
12550 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
12556 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
12557 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
12572 struct bnxt_pf_info *pf = &bp->pf;
12575 bp->num_leds = 0;
12576 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
12583 req->port_id = cpu_to_le16(pf->port_id);
12590 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
12593 bp->num_leds = resp->num_leds;
12594 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
12595 bp->num_leds);
12596 for (i = 0; i < bp->num_leds; i++) {
12597 struct bnxt_led_info *led = &bp->leds[i];
12598 __le16 caps = led->led_state_caps;
12600 if (!led->led_group_id ||
12602 bp->num_leds = 0;
12621 req->port_id = cpu_to_le16(bp->pf.port_id);
12622 req->wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
12623 req->enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
12624 memcpy(req->mac_address, bp->dev->dev_addr, ETH_ALEN);
12629 bp->wol_filter_id = resp->wol_filter_id;
12643 req->port_id = cpu_to_le16(bp->pf.port_id);
12644 req->enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
12645 req->wol_filter_id = bp->wol_filter_id;
12661 req->port_id = cpu_to_le16(bp->pf.port_id);
12662 req->handle = cpu_to_le16(handle);
12666 next_handle = le16_to_cpu(resp->next_handle);
12668 if (resp->wol_type ==
12670 bp->wol = 1;
12671 bp->wol_filter_id = resp->wol_filter_id;
12683 bp->wol = 0;
12684 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
12694 struct ethtool_keee *eee = &bp->eee;
12695 struct bnxt_link_info *link_info = &bp->link_info;
12697 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
12700 if (eee->eee_enabled) {
12704 _bnxt_fw_to_linkmode(advertising, link_info->advertising);
12706 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
12707 eee->eee_enabled = 0;
12710 if (linkmode_andnot(tmp, eee->advertised, advertising)) {
12711 linkmode_and(eee->advertised, advertising,
12712 eee->supported);
12725 struct bnxt_link_info *link_info = &bp->link_info;
12729 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
12736 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
12737 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
12738 link_info->req_flow_ctrl)
12740 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
12741 link_info->force_pause_setting != link_info->req_flow_ctrl)
12743 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
12744 if (BNXT_AUTO_MODE(link_info->auto_mode))
12748 if (link_info->req_duplex != link_info->duplex_setting)
12751 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
12771 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
12785 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
12786 return -EBUSY;
12788 if (bp->dev->reg_state == NETREG_UNREGISTERED)
12789 return -ENODEV;
12796 clear_bit(BNXT_STATE_ABORT_ERR, &bp->state);
12797 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
12808 if (list_empty(&fltr->list))
12811 if (fltr->type == BNXT_FLTR_TYPE_NTUPLE) {
12813 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
12814 atomic_inc(&l2_fltr->refcnt);
12815 ntp_fltr->l2_fltr = l2_fltr;
12818 netdev_err(bp->dev, "restoring previously configured ntuple filter id %d failed\n",
12819 fltr->sw_id);
12821 } else if (fltr->type == BNXT_FLTR_TYPE_L2) {
12825 netdev_err(bp->dev, "restoring previously configured l2 filter id %d failed\n",
12826 fltr->sw_id);
12835 list_for_each_entry_safe(usr_fltr, tmp, &bp->usr_fltr_list, list)
12841 int numa_node = dev_to_node(&bp->pdev->dev);
12848 q_map = kcalloc(bp->tx_nr_rings_per_tc, sizeof(*q_map), GFP_KERNEL);
12850 return -ENOMEM;
12857 map_idx = i % bp->tx_nr_rings_per_tc;
12864 for (q_idx = 0; q_idx < bp->dev->real_num_tx_queues; q_idx++) {
12865 map_idx = q_idx % bp->tx_nr_rings_per_tc;
12866 rc = netif_set_xps_queue(bp->dev, &q_map[map_idx], q_idx);
12868 netdev_warn(bp->dev, "Error setting XPS for q:%d\n",
12881 return bp->num_tc ? bp->tx_nr_rings_per_tc * bp->num_tc :
12882 bp->tx_nr_rings_per_tc;
12887 return bp->num_tc ? bp->tx_nr_rings / bp->num_tc : bp->tx_nr_rings;
12894 netif_carrier_off(bp->dev);
12899 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
12908 bp->tx_nr_rings -= bp->tx_nr_rings_xdp;
12909 bp->tx_nr_rings_per_tc = bnxt_tx_nr_rings_per_tc(bp);
12910 if (bp->tx_nr_rings_xdp) {
12911 bp->tx_nr_rings_xdp = bp->tx_nr_rings_per_tc;
12912 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
12916 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
12924 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
12931 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
12939 mutex_lock(&bp->link_lock);
12941 mutex_unlock(&bp->link_lock);
12943 netdev_warn(bp->dev, "failed to update phy settings\n");
12945 bp->link_info.phy_retry = true;
12946 bp->link_info.phy_retry_expires =
12953 udp_tunnel_nic_reset_ntf(bp->dev);
12956 netdev_warn(bp->dev, "failed to set xps mapping\n");
12959 if (bp->tx_nr_rings_xdp < num_possible_cpus()) {
12965 set_bit(BNXT_STATE_OPEN, &bp->state);
12969 mod_timer(&bp->timer, jiffies + bp->current_interval);
12971 mutex_lock(&bp->link_lock);
12973 mutex_unlock(&bp->link_lock);
12975 /* VF-reps may need to be re-opened after the PF is re-opened */
12999 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
13000 rc = -EIO;
13004 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
13005 netif_close(bp->dev);
13018 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
13019 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
13020 rc = -ENODEV;
13026 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
13030 set_bit(BNXT_STATE_HALF_OPEN, &bp->state);
13033 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
13035 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
13043 netif_close(bp->dev);
13056 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
13062 struct bnxt_pf_info *pf = &bp->pf;
13063 int n = pf->active_vfs;
13075 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
13078 if (rc == -EBUSY)
13079 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n");
13081 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n");
13082 return -ENODEV;
13094 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
13095 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
13106 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
13107 test_bit(BNXT_STATE_READ_STATS, &bp->state));
13116 /* Close the VF-reps before closing PF */
13123 clear_bit(BNXT_STATE_OPEN, &bp->state);
13137 timer_delete_sync(&bp->timer);
13141 if (bp->bnapi && irq_re_init) {
13142 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
13143 bnxt_get_ring_err_stats(bp, &bp->ring_err_stats_prev);
13154 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
13163 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
13164 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
13168 if (bp->sriov_cfg) {
13171 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
13172 !bp->sriov_cfg,
13175 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete, proceeding to close!\n");
13177 netdev_warn(bp->dev, "SRIOV config operation interrupted, proceeding to close!\n");
13200 if (bp->hwrm_spec_code < 0x10a00)
13201 return -EOPNOTSUPP;
13207 req->port_id = cpu_to_le16(bp->pf.port_id);
13208 req->phy_addr = phy_addr;
13209 req->reg_addr = cpu_to_le16(reg & 0x1f);
13211 req->cl45_mdio = 1;
13212 req->phy_addr = mdio_phy_id_prtad(phy_addr);
13213 req->dev_addr = mdio_phy_id_devad(phy_addr);
13214 req->reg_addr = cpu_to_le16(reg);
13220 *val = le16_to_cpu(resp->reg_data);
13231 if (bp->hwrm_spec_code < 0x10a00)
13232 return -EOPNOTSUPP;
13238 req->port_id = cpu_to_le16(bp->pf.port_id);
13239 req->phy_addr = phy_addr;
13240 req->reg_addr = cpu_to_le16(reg & 0x1f);
13242 req->cl45_mdio = 1;
13243 req->phy_addr = mdio_phy_id_prtad(phy_addr);
13244 req->dev_addr = mdio_phy_id_devad(phy_addr);
13245 req->reg_addr = cpu_to_le16(reg);
13247 req->reg_data = cpu_to_le16(val);
13261 mdio->phy_id = bp->link_info.phy_addr;
13268 return -EAGAIN;
13270 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
13272 mdio->val_out = mii_regval;
13278 return -EAGAIN;
13280 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
13281 mdio->val_in);
13287 return -EOPNOTSUPP;
13295 for (i = 0; i < bp->cp_nr_rings; i++) {
13296 struct bnxt_napi *bnapi = bp->bnapi[i];
13297 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
13298 u64 *sw = cpr->stats.sw_stats;
13300 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
13301 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
13302 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
13304 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
13305 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
13306 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
13308 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
13309 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
13310 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
13312 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
13313 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
13314 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
13316 stats->rx_missed_errors +=
13319 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
13321 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
13323 stats->rx_dropped +=
13324 cpr->sw_stats->rx.rx_netpoll_discards +
13325 cpr->sw_stats->rx.rx_oom_discards;
13332 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
13334 stats->rx_packets += prev_stats->rx_packets;
13335 stats->tx_packets += prev_stats->tx_packets;
13336 stats->rx_bytes += prev_stats->rx_bytes;
13337 stats->tx_bytes += prev_stats->tx_bytes;
13338 stats->rx_missed_errors += prev_stats->rx_missed_errors;
13339 stats->multicast += prev_stats->multicast;
13340 stats->rx_dropped += prev_stats->rx_dropped;
13341 stats->tx_dropped += prev_stats->tx_dropped;
13349 set_bit(BNXT_STATE_READ_STATS, &bp->state);
13354 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
13355 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
13356 *stats = bp->net_stats_prev;
13363 if (bp->flags & BNXT_FLAG_PORT_STATS) {
13364 u64 *rx = bp->port_stats.sw_stats;
13365 u64 *tx = bp->port_stats.sw_stats +
13368 stats->rx_crc_errors =
13370 stats->rx_frame_errors =
13372 stats->rx_length_errors =
13376 stats->rx_errors =
13379 stats->collisions =
13381 stats->tx_fifo_errors =
13383 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
13385 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
13392 struct bnxt_sw_stats *sw_stats = cpr->sw_stats;
13393 u64 *hw_stats = cpr->stats.sw_stats;
13395 stats->rx_total_l4_csum_errors += sw_stats->rx.rx_l4_csum_errors;
13396 stats->rx_total_resets += sw_stats->rx.rx_resets;
13397 stats->rx_total_buf_errors += sw_stats->rx.rx_buf_errors;
13398 stats->rx_total_oom_discards += sw_stats->rx.rx_oom_discards;
13399 stats->rx_total_netpoll_discards += sw_stats->rx.rx_netpoll_discards;
13400 stats->rx_total_ring_discards +=
13402 stats->tx_total_resets += sw_stats->tx.tx_resets;
13403 stats->tx_total_ring_discards +=
13405 stats->total_missed_irqs += sw_stats->cmn.missed_irqs;
13413 for (i = 0; i < bp->cp_nr_rings; i++)
13414 bnxt_get_one_ring_err_stats(bp, stats, &bp->bnapi[i]->cp_ring);
13419 struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
13420 struct net_device *dev = bp->dev;
13430 vnic->mc_list_count = 0;
13433 haddr = ha->addr;
13434 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
13435 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
13444 if (mc_count != vnic->mc_list_count) {
13445 vnic->mc_list_count = mc_count;
13453 struct net_device *dev = bp->dev;
13454 struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
13458 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
13462 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
13478 if (!test_bit(BNXT_STATE_OPEN, &bp->state))
13481 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
13482 mask = vnic->rx_mask;
13488 if (dev->flags & IFF_PROMISC)
13493 if (dev->flags & IFF_BROADCAST)
13495 if (dev->flags & IFF_ALLMULTI) {
13497 vnic->mc_list_count = 0;
13498 } else if (dev->flags & IFF_MULTICAST) {
13502 if (mask != vnic->rx_mask || uc_update || mc_update) {
13503 vnic->rx_mask = mask;
13511 struct net_device *dev = bp->dev;
13512 struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
13524 for (i = 1; i < vnic->uc_filter_count; i++) {
13525 struct bnxt_l2_filter *fltr = vnic->l2_filters[i];
13531 vnic->uc_filter_count = 1;
13534 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
13535 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
13538 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
13540 vnic->uc_filter_count++;
13545 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
13546 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
13548 if (BNXT_VF(bp) && rc == -ENODEV) {
13549 if (!test_and_set_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
13550 netdev_warn(bp->dev, "Cannot configure L2 filters while PF is unavailable, will retry\n");
13552 netdev_dbg(bp->dev, "PF still unavailable while configuring L2 filters.\n");
13555 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
13557 vnic->uc_filter_count = i;
13561 if (test_and_clear_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
13562 netdev_notice(bp->dev, "Retry of L2 filter configuration successful.\n");
13565 if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) &&
13567 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
13569 if (rc && (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST)) {
13570 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
13572 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
13573 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
13574 vnic->mc_list_count = 0;
13578 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
13588 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
13593 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
13596 if (!netif_running(bp->dev))
13606 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
13607 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
13616 if (bp->rss_cap & BNXT_RSS_CAP_NEW_RSS_CAP)
13627 if ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&
13631 if (!bnxt_can_reserve_rings(bp) || !bp->rx_nr_rings)
13634 hwr.grp = bp->rx_nr_rings;
13635 hwr.vnic = bnxt_get_total_vnics(bp, bp->rx_nr_rings);
13643 if (bp->rx_nr_rings > 1)
13644 netdev_warn(bp->dev,
13646 min(max_rss_ctxs - 1, max_vnics - 1));
13657 if (hwr.vnic <= bp->hw_resc.resv_vnics &&
13658 hwr.rss_ctx <= bp->hw_resc.resv_rsscos_ctxs)
13662 if (hwr.vnic <= bp->hw_resc.resv_vnics &&
13663 hwr.rss_ctx <= bp->hw_resc.resv_rsscos_ctxs)
13666 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
13682 if ((bp->flags & BNXT_FLAG_NO_AGG_RINGS) || bp->xdp_prog)
13696 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
13702 if (BNXT_VF(bp) && bp->vf.vlan)
13712 bp->flags = flags;
13722 u32 flags = bp->flags;
13733 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
13744 changes = flags ^ bp->flags;
13747 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
13749 (bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
13759 if (flags != bp->flags) {
13760 u32 old_flags = bp->flags;
13762 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
13763 bp->flags = flags;
13776 bp->flags = flags;
13781 bp->flags = old_flags;
13790 struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off);
13800 nexthdr = &ip6h->nexthdr;
13808 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data,
13820 /* The ext header may be a hop-by-hop header inserted for
13825 if (likely(skb->len <= GRO_LEGACY_MAX_SIZE))
13829 if (jhdr->tlv_type != IPV6_TLV_JUMBO || jhdr->hdrlen != 0 ||
13830 jhdr->nexthdr != IPPROTO_TCP)
13838 nexthdr = &hp->nexthdr;
13843 if (skb->encapsulation) {
13849 /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */
13857 __be16 udp_port = uh->dest;
13859 if (udp_port != bp->vxlan_port && udp_port != bp->nge_port &&
13860 udp_port != bp->vxlan_gpe_port)
13862 if (skb->inner_protocol == htons(ETH_P_TEB)) {
13865 switch (eh->h_proto) {
13873 } else if (skb->inner_protocol == htons(ETH_P_IP)) {
13875 } else if (skb->inner_protocol == htons(ETH_P_IPV6)) {
13890 switch (skb->inner_protocol) {
13917 if (!skb->encapsulation)
13919 l4_proto = &ip_hdr(skb)->protocol;
13950 rc = -ENOMEM;
13954 req->host_dest_addr = cpu_to_le64(mapping);
13957 req->read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
13958 req->read_len32 = cpu_to_le32(num_words);
13961 if (rc || resp->error_code) {
13962 rc = -EIO;
13984 req->ring_type = ring_type;
13985 req->fw_ring_id = cpu_to_le32(ring_id);
13989 *prod = le32_to_cpu(resp->producer_index);
13990 *cons = le32_to_cpu(resp->consumer_index);
13999 int i = bnapi->index, j;
14002 netdev_info(bnapi->bp->dev, "[%d.%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
14003 i, j, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
14004 txr->tx_cons);
14009 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
14010 int i = bnapi->index;
14015 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
14016 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
14017 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
14018 rxr->rx_sw_agg_prod);
14023 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
14024 int i = bnapi->index;
14026 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
14027 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
14035 for (i = 0; i < bp->cp_nr_rings; i++) {
14036 bnapi = bp->bnapi[i];
14047 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
14049 struct bnxt_napi *bnapi = rxr->bnapi;
14058 cpr = &bnapi->cp_ring;
14059 cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
14060 req->cmpl_ring = cpu_to_le16(cp_ring_id);
14061 req->ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
14062 req->ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
14070 if (netif_running(bp->dev)) {
14080 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
14086 struct bnxt_fw_health *fw_health = bp->fw_health;
14087 struct pci_dev *pdev = bp->pdev;
14090 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
14095 if (fw_health->tmr_counter) {
14096 fw_health->tmr_counter--;
14101 if (val == fw_health->last_fw_heartbeat && pci_device_is_present(pdev)) {
14102 fw_health->arrests++;
14106 fw_health->last_fw_heartbeat = val;
14109 if (val != fw_health->last_fw_reset_cnt && pci_device_is_present(pdev)) {
14110 fw_health->discoveries++;
14114 fw_health->tmr_counter = fw_health->tmr_multiplier;
14124 struct net_device *dev = bp->dev;
14126 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
14129 if (atomic_read(&bp->intr_sem) != 0)
14132 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
14135 if (BNXT_LINK_IS_UP(bp) && bp->stats_coal_ticks)
14142 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count)
14146 if (bp->link_info.phy_retry) {
14147 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
14148 bp->link_info.phy_retry = false;
14149 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
14155 if (test_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
14158 if ((BNXT_CHIP_P5(bp)) && !bp->chip_rev && netif_carrier_ok(dev))
14162 mod_timer(&bp->timer, jiffies + bp->current_interval);
14173 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
14174 netdev_lock(bp->dev);
14179 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
14180 netdev_unlock(bp->dev);
14187 if (test_bit(BNXT_STATE_OPEN, &bp->state))
14198 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
14203 if (bp->flags & BNXT_FLAG_TPA)
14205 for (i = 0; i < bp->rx_nr_rings; i++) {
14206 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
14210 if (!rxr->bnapi->in_reset)
14215 if (rc == -EINVAL || rc == -EOPNOTSUPP)
14216 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
14218 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
14224 rxr->rx_prod = 0;
14225 rxr->rx_agg_prod = 0;
14226 rxr->rx_sw_agg_prod = 0;
14227 rxr->rx_next_cons = 0;
14228 rxr->bnapi->in_reset = false;
14230 cpr = &rxr->bnapi->cp_ring;
14231 cpr->sw_stats->rx.rx_resets++;
14232 if (bp->flags & BNXT_FLAG_AGG_RINGS)
14233 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
14234 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
14236 if (bp->flags & BNXT_FLAG_TPA)
14248 pci_disable_device(bp->pdev);
14257 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
14260 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
14262 bp->fw_reset_min_dsecs = 0;
14269 if (pci_is_enabled(bp->pdev))
14270 pci_disable_device(bp->pdev);
14276 struct bnxt_fw_health *fw_health = bp->fw_health;
14281 if (val == fw_health->last_fw_heartbeat)
14285 if (val != fw_health->last_fw_reset_cnt)
14297 struct bnxt_fw_health *fw_health = bp->fw_health;
14298 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
14301 if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
14302 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
14309 write_seqlock_irqsave(&ptp->ptp_lock, flags);
14310 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
14311 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
14313 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
14316 wait_dsecs = fw_health->master_func_wait_dsecs;
14317 if (fw_health->primary) {
14318 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
14320 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
14322 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
14323 wait_dsecs = fw_health->normal_func_wait_dsecs;
14324 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
14327 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
14328 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
14334 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
14335 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
14355 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
14358 if (bp->pf.registered_vfs)
14359 return bp->pf.registered_vfs;
14360 if (bp->sriov_cfg)
14370 if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
14371 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
14372 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
14379 write_seqlock_irqsave(&ptp->ptp_lock, flags);
14380 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
14381 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
14383 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
14385 if (bp->pf.active_vfs &&
14386 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
14389 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
14391 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
14392 netif_close(bp->dev);
14397 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
14398 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
14399 bp->fw_reset_state =
14405 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
14406 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
14409 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
14410 tmo = bp->fw_reset_min_dsecs * HZ / 10;
14422 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
14425 for (i = 0; i < bp->cp_nr_rings; i++) {
14426 struct bnxt_napi *bnapi = bp->bnapi[i];
14434 cpr = &bnapi->cp_ring;
14435 for (j = 0; j < cpr->cp_ring_count; j++) {
14436 struct bnxt_cp_ring_info *cpr2 = &cpr->cp_ring_arr[j];
14439 if (cpr2->has_more_work || !bnxt_has_work(bp, cpr2))
14442 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
14443 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
14446 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
14450 cpr->sw_stats->cmn.missed_irqs++;
14459 struct bnxt_link_info *link_info = &bp->link_info;
14461 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
14462 link_info->autoneg = BNXT_AUTONEG_SPEED;
14463 if (bp->hwrm_spec_code >= 0x10201) {
14464 if (link_info->auto_pause_setting &
14466 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
14468 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
14473 link_info->req_duplex = link_info->duplex_setting;
14475 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
14476 link_info->req_flow_ctrl =
14477 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
14479 link_info->req_flow_ctrl = link_info->force_pause_setting;
14484 struct bnxt_fw_health *fw_health = bp->fw_health;
14491 req->event_data1 = cpu_to_le32(fw_health->echo_req_data1);
14492 req->event_data2 = cpu_to_le32(fw_health->echo_req_data2);
14506 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
14508 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
14509 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
14513 if (test_and_clear_bit(BNXT_RESTART_ULP_SP_EVENT, &bp->sp_event)) {
14518 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
14521 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
14523 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
14525 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
14526 netdev_info(bp->dev, "Receive PF driver unload event!\n");
14527 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
14533 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
14536 mutex_lock(&bp->link_lock);
14538 &bp->sp_event))
14543 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
14547 &bp->sp_event))
14549 mutex_unlock(&bp->link_lock);
14551 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
14554 mutex_lock(&bp->link_lock);
14556 mutex_unlock(&bp->link_lock);
14558 netdev_warn(bp->dev, "update phy settings retry failed\n");
14560 bp->link_info.phy_retry = false;
14561 netdev_info(bp->dev, "update phy settings retry succeeded\n");
14564 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
14565 mutex_lock(&bp->link_lock);
14567 mutex_unlock(&bp->link_lock);
14570 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
14573 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
14576 if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event))
14579 if (test_and_clear_bit(BNXT_THERMAL_THRESHOLD_SP_EVENT, &bp->sp_event))
14585 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
14588 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
14591 if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
14594 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) {
14595 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) ||
14596 test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state))
14602 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
14608 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
14629 return -ENOMEM;
14631 if (bp->flags & BNXT_FLAG_AGG_RINGS)
14637 return -ENOMEM;
14644 return -ENOMEM;
14652 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
14655 if (!rc && pci_msix_can_alloc_dyn(bp->pdev)) {
14656 if (!bnxt_ulp_registered(bp->edev)) {
14660 if (hwr.cp > bp->total_irqs) {
14664 netdev_warn(bp->dev, "Unable to allocate %d MSIX vectors, maximum available %d\n",
14666 rc = -ENOSPC;
14675 if (bp->bar2) {
14676 pci_iounmap(pdev, bp->bar2);
14677 bp->bar2 = NULL;
14680 if (bp->bar1) {
14681 pci_iounmap(pdev, bp->bar1);
14682 bp->bar1 = NULL;
14685 if (bp->bar0) {
14686 pci_iounmap(pdev, bp->bar0);
14687 bp->bar0 = NULL;
14693 bnxt_unmap_bars(bp, bp->pdev);
14694 pci_release_regions(bp->pdev);
14695 if (pci_is_enabled(bp->pdev))
14696 pci_disable_device(bp->pdev);
14701 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
14705 if (coal_cap->cmpl_params &
14712 coal = &bp->rx_coal;
14713 coal->coal_ticks = 10;
14714 coal->coal_bufs = 30;
14715 coal->coal_ticks_irq = 1;
14716 coal->coal_bufs_irq = 2;
14717 coal->idle_thresh = 50;
14718 coal->bufs_per_record = 2;
14719 coal->budget = 64; /* NAPI budget */
14720 coal->flags = flags;
14722 coal = &bp->tx_coal;
14723 coal->coal_ticks = 28;
14724 coal->coal_bufs = 30;
14725 coal->coal_ticks_irq = 2;
14726 coal->coal_bufs_irq = 2;
14727 coal->bufs_per_record = 1;
14728 coal->flags = flags;
14730 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
14733 /* FW that pre-reserves 1 VNIC per function */
14738 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&
14741 if ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&
14753 bp->max_pfcwd_tmo_ms = 0;
14760 bp->max_pfcwd_tmo_ms = le16_to_cpu(resp->max_pfcwd_timeout);
14768 bp->fw_cap = 0;
14789 return -ENODEV;
14802 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
14804 return -ENODEV;
14809 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
14813 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
14817 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
14823 return -ENODEV;
14827 netdev_warn(bp->dev, "crash dump mem alloc failure rc: %d\n",
14833 netdev_warn(bp->dev,
14839 bp->fw_cap |= BNXT_FW_CAP_PRE_RESV_VNICS;
14846 if (bp->fw_cap & BNXT_FW_CAP_PTP)
14855 bp->rss_cap &= ~BNXT_RSS_CAP_UDP_RSS_CAP;
14856 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
14860 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)
14861 bp->rss_hash_delta = bp->rss_hash_cfg;
14862 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
14863 bp->rss_cap |= BNXT_RSS_CAP_UDP_RSS_CAP;
14864 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
14871 struct net_device *dev = bp->dev;
14873 dev->hw_features &= ~NETIF_F_NTUPLE;
14874 dev->features &= ~NETIF_F_NTUPLE;
14875 bp->flags &= ~BNXT_FLAG_RFS;
14877 dev->hw_features |= NETIF_F_NTUPLE;
14879 bp->flags |= BNXT_FLAG_RFS;
14880 dev->features |= NETIF_F_NTUPLE;
14887 struct pci_dev *pdev = bp->pdev;
14893 if (bp->flags & BNXT_FLAG_WOL_CAP)
14894 device_set_wakeup_enable(&pdev->dev, bp->wol);
14896 device_set_wakeup_capable(&pdev->dev, false);
14910 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
14915 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
14921 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
14931 struct bnxt_fw_health *fw_health = bp->fw_health;
14932 u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
14933 u32 val = fw_health->fw_reset_seq_vals[reg_idx];
14936 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
14941 pci_write_config_dword(bp->pdev, reg_off, val);
14945 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
14949 writel(val, bp->bar0 + reg_off);
14952 writel(val, bp->bar1 + reg_off);
14956 pci_read_config_dword(bp->pdev, 0, &val);
14967 if (~bp->fw_cap & BNXT_FW_CAP_HOT_RESET_IF)
14973 req->fid = cpu_to_le16(0xffff);
14976 result = !!(le16_to_cpu(resp->flags) &
14984 struct bnxt_fw_health *fw_health = bp->fw_health;
14987 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
14989 bp->fw_reset_timestamp = jiffies;
14993 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
14994 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
14996 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
15001 req->target_id = cpu_to_le16(HWRM_TARGET_ID_KONG);
15002 req->embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
15003 req->selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
15004 req->flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
15007 if (rc != -ENODEV)
15008 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
15010 bp->fw_reset_timestamp = jiffies;
15015 return time_after(jiffies, bp->fw_reset_timestamp +
15016 (bp->fw_reset_max_dsecs * HZ / 10));
15021 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
15022 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF)
15024 bp->fw_reset_state = BNXT_FW_RESET_STATE_ABORT;
15025 netif_close(bp->dev);
15033 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
15034 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
15038 switch (bp->fw_reset_state) {
15044 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
15045 n, jiffies_to_msecs(jiffies -
15046 bp->fw_reset_timestamp));
15050 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
15051 bp->fw_reset_state = 0;
15052 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
15059 bp->fw_reset_timestamp = jiffies;
15060 netdev_lock(bp->dev);
15061 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
15063 netdev_unlock(bp->dev);
15067 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
15068 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
15071 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
15072 tmo = bp->fw_reset_min_dsecs * HZ / 10;
15074 netdev_unlock(bp->dev);
15088 if (!bp->fw_health->primary) {
15089 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
15091 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
15095 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
15100 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
15101 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
15105 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) &&
15106 !bp->fw_reset_min_dsecs) {
15109 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
15112 netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
15113 rc = -ETIMEDOUT;
15120 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
15121 clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
15122 if (test_and_clear_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state) &&
15123 !test_bit(BNXT_STATE_FW_ACTIVATE, &bp->state))
15125 if (pci_enable_device(bp->pdev)) {
15126 netdev_err(bp->dev, "Cannot re-enable PCI device\n");
15127 rc = -ENODEV;
15130 pci_set_master(bp->pdev);
15131 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
15134 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
15138 netdev_err(bp->dev, "Firmware reset aborted\n");
15144 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
15145 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
15148 while (!netdev_trylock(bp->dev)) {
15152 rc = bnxt_open(bp->dev);
15154 netdev_err(bp->dev, "bnxt_open() failed during FW reset\n");
15156 netdev_unlock(bp->dev);
15160 if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) &&
15161 bp->fw_health->enabled) {
15162 bp->fw_health->last_fw_reset_cnt =
15165 bp->fw_reset_state = 0;
15168 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
15170 clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state);
15171 if (test_and_clear_bit(BNXT_STATE_RECOVER, &bp->state)) {
15175 netdev_unlock(bp->dev);
15178 netdev_lock(bp->dev);
15181 netdev_unlock(bp->dev);
15187 if (bp->fw_health->status_reliable ||
15188 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
15191 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
15194 netdev_lock(bp->dev);
15196 netdev_unlock(bp->dev);
15206 SET_NETDEV_DEV(dev, &pdev->dev);
15208 /* enable device (incl. PCI PM wakeup), and bus-mastering */
15211 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15216 dev_err(&pdev->dev,
15218 rc = -ENODEV;
15224 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15228 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
15229 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
15230 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
15231 rc = -EIO;
15237 bp->dev = dev;
15238 bp->pdev = pdev;
15240 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
15243 bp->bar0 = pci_ioremap_bar(pdev, 0);
15244 if (!bp->bar0) {
15245 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15246 rc = -ENOMEM;
15250 bp->bar2 = pci_ioremap_bar(pdev, 4);
15251 if (!bp->bar2) {
15252 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
15253 rc = -ENOMEM;
15257 INIT_WORK(&bp->sp_task, bnxt_sp_task);
15258 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
15260 spin_lock_init(&bp->ntp_fltr_lock);
15262 spin_lock_init(&bp->db_lock);
15265 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
15266 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
15268 timer_setup(&bp->timer, bnxt_timer, 0);
15269 bp->current_interval = BNXT_TIMER_INTERVAL;
15271 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
15272 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
15274 clear_bit(BNXT_STATE_OPEN, &bp->state);
15296 if (!is_valid_ether_addr(addr->sa_data))
15297 return -EADDRNOTAVAIL;
15299 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
15302 rc = bnxt_approve_mac(bp, addr->sa_data, true);
15306 eth_hw_addr_set(dev, addr->sa_data);
15325 WRITE_ONCE(dev->mtu, new_mtu);
15327 /* MTU change may change the AGG ring settings if an XDP multi-buffer
15331 if (READ_ONCE(bp->xdp_prog))
15348 if (tc > bp->max_tc) {
15350 tc, bp->max_tc);
15351 return -EINVAL;
15354 if (bp->num_tc == tc)
15357 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
15360 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
15361 sh, tc, bp->tx_nr_rings_xdp);
15365 /* Needs to close the device and do hw resource re-allocations */
15366 if (netif_running(bp->dev))
15370 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
15372 bp->num_tc = tc;
15374 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
15376 bp->num_tc = 0;
15378 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
15379 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings);
15380 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) :
15381 tx_cp + bp->rx_nr_rings;
15383 if (netif_running(bp->dev))
15395 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
15396 return -EOPNOTSUPP;
15400 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
15402 return -EOPNOTSUPP;
15422 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
15424 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
15427 return -EOPNOTSUPP;
15439 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
15440 return bnxt_toeplitz(bp, fkeys, (void *)vnic->rss_hash_key);
15449 spin_lock_bh(&bp->ntp_fltr_lock);
15450 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, bp->max_fltr, 0);
15452 spin_unlock_bh(&bp->ntp_fltr_lock);
15453 return -ENOMEM;
15456 fltr->base.sw_id = (u16)bit_id;
15457 fltr->base.type = BNXT_FLTR_TYPE_NTUPLE;
15458 fltr->base.flags |= BNXT_ACT_RING_DST;
15459 head = &bp->ntp_fltr_hash_tbl[idx];
15460 hlist_add_head_rcu(&fltr->base.hash, head);
15461 set_bit(BNXT_FLTR_INSERTED, &fltr->base.state);
15462 bnxt_insert_usr_fltr(bp, &fltr->base);
15463 bp->ntp_fltr_count++;
15464 spin_unlock_bh(&bp->ntp_fltr_lock);
15471 struct bnxt_flow_masks *masks1 = &f1->fmasks;
15472 struct bnxt_flow_masks *masks2 = &f2->fmasks;
15473 struct flow_keys *keys1 = &f1->fkeys;
15474 struct flow_keys *keys2 = &f2->fkeys;
15476 if (keys1->basic.n_proto != keys2->basic.n_proto ||
15477 keys1->basic.ip_proto != keys2->basic.ip_proto)
15480 if (keys1->basic.n_proto == htons(ETH_P_IP)) {
15481 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
15482 masks1->addrs.v4addrs.src != masks2->addrs.v4addrs.src ||
15483 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst ||
15484 masks1->addrs.v4addrs.dst != masks2->addrs.v4addrs.dst)
15487 if (!ipv6_addr_equal(&keys1->addrs.v6addrs.src,
15488 &keys2->addrs.v6addrs.src) ||
15489 !ipv6_addr_equal(&masks1->addrs.v6addrs.src,
15490 &masks2->addrs.v6addrs.src) ||
15491 !ipv6_addr_equal(&keys1->addrs.v6addrs.dst,
15492 &keys2->addrs.v6addrs.dst) ||
15493 !ipv6_addr_equal(&masks1->addrs.v6addrs.dst,
15494 &masks2->addrs.v6addrs.dst))
15498 return keys1->ports.src == keys2->ports.src &&
15499 masks1->ports.src == masks2->ports.src &&
15500 keys1->ports.dst == keys2->ports.dst &&
15501 masks1->ports.dst == masks2->ports.dst &&
15502 keys1->control.flags == keys2->control.flags &&
15503 f1->l2_fltr == f2->l2_fltr;
15513 head = &bp->ntp_fltr_hash_tbl[idx];
15533 if (ether_addr_equal(dev->dev_addr, eth->h_dest)) {
15534 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
15535 atomic_inc(&l2_fltr->refcnt);
15539 ether_addr_copy(key.dst_mac_addr, eth->h_dest);
15543 return -EINVAL;
15544 if (l2_fltr->base.flags & BNXT_ACT_FUNC_DST) {
15546 return -EINVAL;
15552 return -ENOMEM;
15555 fkeys = &new_fltr->fkeys;
15557 rc = -EPROTONOSUPPORT;
15561 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
15562 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
15563 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
15564 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
15565 rc = -EPROTONOSUPPORT;
15568 new_fltr->fmasks = BNXT_FLOW_IPV4_MASK_ALL;
15569 if (fkeys->basic.n_proto == htons(ETH_P_IPV6)) {
15570 if (bp->hwrm_spec_code < 0x10601) {
15571 rc = -EPROTONOSUPPORT;
15574 new_fltr->fmasks = BNXT_FLOW_IPV6_MASK_ALL;
15576 flags = fkeys->control.flags;
15578 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
15579 rc = -EPROTONOSUPPORT;
15582 new_fltr->l2_fltr = l2_fltr;
15588 rc = fltr->base.sw_id;
15594 new_fltr->flow_id = flow_id;
15595 new_fltr->base.rxq = rxq_index;
15599 return new_fltr->base.sw_id;
15611 spin_lock_bh(&bp->ntp_fltr_lock);
15612 if (!test_and_clear_bit(BNXT_FLTR_INSERTED, &fltr->base.state)) {
15613 spin_unlock_bh(&bp->ntp_fltr_lock);
15616 hlist_del_rcu(&fltr->base.hash);
15617 bnxt_del_one_usr_fltr(bp, &fltr->base);
15618 bp->ntp_fltr_count--;
15619 spin_unlock_bh(&bp->ntp_fltr_lock);
15620 bnxt_del_l2_filter(bp, fltr->l2_fltr);
15621 clear_bit(fltr->base.sw_id, bp->ntp_fltr_bmap);
15636 head = &bp->ntp_fltr_hash_tbl[i];
15640 if (test_bit(BNXT_FLTR_VALID, &fltr->base.state)) {
15641 if (fltr->base.flags & BNXT_ACT_NO_AGING)
15643 if (rps_may_expire_flow(bp->dev, fltr->base.rxq,
15644 fltr->flow_id,
15645 fltr->base.sw_id)) {
15656 set_bit(BNXT_FLTR_VALID, &fltr->base.state);
15672 if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
15674 else if (ti->type == UDP_TUNNEL_TYPE_GENEVE)
15679 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti->port, cmd);
15688 if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
15690 else if (ti->type == UDP_TUNNEL_TYPE_GENEVE)
15723 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
15734 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
15735 return -EOPNOTSUPP;
15739 return -EINVAL;
15745 if (mode == bp->br_mode)
15750 bp->br_mode = mode;
15761 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
15762 return -EOPNOTSUPP;
15764 /* The PF and it's VF-reps only support the switchdev framework */
15765 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
15766 return -EOPNOTSUPP;
15768 ppid->id_len = sizeof(bp->dsn);
15769 memcpy(ppid->id, bp->dsn, ppid->id_len);
15816 if (!bp->bnapi)
15819 cpr = &bp->bnapi[i]->cp_ring;
15820 sw = cpr->stats.sw_stats;
15822 stats->packets = 0;
15823 stats->packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
15824 stats->packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
15825 stats->packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
15827 stats->bytes = 0;
15828 stats->bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
15829 stats->bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
15830 stats->bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
15832 stats->alloc_fail = cpr->sw_stats->rx.rx_oom_discards;
15842 if (!bp->tx_ring)
15845 bnapi = bp->tx_ring[bp->tx_ring_map[i]].bnapi;
15846 sw = bnapi->cp_ring.stats.sw_stats;
15848 stats->packets = 0;
15849 stats->packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
15850 stats->packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
15851 stats->packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
15853 stats->bytes = 0;
15854 stats->bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
15855 stats->bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
15856 stats->bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
15865 rx->packets = bp->net_stats_prev.rx_packets;
15866 rx->bytes = bp->net_stats_prev.rx_bytes;
15867 rx->alloc_fail = bp->ring_err_stats_prev.rx_total_oom_discards;
15869 tx->packets = bp->net_stats_prev.tx_packets;
15870 tx->bytes = bp->net_stats_prev.tx_bytes;
15886 if (!bp->rx_ring)
15887 return -ENETDOWN;
15889 rxr = &bp->rx_ring[idx];
15895 clone->rx_prod = 0;
15896 clone->rx_agg_prod = 0;
15897 clone->rx_sw_agg_prod = 0;
15898 clone->rx_next_cons = 0;
15899 clone->need_head_pool = false;
15901 rc = bnxt_alloc_rx_page_pool(bp, clone, rxr->page_pool->p.nid);
15905 rc = xdp_rxq_info_reg(&clone->xdp_rxq, bp->dev, idx, 0);
15909 rc = xdp_rxq_info_reg_mem_model(&clone->xdp_rxq,
15911 clone->page_pool);
15915 ring = &clone->rx_ring_struct;
15916 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
15920 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
15921 ring = &clone->rx_agg_ring_struct;
15922 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
15931 if (bp->flags & BNXT_FLAG_TPA) {
15941 if (bp->flags & BNXT_FLAG_AGG_RINGS)
15943 if (bp->flags & BNXT_FLAG_TPA)
15951 bnxt_free_ring(bp, &clone->rx_agg_ring_struct.ring_mem);
15953 bnxt_free_ring(bp, &clone->rx_ring_struct.ring_mem);
15955 xdp_rxq_info_unreg(&clone->xdp_rxq);
15957 page_pool_destroy(clone->page_pool);
15958 page_pool_destroy(clone->head_pool);
15959 clone->page_pool = NULL;
15960 clone->head_pool = NULL;
15973 xdp_rxq_info_unreg(&rxr->xdp_rxq);
15975 page_pool_destroy(rxr->page_pool);
15976 page_pool_destroy(rxr->head_pool);
15977 rxr->page_pool = NULL;
15978 rxr->head_pool = NULL;
15980 ring = &rxr->rx_ring_struct;
15981 bnxt_free_ring(bp, &ring->ring_mem);
15983 ring = &rxr->rx_agg_ring_struct;
15984 bnxt_free_ring(bp, &ring->ring_mem);
15986 kfree(rxr->rx_agg_bmap);
15987 rxr->rx_agg_bmap = NULL;
15998 dst_ring = &dst->rx_ring_struct;
15999 dst_rmem = &dst_ring->ring_mem;
16000 src_ring = &src->rx_ring_struct;
16001 src_rmem = &src_ring->ring_mem;
16003 WARN_ON(dst_rmem->nr_pages != src_rmem->nr_pages);
16004 WARN_ON(dst_rmem->page_size != src_rmem->page_size);
16005 WARN_ON(dst_rmem->flags != src_rmem->flags);
16006 WARN_ON(dst_rmem->depth != src_rmem->depth);
16007 WARN_ON(dst_rmem->vmem_size != src_rmem->vmem_size);
16008 WARN_ON(dst_rmem->ctx_mem != src_rmem->ctx_mem);
16010 dst_rmem->pg_tbl = src_rmem->pg_tbl;
16011 dst_rmem->pg_tbl_map = src_rmem->pg_tbl_map;
16012 *dst_rmem->vmem = *src_rmem->vmem;
16013 for (i = 0; i < dst_rmem->nr_pages; i++) {
16014 dst_rmem->pg_arr[i] = src_rmem->pg_arr[i];
16015 dst_rmem->dma_arr[i] = src_rmem->dma_arr[i];
16018 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
16021 dst_ring = &dst->rx_agg_ring_struct;
16022 dst_rmem = &dst_ring->ring_mem;
16023 src_ring = &src->rx_agg_ring_struct;
16024 src_rmem = &src_ring->ring_mem;
16026 WARN_ON(dst_rmem->nr_pages != src_rmem->nr_pages);
16027 WARN_ON(dst_rmem->page_size != src_rmem->page_size);
16028 WARN_ON(dst_rmem->flags != src_rmem->flags);
16029 WARN_ON(dst_rmem->depth != src_rmem->depth);
16030 WARN_ON(dst_rmem->vmem_size != src_rmem->vmem_size);
16031 WARN_ON(dst_rmem->ctx_mem != src_rmem->ctx_mem);
16032 WARN_ON(dst->rx_agg_bmap_size != src->rx_agg_bmap_size);
16034 dst_rmem->pg_tbl = src_rmem->pg_tbl;
16035 dst_rmem->pg_tbl_map = src_rmem->pg_tbl_map;
16036 *dst_rmem->vmem = *src_rmem->vmem;
16037 for (i = 0; i < dst_rmem->nr_pages; i++) {
16038 dst_rmem->pg_arr[i] = src_rmem->pg_arr[i];
16039 dst_rmem->dma_arr[i] = src_rmem->dma_arr[i];
16042 dst->rx_agg_bmap = src->rx_agg_bmap;
16055 rxr = &bp->rx_ring[idx];
16058 rxr->rx_prod = clone->rx_prod;
16059 rxr->rx_agg_prod = clone->rx_agg_prod;
16060 rxr->rx_sw_agg_prod = clone->rx_sw_agg_prod;
16061 rxr->rx_next_cons = clone->rx_next_cons;
16062 rxr->rx_tpa = clone->rx_tpa;
16063 rxr->rx_tpa_idx_map = clone->rx_tpa_idx_map;
16064 rxr->page_pool = clone->page_pool;
16065 rxr->head_pool = clone->head_pool;
16066 rxr->xdp_rxq = clone->xdp_rxq;
16067 rxr->need_head_pool = clone->need_head_pool;
16071 bnapi = rxr->bnapi;
16072 cpr = &bnapi->cp_ring;
16081 if (bp->tph_mode) {
16082 rc = bnxt_hwrm_cp_ring_alloc_p5(bp, rxr->rx_cpr);
16091 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
16092 if (bp->flags & BNXT_FLAG_AGG_RINGS)
16093 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
16095 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
16102 napi_enable_locked(&bnapi->napi);
16103 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
16105 mru = bp->dev->mtu + VLAN_ETH_HLEN;
16106 for (i = 0; i < bp->nr_vnics; i++) {
16107 vnic = &bp->vnic_info[i];
16116 netdev_err(bp->dev, "Unexpected HWRM error during queue start rc: %d\n",
16118 napi_enable_locked(&bnapi->napi);
16119 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
16133 for (i = 0; i < bp->nr_vnics; i++) {
16134 vnic = &bp->vnic_info[i];
16141 rxr = &bp->rx_ring[idx];
16142 bnapi = rxr->bnapi;
16143 cpr = &bnapi->cp_ring;
16144 cancel_work_sync(&cpr->dim.work);
16147 page_pool_disable_direct_recycling(rxr->page_pool);
16149 page_pool_disable_direct_recycling(rxr->head_pool);
16151 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
16158 napi_disable_locked(&bnapi->napi);
16160 if (bp->tph_mode) {
16161 bnxt_hwrm_cp_ring_free(bp, rxr->rx_cpr);
16162 bnxt_clear_one_cp_ring(bp, rxr->rx_cpr);
16164 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
16197 WARN_ON(bp->num_rss_ctx);
16198 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
16200 cancel_work_sync(&bp->sp_task);
16201 cancel_delayed_work_sync(&bp->fw_reset_task);
16202 bp->sp_event = 0;
16214 kfree(bp->ptp_cfg);
16215 bp->ptp_cfg = NULL;
16216 kfree(bp->fw_health);
16217 bp->fw_health = NULL;
16221 kfree(bp->rss_indir_tbl);
16222 bp->rss_indir_tbl = NULL;
16230 struct bnxt_link_info *link_info = &bp->link_info;
16232 bp->phy_flags = 0;
16235 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
16239 if (bp->phy_flags & BNXT_PHY_FL_NO_FCS)
16240 bp->dev->priv_flags |= IFF_SUPP_NOFCS;
16242 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS;
16244 bp->mac_flags = 0;
16250 mutex_lock(&bp->link_lock);
16253 mutex_unlock(&bp->link_lock);
16254 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
16262 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
16263 link_info->support_auto_speeds = link_info->support_speeds;
16266 mutex_unlock(&bp->link_lock);
16274 if (!pdev->msix_cap)
16277 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
16284 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
16287 *max_tx = hw_resc->max_tx_rings;
16288 *max_rx = hw_resc->max_rx_rings;
16290 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
16292 hw_resc->max_stat_ctxs -
16294 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS))
16296 max_ring_grps = hw_resc->max_hw_ring_grps;
16298 *max_cp -= 1;
16299 *max_rx -= 2;
16301 if (bp->flags & BNXT_FLAG_AGG_RINGS)
16303 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
16325 return -ENOMEM;
16336 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
16338 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
16342 bp->flags |= BNXT_FLAG_AGG_RINGS;
16345 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
16346 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
16347 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
16351 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
16363 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
16364 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
16365 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
16380 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
16381 bp->rx_nr_rings = bp->cp_nr_rings;
16382 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
16383 bp->tx_nr_rings = bnxt_tx_nr_rings(bp);
16395 bp->flags |= BNXT_FLAG_SHARED_RINGS;
16397 /* Reduce default rings on multi-port cards so that total default
16400 if (bp->port_count > 1) {
16402 max_t(int, num_online_cpus() / bp->port_count, 1);
16409 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
16410 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
16414 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
16415 bp->tx_nr_rings = bnxt_tx_nr_rings(bp);
16417 avail_msix = bnxt_get_max_func_irqs(bp) - bp->cp_nr_rings;
16419 int ulp_num_msix = min(avail_msix, bp->ulp_num_msix_want);
16426 if (rc && rc != -ENODEV)
16427 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
16428 bp->tx_nr_rings_per_tc = bnxt_tx_nr_rings_per_tc(bp);
16432 /* Rings may have been trimmed, re-reserve the trimmed rings. */
16435 if (rc && rc != -ENODEV)
16436 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
16437 bp->tx_nr_rings_per_tc = bnxt_tx_nr_rings_per_tc(bp);
16440 bp->rx_nr_rings++;
16441 bp->cp_nr_rings++;
16444 bp->tx_nr_rings = 0;
16445 bp->rx_nr_rings = 0;
16454 if (bp->tx_nr_rings)
16461 if (BNXT_VF(bp) && rc == -ENODEV)
16462 netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
16464 netdev_err(bp->dev, "Not enough rings available.\n");
16471 bp->tx_nr_rings_per_tc = bnxt_tx_nr_rings_per_tc(bp);
16484 netdev_ops_assert_locked(bp->dev);
16487 if (netif_running(bp->dev))
16495 if (netif_running(bp->dev)) {
16497 netif_close(bp->dev);
16510 eth_hw_addr_set(bp->dev, bp->pf.mac_addr);
16513 struct bnxt_vf_info *vf = &bp->vf;
16516 if (is_valid_ether_addr(vf->mac_addr)) {
16517 /* overwrite netdev dev_addr with admin VF MAC */
16518 eth_hw_addr_set(bp->dev, vf->mac_addr);
16524 eth_hw_addr_random(bp->dev);
16526 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
16534 struct pci_dev *pdev = bp->pdev;
16550 size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
16551 memcpy(bp->board_partno, &vpd_data[pos], size);
16560 size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
16561 memcpy(bp->board_serialno, &vpd_data[pos], size);
16568 struct pci_dev *pdev = bp->pdev;
16573 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
16574 return -EOPNOTSUPP;
16579 bp->flags |= BNXT_FLAG_DSN_VALID;
16585 if (!bp->db_size)
16586 return -ENODEV;
16587 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
16588 if (!bp->bar1)
16589 return -ENOMEM;
16595 netdev_info(bp->dev, "%s found at mem %lx, node addr %pM\n",
16596 board_info[bp->board_idx].name,
16597 (long)pci_resource_start(bp->pdev, 0), bp->dev->dev_addr);
16599 pcie_print_link_status(bp->pdev);
16610 return -ENODEV;
16612 if (!pdev->msix_cap) {
16613 dev_err(&pdev->dev, "MSIX capability not found, aborting\n");
16614 return -ENODEV;
16629 return -ENOMEM;
16632 bp->board_idx = ent->driver_data;
16633 bp->msg_enable = BNXT_DEF_MSG_ENABLE;
16636 if (bnxt_vf_pciid(bp->board_idx))
16637 bp->flags |= BNXT_FLAG_VF;
16641 SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port);
16647 dev->netdev_ops = &bnxt_netdev_ops;
16648 dev->stat_ops = &bnxt_stat_ops;
16649 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
16650 dev->ethtool_ops = &bnxt_ethtool_ops;
16657 mutex_init(&bp->hwrm_cmd_lock);
16658 mutex_init(&bp->link_lock);
16668 bp->flags |= BNXT_FLAG_CHIP_P5_PLUS;
16670 bp->flags |= BNXT_FLAG_CHIP_P7;
16683 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
16688 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
16695 if (bp->flags & BNXT_FLAG_UDP_GSO_CAP)
16696 dev->hw_features |= NETIF_F_GSO_UDP_L4;
16699 dev->hw_features |= NETIF_F_LRO;
16701 dev->hw_enc_features =
16707 if (bp->flags & BNXT_FLAG_UDP_GSO_CAP)
16708 dev->hw_enc_features |= NETIF_F_GSO_UDP_L4;
16709 if (bp->flags & BNXT_FLAG_CHIP_P7)
16710 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels_p7;
16712 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
16714 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
16716 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
16717 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
16718 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
16719 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
16720 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
16722 dev->hw_features |= NETIF_F_GRO_HW;
16723 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
16724 if (dev->features & NETIF_F_GRO_HW)
16725 dev->features &= ~NETIF_F_LRO;
16726 dev->priv_flags |= IFF_UNICAST_FLT;
16729 if (bp->tso_max_segs)
16730 netif_set_tso_max_segs(dev, bp->tso_max_segs);
16732 dev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
16736 init_waitqueue_head(&bp->sriov_cfg_wait);
16739 bp->gro_func = bnxt_gro_func_5730x;
16741 bp->gro_func = bnxt_gro_func_5731x;
16743 bp->gro_func = bnxt_gro_func_5750x;
16746 bp->flags |= BNXT_FLAG_DOUBLE_DB;
16750 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
16751 rc = -EADDRNOTAVAIL;
16757 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
16760 /* MTU range: 60 - FW defined max */
16761 dev->min_mtu = ETH_ZLEN;
16762 dev->max_mtu = bp->max_mtu;
16768 hw_resc = &bp->hw_resc;
16769 bp->max_fltr = hw_resc->max_rx_em_flows + hw_resc->max_rx_wm_flows +
16772 if (bp->max_fltr < BNXT_MAX_FLTR)
16773 bp->max_fltr = BNXT_MAX_FLTR;
16782 if (BNXT_VF(bp) && rc == -ENODEV) {
16783 netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
16785 netdev_err(bp->dev, "Not enough rings available.\n");
16786 rc = -ENOMEM;
16795 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
16796 bp->flags |= BNXT_FLAG_STRIP_VLAN;
16803 * limited MSIX, so we re-initialize the TX rings per TC.
16805 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
16812 dev_err(&pdev->dev, "Unable to create workqueue.\n");
16813 rc = -ENOMEM;
16828 INIT_LIST_HEAD(&bp->usr_fltr_list);
16831 bp->rss_cap |= BNXT_RSS_CAP_MULTI_RSS_CTX;
16833 dev->queue_mgmt_ops = &bnxt_queue_mgmt_ops;
16834 dev->request_ops_lock = true;
16835 dev->netmem_tx = true;
16863 kfree(bp->ptp_cfg);
16864 bp->ptp_cfg = NULL;
16865 kfree(bp->fw_health);
16866 bp->fw_health = NULL;
16870 kfree(bp->rss_indir_tbl);
16871 bp->rss_indir_tbl = NULL;
16904 pci_wake_from_d3(pdev, bp->wol);
16929 pci_disable_device(bp->pdev);
16942 rc = pci_enable_device(bp->pdev);
16944 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
16948 pci_set_master(bp->pdev);
16950 rc = -ENODEV;
16955 rc = -EBUSY;
16966 rc = -ENODEV;
16969 if (bp->fw_crash_mem)
16973 kfree(bp->ptp_cfg);
16974 bp->ptp_cfg = NULL;
16984 netdev_unlock(bp->dev);
17001 * bnxt_io_error_detected - called when PCI error is detected
17022 if (test_and_set_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
17023 netdev_err(bp->dev, "Firmware reset already in progress\n");
17037 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
17054 * bnxt_io_slot_reset - called after the pci bus has been reset.
17057 * Restart the card from scratch, as if from a cold-boot.
17071 netdev_info(bp->dev, "PCI Slot Reset\n");
17073 if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&
17074 test_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state))
17080 dev_err(&pdev->dev,
17081 "Cannot re-enable PCI device after reset.\n");
17088 * As pci_restore_state() does not re-write the BARs if the
17093 &bp->state)) {
17096 pci_write_config_dword(bp->pdev, off, 0);
17115 dev_err(&pdev->dev, "Firmware not ready\n");
17129 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
17137 * bnxt_io_resume - called when traffic can start flowing again.
17149 netdev_info(bp->dev, "PCI Slot Resume\n");