Lines Matching full:attention

930 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
931  * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
1034    follows: [0] NIG attention for function0; [1] NIG attention for
1049    NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1127    Latched timeout attention; [27] GRC Latched reserved access attention;
1141    attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1147  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1148  * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1153    latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1154    GRC Latched reserved access attention; one in d7 clears Latched
1162    as follows: [0] NIG attention for function0; [1] NIG attention for
1182    as follows: [0] NIG attention for function0; [1] NIG attention for
1202    as follows: [0] NIG attention for function0; [1] NIG attention for
1217    as follows: [0] NIG attention for function0; [1] NIG attention for
1360    Latched timeout attention; [27] GRC Latched reserved access attention;
1378    Latched timeout attention; [27] GRC Latched reserved access attention;
1396    Latched timeout attention; [27] GRC Latched reserved access attention;
1410    Latched timeout attention; [27] GRC Latched reserved access attention;
1417  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1418  * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1423  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1424  * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1427 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1444    0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1445    function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1473 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1481    NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1723    attention. bits [19:0] - address; [22:20] function; [23] reserved;
1724    [27:24] the master that caused the attention - according to the following
1729    attention. bits [19:0] - address; [22:20] function; [23] reserved;
1730    [27:24] the master that caused the attention - according to the following
1738    assert it attention output. */
2989 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2990  * corresponding PF generates config space A attention. Set by PXP. Reset by
2994 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2995  * corresponding PF generates config space B attention. Set by PXP. Reset by
3016 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
3021 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
3026 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
3030 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
3034 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
3038 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
3096 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
6292 /* storm asserts attention bits */
6298 /* mcp error attention bit */
6301 /*E1H NIG status sync attention mapped to group 4-7*/
7593 #define IGU_PF_CONF_ATTN_BIT_EN   (0x1<<3)  /* attention enable       */