1354 	u32 xmac_base;  in bnx2x_update_pfc_xmac()  local
1358 	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_update_pfc_xmac()
1384 		REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);  in bnx2x_update_pfc_xmac()
1385 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);  in bnx2x_update_pfc_xmac()
1386 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);  in bnx2x_update_pfc_xmac()
1392 	REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);  in bnx2x_update_pfc_xmac()
1393 	REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);  in bnx2x_update_pfc_xmac()
1394 	REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);  in bnx2x_update_pfc_xmac()
1398 	REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,  in bnx2x_update_pfc_xmac()
1403 	REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,  in bnx2x_update_pfc_xmac()
1710 	u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_set_xmac_rxtx()  local
1719 		pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);  in bnx2x_set_xmac_rxtx()
1720 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,  in bnx2x_set_xmac_rxtx()
1722 		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,  in bnx2x_set_xmac_rxtx()
1725 		val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);  in bnx2x_set_xmac_rxtx()
1730 		REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);  in bnx2x_set_xmac_rxtx()
1737 	u32 val, xmac_base;  in bnx2x_xmac_enable()  local
1741 	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_xmac_enable()
1758 		REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,  in bnx2x_xmac_enable()
1761 		REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);  in bnx2x_xmac_enable()
1762 		REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,  in bnx2x_xmac_enable()
1767 	REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);  in bnx2x_xmac_enable()
1770 	REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);  in bnx2x_xmac_enable()
1777 		REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);  in bnx2x_xmac_enable()
1778 		REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);  in bnx2x_xmac_enable()
1780 		REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);  in bnx2x_xmac_enable()
1795 	REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);  in bnx2x_xmac_enable()
13116 		u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_link_reset()  local
13120 			REG_WR(bp, xmac_base + XMAC_REG_CTRL,  in bnx2x_link_reset()