222 	u32 val = REG_RD(bp, reg);  in bnx2x_bits_en()
231 	u32 val = REG_RD(bp, reg);  in bnx2x_bits_dis()
254 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
269 	link_status = REG_RD(bp, params->shmem_base +  in bnx2x_check_lfa()
298 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
307 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
316 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
326 		cur_speed_cap_mask = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
339 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
349 	eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_check_lfa()
380 	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);  in bnx2x_get_epio()
383 	*en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;  in bnx2x_get_epio()
397 	gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);  in bnx2x_set_epio()
406 	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);  in bnx2x_set_epio()
1421 	cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_set_mdio_clk()
1458 	port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);  in bnx2x_is_4_port_mode()
1464 	return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);  in bnx2x_is_4_port_mode()
1485 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1490 		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1531 	if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_umac_rxtx()
1534 	val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);  in bnx2x_set_umac_rxtx()
1659 	    (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_xmac_init()
1713 	if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_xmac_rxtx()
1719 		pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);  in bnx2x_set_xmac_rxtx()
1725 		val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);  in bnx2x_set_xmac_rxtx()
1868 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);  in bnx2x_emac_enable()
1897 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_enable()
2136 	xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :  in bnx2x_update_pfc_nig()
2245 		val = REG_RD(bp, MISC_REG_RESET_REG_2);  in bnx2x_update_pfc()
2447 	u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);  in bnx2x_set_bmac_rx()
2454 	if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_bmac_rx()
2480 	init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);  in bnx2x_pbf_update()
2481 	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2486 		crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2489 	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2561 		if (REG_RD(bp, NIG_REG_PORT_SWAP))  in bnx2x_get_emac_base()
2567 		if (REG_RD(bp, NIG_REG_PORT_SWAP))  in bnx2x_get_emac_base()
2596 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2609 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2632 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2645 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2673 		chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_cl45_read()
2674 			  ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_cl45_read()
2690 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2711 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2748 		chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_cl45_write()
2749 			  ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_cl45_write()
2766 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2786 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2820 	if (REG_RD(bp, params->shmem2_base) <=  in bnx2x_eee_has_cap()
2885 		eee_mode = ((REG_RD(bp, params->shmem_base +  in bnx2x_eee_calc_timer()
3062 	board_cfg = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3070 	sfp_ctrl = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3102 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3119 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3129 		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3144 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3154 		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3160 		data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));  in bnx2x_bsc_read()
3236 		path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3240 			path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);  in bnx2x_get_warpcore_lane()
3246 		port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3250 			port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);  in bnx2x_get_warpcore_lane()
3260 			REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3265 				REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);  in bnx2x_get_warpcore_lane()
3812 	if (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
3852 		wc_lane_config = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
4004 		cfg_tap_val = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_set_10G_XFI()
4337 		cfg_pin = (REG_RD(bp, shmem_base +  in bnx2x_get_mod_abs_int_cfg()
4414 		serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_runtime()
4477 	cfg_pin = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e3_set_transmitter()
4498 	serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_init()
4813 	vars->link_status = REG_RD(bp, params->shmem_base +  in bnx2x_link_status_update()
4823 		vars->eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_link_status_update()
4833 	media_types = REG_RD(bp, sync_offset);  in bnx2x_link_status_update()
4851 	vars->aeu_int_mask = REG_RD(bp, sync_offset);  in bnx2x_link_status_update()
6080 		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in bnx2x_link_int_enable()
6082 		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in bnx2x_link_int_enable()
6083 		 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),  in bnx2x_link_int_enable()
6084 		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));  in bnx2x_link_int_enable()
6086 	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in bnx2x_link_int_enable()
6087 	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in bnx2x_link_int_enable()
6100 	latch_status = REG_RD(bp,  in bnx2x_rearm_latch_signal()
6217 	spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6227 		spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6256 			md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +  in bnx2x_set_xgxs_loopback()
6785 		val = REG_RD(bp, addr) + 1;  in bnx2x_chng_link_count()
6833 		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in bnx2x_link_update()
6835 	is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +  in bnx2x_link_update()
6838 		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in bnx2x_link_update()
6840 		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));  in bnx2x_link_update()
6843 	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in bnx2x_link_update()
6844 	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in bnx2x_link_update()
7421 	if (REG_RD(bp, params->shmem_base +  in bnx2x_8073_config_init()
7779 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_get_gpio_port()
7780 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_get_gpio_port()
7794 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e1e2_set_transmitter()
7926 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_power_module()
8225 	media_types = REG_RD(bp, sync_offset);  in bnx2x_get_edc_mode()
8270 	val = REG_RD(bp, params->shmem_base +  in bnx2x_verify_sfp_module()
8535 	u32 fault_led_gpio = REG_RD(bp, params->shmem_base +  in bnx2x_set_e1e2_module_fault_led()
8568 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_set_e3_module_fault_led()
8690 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_module_detection()
8984 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8706_config_init()
9227 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_8727_hw_reset()
9228 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_8727_hw_reset()
9352 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8727_config_init()
9380 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_8727_handle_mod_abs()
10131 	    (REG_RD(bp, params->shmem2_base +  in bnx2x_848xx_cmd_hdlr()
10153 	pair_swap = REG_RD(bp, params->shmem_base +  in bnx2x_848xx_pair_swap_cfg()
10184 			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +  in bnx2x_84833_get_reset_gpios()
10197 			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +  in bnx2x_84833_get_reset_gpios()
10216 	u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +  in bnx2x_84833_hw_reset_phy()
10403 		u32 cms_enable = REG_RD(bp, params->shmem_base +  in bnx2x_848x3_config_init()
10775 				if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +  in bnx2x_848xx_set_link_led()
10856 				if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +  in bnx2x_848xx_set_link_led()
11053 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_config_init()
11292 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_link_reset()
12158 			rx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12162 			tx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12166 			rx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12170 			tx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
12189 		ext_phy_config = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_config()
12194 		ext_phy_config = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_config()
12210 	u32 switch_cfg = (REG_RD(bp, shmem_base +  in bnx2x_populate_int_phy()
12214 	chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_populate_int_phy()
12215 		((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_populate_int_phy()
12220 		phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12223 		if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)  in bnx2x_populate_int_phy()
12228 		serdes_net_if = (REG_RD(bp, shmem_base +  in bnx2x_populate_int_phy()
12310 			phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12316 			phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12424 	config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,  in bnx2x_populate_ext_phy()
12435 		u32 size = REG_RD(bp, shmem2_base);  in bnx2x_populate_ext_phy()
12456 		u32 raw_ver = REG_RD(bp, phy->ver_addr);  in bnx2x_populate_ext_phy()
12489 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12492 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12497 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12500 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12638 		media_types = REG_RD(bp, sync_offset);  in bnx2x_phy_probe()
12839 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_avoid_link_flap()
12918 	tmp_val = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12926 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
13118 		if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_link_reset()
13193 	swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);  in bnx2x_8073_common_init_phy()
13194 	swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);  in bnx2x_8073_common_init_phy()
13318 	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);  in bnx2x_8726_common_init_phy()
13361 	u32 phy_gpio_reset = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_reset_gpio()
13413 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_8727_common_init_phy()
13414 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_8727_common_init_phy()
13586 		val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);  in bnx2x_common_init_phy()
13590 	phy_ver = REG_RD(bp, shmem_base_path[0] +  in bnx2x_common_init_phy()
13622 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_check_over_curr()
13738 	    (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))  in bnx2x_check_half_open_conn()
13742 	    (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_check_half_open_conn()
13756 		if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))  in bnx2x_check_half_open_conn()
13762 	} else if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_check_half_open_conn()
13793 	cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,  in bnx2x_sfp_tx_fault_detection()
13936 		if ((REG_RD(bp, params->shmem_base +  in bnx2x_period_func()
14036 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_init_mod_abs_int()
14037 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_init_mod_abs_int()
14057 	aeu_mask = REG_RD(bp, offset);  in bnx2x_init_mod_abs_int()
14062 	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);  in bnx2x_init_mod_abs_int()