Lines Matching +full:0 +full:x10120000
17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
45 #define PIN_CFG_GPIO2_P0 0x00000003
46 #define PIN_CFG_GPIO3_P0 0x00000004
47 #define PIN_CFG_GPIO0_P1 0x00000005
48 #define PIN_CFG_GPIO1_P1 0x00000006
49 #define PIN_CFG_GPIO2_P1 0x00000007
50 #define PIN_CFG_GPIO3_P1 0x00000008
51 #define PIN_CFG_EPIO0 0x00000009
52 #define PIN_CFG_EPIO1 0x0000000a
53 #define PIN_CFG_EPIO2 0x0000000b
54 #define PIN_CFG_EPIO3 0x0000000c
55 #define PIN_CFG_EPIO4 0x0000000d
56 #define PIN_CFG_EPIO5 0x0000000e
57 #define PIN_CFG_EPIO6 0x0000000f
58 #define PIN_CFG_EPIO7 0x00000010
59 #define PIN_CFG_EPIO8 0x00000011
60 #define PIN_CFG_EPIO9 0x00000012
61 #define PIN_CFG_EPIO10 0x00000013
62 #define PIN_CFG_EPIO11 0x00000014
63 #define PIN_CFG_EPIO12 0x00000015
64 #define PIN_CFG_EPIO13 0x00000016
65 #define PIN_CFG_EPIO14 0x00000017
66 #define PIN_CFG_EPIO15 0x00000018
67 #define PIN_CFG_EPIO16 0x00000019
68 #define PIN_CFG_EPIO17 0x0000001a
69 #define PIN_CFG_EPIO18 0x0000001b
70 #define PIN_CFG_EPIO19 0x0000001c
71 #define PIN_CFG_EPIO20 0x0000001d
72 #define PIN_CFG_EPIO21 0x0000001e
73 #define PIN_CFG_EPIO22 0x0000001f
74 #define PIN_CFG_EPIO23 0x00000020
75 #define PIN_CFG_EPIO24 0x00000021
76 #define PIN_CFG_EPIO25 0x00000022
77 #define PIN_CFG_EPIO26 0x00000023
78 #define PIN_CFG_EPIO27 0x00000024
79 #define PIN_CFG_EPIO28 0x00000025
80 #define PIN_CFG_EPIO29 0x00000026
81 #define PIN_CFG_EPIO30 0x00000027
82 #define PIN_CFG_EPIO31 0x00000028
85 #define EPIO_CFG_NA 0x00000000
86 #define EPIO_CFG_EPIO0 0x00000001
87 #define EPIO_CFG_EPIO1 0x00000002
88 #define EPIO_CFG_EPIO2 0x00000003
89 #define EPIO_CFG_EPIO3 0x00000004
90 #define EPIO_CFG_EPIO4 0x00000005
91 #define EPIO_CFG_EPIO5 0x00000006
92 #define EPIO_CFG_EPIO6 0x00000007
93 #define EPIO_CFG_EPIO7 0x00000008
94 #define EPIO_CFG_EPIO8 0x00000009
95 #define EPIO_CFG_EPIO9 0x0000000a
96 #define EPIO_CFG_EPIO10 0x0000000b
97 #define EPIO_CFG_EPIO11 0x0000000c
98 #define EPIO_CFG_EPIO12 0x0000000d
99 #define EPIO_CFG_EPIO13 0x0000000e
100 #define EPIO_CFG_EPIO14 0x0000000f
101 #define EPIO_CFG_EPIO15 0x00000010
102 #define EPIO_CFG_EPIO16 0x00000011
103 #define EPIO_CFG_EPIO17 0x00000012
104 #define EPIO_CFG_EPIO18 0x00000013
105 #define EPIO_CFG_EPIO19 0x00000014
106 #define EPIO_CFG_EPIO20 0x00000015
107 #define EPIO_CFG_EPIO21 0x00000016
108 #define EPIO_CFG_EPIO22 0x00000017
109 #define EPIO_CFG_EPIO23 0x00000018
110 #define EPIO_CFG_EPIO24 0x00000019
111 #define EPIO_CFG_EPIO25 0x0000001a
112 #define EPIO_CFG_EPIO26 0x0000001b
113 #define EPIO_CFG_EPIO27 0x0000001c
114 #define EPIO_CFG_EPIO28 0x0000001d
115 #define EPIO_CFG_EPIO29 0x0000001e
116 #define EPIO_CFG_EPIO30 0x0000001f
117 #define EPIO_CFG_EPIO31 0x00000020
126 u8 part_num[16]; /* 0x104 */
128 u32 config; /* 0x114 */
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
131 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
132 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
133 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
135 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
137 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
139 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
140 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
142 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
146 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
147 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
148 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
149 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
150 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
153 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
155 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
156 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
158 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
160 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
162 #define SHARED_HW_CFG_LED_MAC1 0x00000000
163 #define SHARED_HW_CFG_LED_PHY1 0x00010000
164 #define SHARED_HW_CFG_LED_PHY2 0x00020000
165 #define SHARED_HW_CFG_LED_PHY3 0x00030000
166 #define SHARED_HW_CFG_LED_MAC2 0x00040000
167 #define SHARED_HW_CFG_LED_PHY4 0x00050000
168 #define SHARED_HW_CFG_LED_PHY5 0x00060000
169 #define SHARED_HW_CFG_LED_PHY6 0x00070000
170 #define SHARED_HW_CFG_LED_MAC3 0x00080000
171 #define SHARED_HW_CFG_LED_PHY7 0x00090000
172 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
173 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
174 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
175 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
176 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
177 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
180 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
182 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
183 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
184 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
185 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
186 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
187 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
189 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
190 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
191 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
193 #define SHARED_HW_CFG_ATC_MASK 0x80000000
194 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
195 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
197 u32 config2; /* 0x118 */
199 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
200 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
202 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
203 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
207 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
210 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
211 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
212 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
214 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
216 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
217 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
218 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
222 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
223 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
229 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
230 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
239 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
241 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
242 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
243 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
246 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
250 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
251 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
254 tl_control_0 (register 0x2800) */
255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
256 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
257 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
259 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
260 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
261 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
263 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
264 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
265 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
285 u32 config_3; /* 0x11C */
286 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
288 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
289 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
291 u32 ump_nc_si_config; /* 0x120 */
292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
307 u32 board; /* 0x124 */
308 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
309 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
310 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
313 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
319 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
322 u32 wc_lane_config; /* 0x128 */
323 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
324 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
335 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
336 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
337 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
338 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
340 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
341 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
342 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
343 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
360 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
363 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
364 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
367 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
368 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
371 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
372 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
373 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
375 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
377 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
381 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
382 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
383 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
385 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
387 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
391 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
392 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
403 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
410 u32 pf_config; /* 0x158 */
411 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
412 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
418 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
419 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
421 u32 vf_config; /* 0x15C */
422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
423 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
428 u32 mf_pci_id; /* 0x160 */
429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
433 u32 sfp_ctrl; /* 0x164 */
434 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
435 #define PORT_HW_CFG_TX_LASER_SHIFT 0
436 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
437 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
438 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
439 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
440 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
443 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
449 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
453 u32 e3_sfp_ctrl; /* 0x168 */
454 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
455 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
463 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
468 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
475 u32 e3_cmn_pin_cfg; /* 0x16C */
476 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
477 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
481 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
488 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
493 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
494 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
501 u32 e3_cmn_pin_cfg1; /* 0x170 */
502 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
503 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
506 u32 generic_features; /* 0x174 */
507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
512 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
513 * LOM recommended and tested value is 0xBEB2. Using a different
516 u32 sfi_tap_values; /* 0x178 */
517 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
518 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
521 * value is 0x2. LOM recommended and tested value is 0x2. Using a
524 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
527 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
531 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
535 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
538 u32 reserved0[5]; /* 0x17c */
540 u32 aeu_int_mask; /* 0x190 */
542 u32 media_type; /* 0x194 */
543 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
544 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
546 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
549 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
557 u16 xgxs_config_rx[4]; /* 0x198 */
558 u16 xgxs_config_tx[4]; /* 0x1A0 */
562 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
563 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
572 u32 Reserved1[49]; /* 0x1C0 */
574 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
576 u32 xgbt_phy_cfg; /* 0x284 */
577 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
578 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
580 u32 default_cfg; /* 0x288 */
581 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
582 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
583 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
584 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
585 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
586 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
588 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
590 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
591 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
592 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
593 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
595 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
597 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
598 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
599 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
600 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
602 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
604 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
605 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
606 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
607 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
615 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
617 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
618 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
619 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
620 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
621 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
622 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
623 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
624 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
625 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
626 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
631 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
632 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
633 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
634 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
635 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
636 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
637 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
641 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
643 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
644 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
647 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
649 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
650 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
653 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
655 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
656 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
657 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
658 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
659 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
660 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
663 u32 speed_capability_mask2; /* 0x28C */
664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
666 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
677 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
678 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
679 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
680 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
681 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
682 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
691 u32 multi_phy_config; /* 0x290 */
692 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
693 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
694 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
695 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
696 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
697 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
698 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
702 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
704 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
705 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
709 u32 external_phy_config2; /* 0x294 */
710 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
711 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
728 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
729 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
730 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
731 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
732 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200
735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
741 u16 xgxs_config2_rx[4]; /* 0x296 */
742 u16 xgxs_config2_tx[4]; /* 0x2A0 */
745 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
746 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
748 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
750 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
752 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
754 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
755 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
756 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
757 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
759 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
763 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
764 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
765 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
769 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
770 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
786 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
787 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
788 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
789 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200
793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
797 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
800 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
802 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
803 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
804 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
805 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
809 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
810 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
811 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
812 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
813 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
814 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
815 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
816 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
817 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
818 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
822 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
823 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
824 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
825 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
826 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
827 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
828 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
829 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
830 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
833 u32 backup_mac_upper; /* 0x2B4 */
834 u32 backup_mac_lower; /* 0x2B8 */
844 u32 config; /* 0x450 */
845 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
849 0x00000002
851 0x00000000
853 0x00000002
855 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
856 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
857 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
859 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
863 high means only SF, 0 is according to CLP configuration */
864 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
866 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
867 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
868 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
869 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
870 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
871 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
872 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
873 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
877 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
881 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
890 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
893 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
894 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
895 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
896 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
897 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
898 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
899 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
900 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
901 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
902 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
903 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
904 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
905 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
906 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
907 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
908 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
909 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
910 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
911 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
913 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
914 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
915 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
916 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
917 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
918 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
919 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
920 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
921 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
922 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
923 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
924 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
925 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
926 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
927 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
928 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
930 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
931 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
932 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
934 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
935 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
936 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
938 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
940 #define PORT_FEATURE_WOL_ENABLED 0x01000000
941 #define PORT_FEATURE_MBA_ENABLED 0x02000000
942 #define PORT_FEATURE_MFW_ENABLED 0x04000000
945 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
946 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
947 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
951 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
954 0x00000000
956 0x20000000
957 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
958 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
962 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
963 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
964 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
965 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
966 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
967 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
968 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
969 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
970 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
973 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
974 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
975 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
976 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
977 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
978 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
979 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
980 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
982 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
985 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
986 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
987 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
988 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
989 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
990 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
996 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
997 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
998 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
999 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
1000 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
1001 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
1002 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
1003 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
1004 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
1005 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
1006 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
1007 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
1008 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
1009 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
1011 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
1013 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1014 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1015 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1016 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1017 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
1019 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1020 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
1021 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
1022 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
1023 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
1024 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
1025 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
1026 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
1027 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
1029 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
1030 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
1031 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
1034 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
1035 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1036 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1039 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
1040 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1041 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1042 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1043 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1046 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1055 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1056 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1057 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1058 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1059 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1060 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1061 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1062 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1063 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1064 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1065 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1066 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1067 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1070 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1073 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1075 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1076 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1077 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1079 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1081 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1082 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1083 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1084 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1085 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1086 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1087 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1088 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1089 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1091 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1093 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1094 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1095 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1096 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1097 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1105 u32 link_config2; /* 0x47C */
1109 u32 mfw_wol_link_cfg2; /* 0x480 */
1113 u32 eee_power_mode; /* 0x484 */
1114 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1115 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1116 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1117 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1118 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1119 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1122 u32 Reserved2[16]; /* 0x488 */
1153 #define FUNC_0 0
1165 #define VN_0 0
1189 #define MFW_TRACE_SIGNATURE 0x54524342
1199 #define LINK_STATUS_NONE (0<<0)
1200 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1201 #define LINK_STATUS_LINK_UP 0x00000001
1202 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1203 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1220 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1221 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1223 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1224 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1225 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1227 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1228 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1229 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1230 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1231 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1232 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1233 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1235 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1236 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1238 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1239 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1241 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1242 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1247 #define LINK_STATUS_SERDES_LINK 0x00100000
1249 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1250 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1251 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1252 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1254 #define LINK_STATUS_PFC_ENABLED 0x20000000
1256 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1257 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1272 #define DRV_MSG_CODE_MASK 0xffff0000
1273 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1274 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1275 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1276 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1277 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1278 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1279 #define DRV_MSG_CODE_DCC_OK 0x30000000
1280 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1281 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1282 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1283 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1284 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1285 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1286 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1287 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1288 #define DRV_MSG_CODE_OEM_OK 0x00010000
1289 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
1290 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
1291 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
1297 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1298 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1299 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1300 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1301 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1302 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1303 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1304 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1305 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1306 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1308 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1309 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1310 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1312 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1314 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1315 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1316 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1317 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1318 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1320 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1321 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1323 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1325 #define DRV_MSG_CODE_RMMOD 0xdb000000
1326 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
1328 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1329 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1330 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1332 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1334 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1335 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1337 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1338 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1339 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1340 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1342 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1345 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1346 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1348 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1350 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1351 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1354 #define FW_MSG_CODE_MASK 0xffff0000
1355 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1356 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1357 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1358 /* Load common chip is supported from bc 6.0.0 */
1359 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1360 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1362 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1363 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1364 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1365 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1366 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1367 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1368 #define FW_MSG_CODE_DCC_DONE 0x30100000
1369 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1370 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1371 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1372 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1373 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1374 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1375 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1376 #define FW_MSG_CODE_NO_KEY 0x80f00000
1377 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1378 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1379 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1380 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1381 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1382 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1383 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1384 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1385 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1386 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1387 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1389 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1390 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1391 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1392 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1393 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1395 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1396 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1398 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1400 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000
1402 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1403 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1405 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1407 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1408 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1409 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1410 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1412 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1417 #define DRV_PULSE_SEQ_MASK 0x00007fff
1418 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1423 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1431 #define MCP_PULSE_SEQ_MASK 0x00007fff
1432 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1435 #define MCP_EVENT_MASK 0xffff0000
1436 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1442 #define DRV_STATUS_PMF 0x00000001
1443 #define DRV_STATUS_VF_DISABLED 0x00000002
1444 #define DRV_STATUS_SET_MF_BW 0x00000004
1445 #define DRV_STATUS_LINK_EVENT 0x00000008
1447 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
1448 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
1449 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
1451 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
1453 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1454 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1455 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1456 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1457 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1458 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1459 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1461 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1462 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1463 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1464 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1465 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1466 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1467 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1469 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1471 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1474 #define VIRT_MAC_SIGN_MASK 0xffff0000
1475 #define VIRT_MAC_SIGNATURE 0x564d0000
1498 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1500 #define SHARED_MF_CLP_EXIT 0x00000001
1502 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1509 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1510 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1521 /* function 0 of each port cannot be hidden */
1522 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1524 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1525 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1526 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1527 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1528 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1532 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1533 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1536 /* 0 - low priority, 3 - high priority */
1537 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1539 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1542 /* value range - 0..100, increments in 100Mbps */
1543 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1545 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1546 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1548 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1551 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1552 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1555 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1558 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1559 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1563 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1567 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1568 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1569 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1571 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1572 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1579 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1587 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
1588 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1589 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1590 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1591 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1592 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1593 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
1608 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1618 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1619 /* 0x8*2*2=0x20 */
1622 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1627 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1628 }; /* 0x224 */
1635 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1636 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1639 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1640 #define SHR_MEM_VALIDITY_MB 0x00200000
1641 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1642 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1644 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1645 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1646 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1647 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1649 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1650 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1651 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1652 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1653 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1654 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1656 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1658 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1661 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1662 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1664 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1669 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1672 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1675 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1731 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1737 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1743 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1760 } while (0)
1779 #define FCOE_APP_IDX 0
1799 #define DCBX_PFC_PRI_0 0x01
1800 #define DCBX_PFC_PRI_1 0x02
1801 #define DCBX_PFC_PRI_2 0x04
1802 #define DCBX_PFC_PRI_3 0x08
1803 #define DCBX_PFC_PRI_4 0x10
1804 #define DCBX_PFC_PRI_5 0x20
1805 #define DCBX_PFC_PRI_6 0x40
1806 #define DCBX_PFC_PRI_7 0x80
1815 #define DCBX_PFC_PRI_0 0x01
1816 #define DCBX_PFC_PRI_1 0x02
1817 #define DCBX_PFC_PRI_2 0x04
1818 #define DCBX_PFC_PRI_3 0x08
1819 #define DCBX_PFC_PRI_4 0x10
1820 #define DCBX_PFC_PRI_5 0x20
1821 #define DCBX_PFC_PRI_6 0x40
1822 #define DCBX_PFC_PRI_7 0x80
1831 #define DCBX_APP_ENTRY_VALID 0x01
1832 #define DCBX_APP_ENTRY_SF_MASK 0xF0
1834 #define DCBX_APP_SF_ETH_TYPE 0x10
1835 #define DCBX_APP_SF_PORT 0x20
1836 #define DCBX_APP_SF_UDP 0x40
1837 #define DCBX_APP_SF_DEFAULT 0x80
1840 #define DCBX_APP_ENTRY_VALID 0x01
1841 #define DCBX_APP_ENTRY_SF_MASK 0xF0
1843 #define DCBX_APP_ENTRY_VALID 0x01
1844 #define DCBX_APP_SF_ETH_TYPE 0x10
1845 #define DCBX_APP_SF_PORT 0x20
1846 #define DCBX_APP_SF_UDP 0x40
1847 #define DCBX_APP_SF_DEFAULT 0x80
1888 #define LLDP_TX_ONLY 0x01
1889 #define LLDP_RX_ONLY 0x02
1890 #define LLDP_TX_RX 0x03
1891 #define LLDP_DISABLED 0x04
1898 #define LLDP_TX_ONLY 0x01
1899 #define LLDP_RX_ONLY 0x02
1900 #define LLDP_TX_RX 0x03
1901 #define LLDP_DISABLED 0x04
1934 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1935 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1936 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1937 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1938 #define DCBX_ETS_RECO_VALID 0x00000010
1939 #define DCBX_ETS_WILLING 0x00000020
1940 #define DCBX_PFC_WILLING 0x00000040
1941 #define DCBX_APP_WILLING 0x00000080
1942 #define DCBX_VERSION_CEE 0x00000100
1943 #define DCBX_VERSION_IEEE 0x00000200
1944 #define DCBX_DCBX_ENABLED 0x00000400
1945 #define DCBX_CEE_VERSION_MASK 0x0000f000
1947 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1956 #define DCBX_ETS_TLV_RX 0x00000001
1957 #define DCBX_PFC_TLV_RX 0x00000002
1958 #define DCBX_APP_TLV_RX 0x00000004
1959 #define DCBX_ETS_RX_ERROR 0x00000010
1960 #define DCBX_PFC_RX_ERROR 0x00000020
1961 #define DCBX_APP_RX_ERROR 0x00000040
1962 #define DCBX_ETS_REM_WILLING 0x00000100
1963 #define DCBX_PFC_REM_WILLING 0x00000200
1964 #define DCBX_APP_REM_WILLING 0x00000400
1965 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1966 #define DCBX_REMOTE_MIB_VALID 0x00002000
1976 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1977 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1978 #define DCBX_LOCAL_APP_ERROR 0x00000004
1979 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1980 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1981 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1982 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1983 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1984 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1996 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
1997 #define REQ_DUPLEX_PHY0_SHIFT 0
1998 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
2001 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
2002 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
2003 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
2006 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
2007 #define REQ_LINE_SPD_PHY0_SHIFT 0
2008 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
2012 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
2013 #define REQ_FC_AUTO_ADV0_SHIFT 0
2014 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
2016 #define LFA_LINK_FLAP_REASON_OFFSET 0
2017 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
2018 #define LFA_LINK_DOWN 0x1
2019 #define LFA_LOOPBACK_ENABLED 0x2
2020 #define LFA_DUPLEX_MISMATCH 0x3
2021 #define LFA_MFW_IS_TOO_OLD 0x4
2022 #define LFA_LINK_SPEED_MISMATCH 0x5
2023 #define LFA_FLOW_CTRL_MISMATCH 0x6
2024 #define LFA_SPEED_CAP_MISMATCH 0x7
2025 #define LFA_DCC_LFA_DISABLED 0x8
2026 #define LFA_EEE_MISMATCH 0x9
2029 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
2032 #define LINK_FLAP_COUNT_MASK 0x00ff0000
2034 #define LFA_FLAGS_MASK 0xff000000
2040 * on driver unload driver value of 0x0 will be set.
2043 #define DRV_VER_NOT_LOADED 0
2046 #define DRV_PERS_ETHERNET 0
2057 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
2058 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
2060 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
2064 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
2065 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
2067 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
2071 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
2072 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
2074 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
2078 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
2079 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
2083 CURR_CFG_MET_NONE = 0, /* default config */
2113 #define FIRST_DUMP_VALID (1 << 0)
2117 #define ENABLE_ALL_TRIGGERS (0x7fffffff)
2128 u32 size; /* 0x0000 */
2130 u32 dcc_support; /* 0x0004 */
2131 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2132 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2133 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2134 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2135 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2136 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2138 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2141 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2144 u32 mf_cfg_addr; /* 0x0010 */
2145 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2147 struct fw_flr_mb flr_mb; /* 0x0014 */
2148 u32 dcbx_lldp_params_offset; /* 0x0028 */
2149 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2150 u32 dcbx_neg_res_offset; /* 0x002c */
2151 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2152 u32 dcbx_remote_mib_offset; /* 0x0030 */
2153 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2160 u32 other_shmem_base_addr; /* 0x0034 */
2161 u32 other_shmem2_base_addr; /* 0x0038 */
2166 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2172 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2174 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2175 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2182 * bits 0-2 - function number / instance of driver to perform request
2186 u32 edebug_driver_if[2]; /* 0x0068 */
2191 u32 nvm_retain_bitmap_addr; /* 0x0070 */
2194 u32 afex_driver_support; /* 0x0074 */
2195 #define SHMEM_AFEX_VERSION_MASK 0x100f
2196 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2197 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2205 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2206 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2208 u32 swim_base_addr; /* 0x0108 */
2219 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2220 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2221 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2237 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2240 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2241 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2242 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2243 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2244 #define DRV_FLAGS_MTU_MASK 0xffff0000
2260 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2261 #define DRV_INFO_CONTROL_VER_SHIFT 0
2262 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2270 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2280 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2284 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2285 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2287 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2288 #define SHMEM_EEE_100M_ADV (1<<0)
2292 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2294 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2295 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2296 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2297 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2305 u32 reserved2; /* Offset 0x148 */
2306 u32 reserved3; /* Offset 0x14C */
2307 u32 reserved4; /* Offset 0x150 */
2308 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2309 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
2310 #define LINK_ATTR_84858 0x00000002
2311 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
2313 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
2314 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
2315 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
2318 u32 link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
2319 #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */
2321 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2326 /* We use indication for each PF (0..3) */
2328 union { /* For various OEMs */ /* Offset 0x1a0 */
2330 #define STORAGE_BOOT_PROG_MASK 0x000000FF
2331 #define STORAGE_BOOT_PROG_NONE 0x00000000
2332 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
2333 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
2334 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
2335 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
2336 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
2337 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
2338 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
2339 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
2340 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
2346 /* For PCP values 0-3 use the map lower */
2347 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
2348 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
2350 u32 c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
2353 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
2354 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
2356 u32 c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
2359 u32 c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
2362 u32 fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
2365 enum curr_cfg_method_e curr_cfg; /* 0x1dc */
2367 /* Storm FW version, shold be kept in the format 0xMMmmbbdd:
2370 u32 netproc_fw_ver; /* 0x1e0 */
2373 u32 clp_ver; /* 0x1e4 */
2375 u32 pcie_bus_num; /* 0x1e8 */
2377 u32 sriov_switch_mode; /* 0x1ec */
2378 #define SRIOV_SWITCH_MODE_NONE 0x0
2379 #define SRIOV_SWITCH_MODE_VEB 0x1
2380 #define SRIOV_SWITCH_MODE_VEPA 0x2
2382 u8 rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
2384 u32 img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
2386 u32 mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
2388 u32 os_driver_state[E2_FUNC_MAX]; /* 0x208 */
2389 #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
2395 struct mdump_driver_info drv_info; /* 0x218 */
3029 #define BCM_5710_FW_ENGINEERING_VERSION 0
3059 #define DMAE_COMMAND_SRC (0x1<<0)
3060 #define DMAE_COMMAND_SRC_SHIFT 0
3061 #define DMAE_COMMAND_DST (0x3<<1)
3063 #define DMAE_COMMAND_C_DST (0x1<<3)
3065 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
3067 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
3069 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
3071 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
3073 #define DMAE_COMMAND_PORT (0x1<<11)
3075 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
3077 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
3079 #define DMAE_COMMAND_DST_RESET (0x1<<14)
3081 #define DMAE_COMMAND_E1HVN (0x3<<15)
3083 #define DMAE_COMMAND_DST_VN (0x3<<17)
3085 #define DMAE_COMMAND_C_FUNC (0x1<<19)
3087 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
3089 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
3097 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
3098 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
3099 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
3101 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
3103 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
3105 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
3107 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
3113 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
3114 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
3115 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
3117 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
3119 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
3121 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
3123 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
3160 #define DOORBELL_HDR_RX (0x1<<0)
3161 #define DOORBELL_HDR_RX_SHIFT 0
3162 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
3164 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
3166 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
3177 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3178 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3179 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3181 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3187 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3188 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3189 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3191 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3257 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3258 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3259 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3261 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3263 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3265 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3271 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3272 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3273 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3275 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3277 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3279 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3290 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3291 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3292 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3294 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3296 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3298 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3300 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3311 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3312 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3313 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3315 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3317 #define IGU_REGULAR_BUPDATE (0x1<<24)
3319 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3321 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3323 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3325 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3327 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3356 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3357 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3358 #define IGU_CTRL_REG_FID (0x7F<<12)
3360 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3362 #define IGU_CTRL_REG_TYPE (0x1<<20)
3364 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3397 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3398 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3399 #define PARSING_FLAGS_VLAN (0x1<<1)
3401 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3403 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3405 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3407 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3409 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3411 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3413 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3415 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3417 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3419 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3421 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3474 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3475 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3476 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3478 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3480 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3482 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3495 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3496 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3497 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3499 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3637 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3638 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3639 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3641 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3643 #define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1<<3)
3645 #define CLIENT_INIT_RX_DATA_RESERVED5 (0xF<<4)
3675 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3676 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3677 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3679 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3681 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3683 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3685 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3687 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3689 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3718 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3719 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3720 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3722 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3724 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3726 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
3816 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3817 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3818 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3820 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3822 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3824 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3975 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3976 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3977 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3979 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
4000 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
4001 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
4002 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
4004 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
4006 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
4008 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
4010 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
4012 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
4015 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
4016 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
4017 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
4019 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
4021 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
4023 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
4025 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
4049 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
4050 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
4051 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
4053 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
4059 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
4060 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
4061 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
4063 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
4065 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
4067 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
4069 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
4071 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
4073 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
4150 #define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
4151 #define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
4152 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
4167 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
4168 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
4169 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
4171 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
4173 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
4242 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
4243 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4244 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
4246 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
4248 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
4250 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
4252 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
4254 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
4256 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
4258 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
4260 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
4262 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
4288 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4289 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4290 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4292 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4297 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4298 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4299 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4362 #define SPE_HDR_CID (0xFFFFFF<<0)
4363 #define SPE_HDR_CID_SHIFT 0
4364 #define SPE_HDR_CMD_ID (0xFF<<24)
4367 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4368 #define SPE_HDR_CONN_TYPE_SHIFT 0
4369 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4477 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4478 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4479 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4481 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4483 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4485 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4487 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4489 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4504 #define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
4505 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4506 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
4508 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4510 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4512 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
4521 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4522 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4523 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4525 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4527 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4529 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4531 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4534 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4535 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4536 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4538 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4540 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4542 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4544 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4546 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4548 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4564 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
4565 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4566 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4568 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4570 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4572 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4581 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
4582 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4583 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
4585 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
4587 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
4589 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
4591 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
4593 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
4596 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
4597 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
4598 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
4602 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
4603 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4604 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
4606 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
4608 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
4610 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
4612 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
4614 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
4616 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
4696 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4697 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4698 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4700 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4702 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4704 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4706 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4776 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4777 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4778 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4780 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4782 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4784 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4786 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4788 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4841 * FCoE RX statistics parameters section#0
4925 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4926 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4927 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4929 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4931 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4933 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
5170 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5171 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5172 #define E2_INTEG_DATA_LB_TX (0x1<<1)
5174 #define E2_INTEG_DATA_COS_TX (0x1<<2)
5176 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5178 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5180 #define E2_INTEG_DATA_RESERVED (0x7<<5)
5190 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5191 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5192 #define E2_INTEG_DATA_LB_TX (0x1<<1)
5194 #define E2_INTEG_DATA_COS_TX (0x1<<2)
5196 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5198 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5200 #define E2_INTEG_DATA_RESERVED (0x7<<5)
5479 #define FW_VERSION_OPTIMIZED (0x1<<0)
5480 #define FW_VERSION_OPTIMIZED_SHIFT 0
5481 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5483 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5485 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5503 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5504 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5505 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5507 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5509 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5515 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5516 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5517 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5519 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5521 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5793 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5794 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5795 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5797 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5799 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5801 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)