Lines Matching +full:- +full:l
3 * Copyright (c) 2004-2014 Broadcom Corporation
4 * Copyright (c) 2014-2015 QLogic Corporation
71 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
72 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
73 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
74 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
75 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
76 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
77 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
78 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
79 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
80 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
81 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
82 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
83 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
84 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
85 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
86 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
87 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
88 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
89 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
90 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
91 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
92 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
93 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
94 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
95 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
96 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
97 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
98 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
99 #define STATUS_ATTN_BITS_EPB_ERROR (1L<<30)
100 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
387 #define BNX2_PCICFG_MSI_CONTROL_ENABLE (1L<<16)
390 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
391 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
392 #define BNX2_PCICFG_MISC_CONFIG_RESERVED1 (1L<<4)
393 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
394 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
395 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
396 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
397 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
398 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1L<<10)
399 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1L<<11)
400 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1L<<12)
406 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
407 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
408 #define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
409 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
411 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
412 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
413 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
414 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
415 #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE (1L<<8)
419 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
420 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
421 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
422 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
423 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
424 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
425 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
426 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
428 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
429 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
431 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
432 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
433 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
434 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
435 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
437 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
438 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
439 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
440 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
441 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
442 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
443 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 (1L<<17)
444 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
445 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 (1L<<19)
454 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
455 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
456 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
466 #define BNX2_PCICFG_DEVICE_STATUS_NO_PEND ((1L<<5)<<16)
474 #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN (1L<<31)
482 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
483 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
484 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
485 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
486 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
487 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
488 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
489 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
491 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
492 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
493 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
494 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
495 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
496 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
497 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
498 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
503 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
504 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
505 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
506 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
507 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
508 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
509 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
510 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
511 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
512 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
513 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
514 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
515 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
516 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
517 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
518 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
519 #define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
520 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
521 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
522 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
524 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
525 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
526 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
527 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
528 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
529 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
530 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
531 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
532 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
533 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
534 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
535 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
536 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
537 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
538 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
539 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
542 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
543 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
544 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
545 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
546 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
547 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
548 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
550 #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI (1L<<16)
556 #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
557 #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
558 #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
560 #define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
561 #define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
579 #define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
583 #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
587 #define BNX2_PCI_VPD_ADDR_FLAG_SL 0L
589 #define BNX2_PCI_VPD_ADDR_FLAG_WR (1L<<15)
606 #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
607 #define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
608 #define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
609 #define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
610 #define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
611 #define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
612 #define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
613 #define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
614 #define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
615 #define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
616 #define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
617 #define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
618 #define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
619 #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
620 #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
621 #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
624 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
625 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
626 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
627 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
628 #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP (1L<<8)
631 #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
632 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
633 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
637 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0 (1L<<25)
639 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0 (1L<<28)
644 #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
645 #define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
646 #define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
647 #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
648 #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
649 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
652 #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI (1L<<9)
656 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
657 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
676 #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ (1L<<27)
704 #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1L<<5)
708 #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1L<<5)
711 #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1L<<15)
715 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1L<<0)
716 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (1L<<0)
718 #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT (1L<<9)
721 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5L<<12)
722 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6L<<12)
724 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 (1L<<15)
725 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 (2L<<15)
727 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5L<<18)
728 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6L<<18)
730 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1L<<21)
731 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2L<<21)
736 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1L<<4)
759 #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
760 #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
761 #define BNX2_MISC_COMMAND_SW_RESET (1L<<4)
762 #define BNX2_MISC_COMMAND_POR_RESET (1L<<5)
763 #define BNX2_MISC_COMMAND_HD_RESET (1L<<6)
764 #define BNX2_MISC_COMMAND_CMN_SW_RESET (1L<<7)
765 #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
766 #define BNX2_MISC_COMMAND_CS16_ERR (1L<<9)
769 #define BNX2_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
770 #define BNX2_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
771 #define BNX2_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
772 #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
773 #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
774 #define BNX2_MISC_COMMAND_PCIE_DIS (1L<<28)
777 #define BNX2_MISC_CFG_GRC_TMOUT (1L<<0)
779 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
780 #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
781 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
782 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
783 #define BNX2_MISC_CFG_BIST_EN (1L<<3)
784 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
785 #define BNX2_MISC_CFG_RESERVED5_TE (1L<<5)
786 #define BNX2_MISC_CFG_RESERVED6_TE (1L<<6)
787 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
789 #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
790 #define BNX2_MISC_CFG_LEDMODE_PHY1_TE (1L<<8)
791 #define BNX2_MISC_CFG_LEDMODE_PHY2_TE (2L<<8)
792 #define BNX2_MISC_CFG_LEDMODE_PHY3_TE (3L<<8)
793 #define BNX2_MISC_CFG_LEDMODE_PHY4_TE (4L<<8)
794 #define BNX2_MISC_CFG_LEDMODE_PHY5_TE (5L<<8)
795 #define BNX2_MISC_CFG_LEDMODE_PHY6_TE (6L<<8)
796 #define BNX2_MISC_CFG_LEDMODE_PHY7_TE (7L<<8)
797 #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11)
798 #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12)
800 #define BNX2_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
801 #define BNX2_MISC_CFG_LEDMODE_PHY1_XI (1L<<8)
802 #define BNX2_MISC_CFG_LEDMODE_PHY2_XI (2L<<8)
803 #define BNX2_MISC_CFG_LEDMODE_PHY3_XI (3L<<8)
804 #define BNX2_MISC_CFG_LEDMODE_MAC2_XI (4L<<8)
805 #define BNX2_MISC_CFG_LEDMODE_PHY4_XI (5L<<8)
806 #define BNX2_MISC_CFG_LEDMODE_PHY5_XI (6L<<8)
807 #define BNX2_MISC_CFG_LEDMODE_PHY6_XI (7L<<8)
808 #define BNX2_MISC_CFG_LEDMODE_MAC3_XI (8L<<8)
809 #define BNX2_MISC_CFG_LEDMODE_PHY7_XI (9L<<8)
810 #define BNX2_MISC_CFG_LEDMODE_PHY8_XI (10L<<8)
811 #define BNX2_MISC_CFG_LEDMODE_PHY9_XI (11L<<8)
812 #define BNX2_MISC_CFG_LEDMODE_MAC4_XI (12L<<8)
813 #define BNX2_MISC_CFG_LEDMODE_PHY10_XI (13L<<8)
814 #define BNX2_MISC_CFG_LEDMODE_PHY11_XI (14L<<8)
815 #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8)
816 #define BNX2_MISC_CFG_PORT_SELECT_XI (1L<<13)
817 #define BNX2_MISC_CFG_PARITY_MODE_XI (1L<<14)
821 #define BNX2_MISC_ID_BOND_ID_X (0L<<0)
822 #define BNX2_MISC_ID_BOND_ID_C (3L<<0)
823 #define BNX2_MISC_ID_BOND_ID_S (12L<<0)
829 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
830 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
831 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
832 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
833 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
834 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
835 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
836 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
837 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
838 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
839 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
840 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
841 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
842 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
843 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
844 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
845 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
846 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
847 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
848 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
849 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
850 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
851 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
852 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
853 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
854 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
855 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
856 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
857 #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
861 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
862 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
863 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
864 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
865 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
866 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
867 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
868 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
869 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
870 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
871 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
872 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
873 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
874 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
875 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
876 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
877 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
878 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
879 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
880 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
881 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
882 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
883 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
884 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
885 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
886 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
887 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
888 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
889 #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
893 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
894 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
895 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
896 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
897 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
898 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
899 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
900 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
901 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
902 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
903 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
904 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
905 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
906 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
907 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
908 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
909 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
910 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
911 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
912 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
913 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
914 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
915 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
916 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
917 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
918 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
919 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
920 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
921 #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
926 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
927 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
928 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
929 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
930 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
931 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
932 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
933 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
935 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
936 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
938 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
939 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
940 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
941 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
943 #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
945 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
946 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
947 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
948 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
949 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
951 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
952 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17)
953 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18)
954 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19)
956 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17)
959 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27)
982 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
983 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
984 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
985 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
986 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
987 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
988 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
989 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
990 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
991 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
992 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
993 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
994 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
995 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
996 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
997 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
998 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
999 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
1000 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
1001 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
1002 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1003 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1004 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1005 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1006 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1007 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1008 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1009 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
1010 #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1072 #define BNX2_MISC_RESERVED2_PCIE_DIS (1L<<0)
1073 #define BNX2_MISC_RESERVED2_LINK_IN_L23 (1L<<1)
1076 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
1077 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
1078 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
1079 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
1080 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
1081 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
1082 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
1083 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
1084 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8)
1085 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9)
1087 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
1088 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
1089 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
1090 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
1093 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
1094 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
1098 #define BNX2_MISC_SMB_IN_RDY (1L<<8)
1099 #define BNX2_MISC_SMB_IN_DONE (1L<<9)
1100 #define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
1110 #define BNX2_MISC_SMB_OUT_RDY (1L<<8)
1111 #define BNX2_MISC_SMB_OUT_START (1L<<9)
1112 #define BNX2_MISC_SMB_OUT_LAST (1L<<10)
1113 #define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
1114 #define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
1115 #define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
1118 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1119 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
1120 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
1121 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
1122 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
1123 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
1124 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20)
1125 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
1127 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
1128 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
1129 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
1130 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
1131 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
1152 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
1153 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
1154 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
1155 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
1156 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
1157 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
1158 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
1159 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
1160 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
1161 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
1162 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
1163 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
1164 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
1165 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
1166 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
1167 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
1168 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
1169 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
1170 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
1171 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
1172 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
1173 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
1174 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
1175 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
1176 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
1177 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
1178 #define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
1179 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
1180 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
1181 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
1182 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
1183 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
1184 #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
1185 #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1)
1186 #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2)
1187 #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3)
1188 #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4)
1189 #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5)
1190 #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6)
1191 #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7)
1192 #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8)
1193 #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9)
1194 #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10)
1195 #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11)
1196 #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12)
1197 #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13)
1198 #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14)
1199 #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15)
1200 #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16)
1201 #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17)
1202 #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18)
1203 #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19)
1204 #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20)
1205 #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21)
1206 #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22)
1207 #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23)
1208 #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24)
1209 #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25)
1210 #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26)
1211 #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27)
1212 #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28)
1213 #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29)
1214 #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30)
1215 #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31)
1218 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1219 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1220 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1221 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1222 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1223 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1224 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1225 #define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1226 #define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1227 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1228 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1229 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1230 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1231 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1232 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1233 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1234 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1235 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1236 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1237 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1238 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1239 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1240 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1241 #define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1242 #define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1243 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1244 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1245 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1246 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1247 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1248 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1249 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1250 #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
1251 #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2)
1252 #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3)
1253 #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4)
1254 #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5)
1255 #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6)
1256 #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7)
1257 #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8)
1258 #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9)
1259 #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10)
1260 #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11)
1261 #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12)
1262 #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13)
1263 #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14)
1264 #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15)
1265 #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16)
1266 #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17)
1267 #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18)
1268 #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19)
1269 #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20)
1270 #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21)
1271 #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22)
1272 #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23)
1273 #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24)
1274 #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25)
1275 #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26)
1276 #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27)
1277 #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28)
1278 #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29)
1281 #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1282 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1283 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1284 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1285 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1286 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1287 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1288 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1289 #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1290 #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
1291 #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1)
1292 #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2)
1293 #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3)
1294 #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4)
1295 #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5)
1296 #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6)
1306 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
1307 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
1308 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
1309 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
1310 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
1311 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
1312 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
1313 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
1314 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
1315 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
1316 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
1317 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
1318 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
1319 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
1320 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
1321 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
1323 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
1324 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4)
1325 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4)
1326 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4)
1327 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4)
1328 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4)
1329 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4)
1330 #define BNX2_MISC_VREG_CONTROL_2_5_NOM (7L<<4)
1331 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4)
1332 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4)
1333 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4)
1334 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4)
1335 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4)
1336 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4)
1337 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4)
1338 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4)
1340 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
1341 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8)
1342 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8)
1343 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8)
1344 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8)
1345 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8)
1346 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8)
1347 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8)
1348 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8)
1349 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8)
1350 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8)
1351 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8)
1352 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8)
1353 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8)
1354 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8)
1355 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8)
1361 #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
1362 #define BNX2_MISC_GP_HW_CTL0_RMII_MODE (1L<<1)
1363 #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2)
1364 #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3)
1365 #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4)
1366 #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5)
1367 #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6)
1369 #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7)
1370 #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8)
1371 #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9)
1372 #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10)
1374 #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11)
1375 #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12)
1376 #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13)
1377 #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14)
1378 #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15)
1380 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
1381 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16)
1382 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16)
1383 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16)
1384 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16)
1385 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16)
1386 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20)
1387 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21)
1389 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
1390 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22)
1391 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22)
1392 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22)
1394 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
1395 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24)
1396 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24)
1397 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24)
1399 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
1400 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26)
1401 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26)
1402 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26)
1404 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
1405 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28)
1406 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28)
1407 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28)
1409 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
1410 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30)
1411 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30)
1412 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30)
1415 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
1416 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1)
1417 #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2)
1418 #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3)
1423 #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
1424 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1)
1425 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2)
1426 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3)
1431 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
1432 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
1433 #define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
1438 #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
1466 #define BNX2_MISC_CS16_ERR_ENA_PCI (1L<<0)
1467 #define BNX2_MISC_CS16_ERR_ENA_RDMA (1L<<1)
1468 #define BNX2_MISC_CS16_ERR_ENA_TDMA (1L<<2)
1469 #define BNX2_MISC_CS16_ERR_ENA_EMAC (1L<<3)
1470 #define BNX2_MISC_CS16_ERR_ENA_CTX (1L<<4)
1471 #define BNX2_MISC_CS16_ERR_ENA_TBDR (1L<<5)
1472 #define BNX2_MISC_CS16_ERR_ENA_RBDC (1L<<6)
1473 #define BNX2_MISC_CS16_ERR_ENA_COM (1L<<7)
1474 #define BNX2_MISC_CS16_ERR_ENA_CP (1L<<8)
1475 #define BNX2_MISC_CS16_ERR_STA_PCI (1L<<16)
1476 #define BNX2_MISC_CS16_ERR_STA_RDMA (1L<<17)
1477 #define BNX2_MISC_CS16_ERR_STA_TDMA (1L<<18)
1478 #define BNX2_MISC_CS16_ERR_STA_EMAC (1L<<19)
1479 #define BNX2_MISC_CS16_ERR_STA_CTX (1L<<20)
1480 #define BNX2_MISC_CS16_ERR_STA_TBDR (1L<<21)
1481 #define BNX2_MISC_CS16_ERR_STA_RBDC (1L<<22)
1482 #define BNX2_MISC_CS16_ERR_STA_COM (1L<<23)
1483 #define BNX2_MISC_CS16_ERR_STA_CP (1L<<24)
1493 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
1494 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
1495 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
1497 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
1498 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
1499 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
1500 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
1501 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
1502 #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
1503 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
1504 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
1505 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
1506 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
1508 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
1509 #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
1511 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
1512 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
1513 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
1514 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
1518 #define BNX2_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
1519 #define BNX2_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
1520 #define BNX2_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
1521 #define BNX2_MISC_OTP_CMD1_FMODE_SET (3L<<0)
1522 #define BNX2_MISC_OTP_CMD1_FMODE_RST (4L<<0)
1523 #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
1524 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
1525 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
1526 #define BNX2_MISC_OTP_CMD1_USEPINS (1L<<8)
1527 #define BNX2_MISC_OTP_CMD1_PROGSEL (1L<<9)
1528 #define BNX2_MISC_OTP_CMD1_PROGSTART (1L<<10)
1530 #define BNX2_MISC_OTP_CMD1_PBYP (1L<<19)
1533 #define BNX2_MISC_OTP_CMD1_SADBYP (1L<<30)
1534 #define BNX2_MISC_OTP_CMD1_DEBUG (1L<<31)
1539 #define BNX2_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
1540 #define BNX2_MISC_OTP_CMD2_DOSEL_1 (1L<<16)
1541 #define BNX2_MISC_OTP_CMD2_DOSEL_127 (127L<<16)
1545 #define BNX2_MISC_OTP_STATUS_VALID (1L<<8)
1546 #define BNX2_MISC_OTP_STATUS_BUSY (1L<<9)
1547 #define BNX2_MISC_OTP_STATUS_BUSYSM (1L<<10)
1548 #define BNX2_MISC_OTP_STATUS_DONE (1L<<11)
1551 #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
1552 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1)
1553 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2)
1554 #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3)
1559 #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
1560 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1)
1561 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2)
1562 #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3)
1567 #define BNX2_MISC_BIST_CS0_MBIST_EN (1L<<0)
1569 #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3)
1570 #define BNX2_MISC_BIST_CS0_MBIST_DONE (1L<<8)
1571 #define BNX2_MISC_BIST_CS0_MBIST_GO (1L<<9)
1572 #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31)
1576 #define BNX2_MISC_BIST_CS1_MBIST_EN (1L<<0)
1578 #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3)
1579 #define BNX2_MISC_BIST_CS1_MBIST_DONE (1L<<8)
1580 #define BNX2_MISC_BIST_CS1_MBIST_GO (1L<<9)
1584 #define BNX2_MISC_BIST_CS2_MBIST_EN (1L<<0)
1586 #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3)
1587 #define BNX2_MISC_BIST_CS2_MBIST_DONE (1L<<8)
1588 #define BNX2_MISC_BIST_CS2_MBIST_GO (1L<<9)
1592 #define BNX2_MISC_BIST_CS3_MBIST_EN (1L<<0)
1594 #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3)
1595 #define BNX2_MISC_BIST_CS3_MBIST_DONE (1L<<8)
1596 #define BNX2_MISC_BIST_CS3_MBIST_GO (1L<<9)
1600 #define BNX2_MISC_BIST_CS4_MBIST_EN (1L<<0)
1602 #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3)
1603 #define BNX2_MISC_BIST_CS4_MBIST_DONE (1L<<8)
1604 #define BNX2_MISC_BIST_CS4_MBIST_GO (1L<<9)
1608 #define BNX2_MISC_BIST_CS5_MBIST_EN (1L<<0)
1610 #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3)
1611 #define BNX2_MISC_BIST_CS5_MBIST_DONE (1L<<8)
1612 #define BNX2_MISC_BIST_CS5_MBIST_GO (1L<<9)
1622 #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
1623 #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1)
1626 #define BNX2_MISC_USPLL_CTRL_VC_EN (1L<<10)
1630 #define BNX2_MISC_USPLL_CTRL_TESTD_EN (1L<<19)
1632 #define BNX2_MISC_USPLL_CTRL_TESTA_EN (1L<<23)
1634 #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26)
1635 #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27)
1636 #define BNX2_MISC_USPLL_CTRL_ANALOG_RST (1L<<28)
1637 #define BNX2_MISC_USPLL_CTRL_LOCK (1L<<29)
1640 #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
1641 #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1)
1642 #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2)
1643 #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3)
1644 #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4)
1645 #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5)
1646 #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6)
1647 #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7)
1648 #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8)
1649 #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9)
1650 #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10)
1651 #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11)
1652 #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12)
1653 #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13)
1654 #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14)
1655 #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15)
1656 #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16)
1657 #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17)
1658 #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18)
1659 #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19)
1660 #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20)
1661 #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21)
1662 #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22)
1663 #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23)
1664 #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24)
1665 #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25)
1666 #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26)
1667 #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27)
1668 #define BNX2_MISC_PERR_STATUS0_THBUF_PERR (1L<<28)
1669 #define BNX2_MISC_PERR_STATUS0_TDMA_PERR (1L<<29)
1670 #define BNX2_MISC_PERR_STATUS0_TBDC_PERR (1L<<30)
1671 #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31)
1674 #define BNX2_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
1675 #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2)
1676 #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3)
1677 #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4)
1678 #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5)
1679 #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6)
1680 #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7)
1681 #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8)
1682 #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9)
1683 #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10)
1684 #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11)
1685 #define BNX2_MISC_PERR_STATUS1_COMQ_PERR (1L<<12)
1686 #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13)
1687 #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14)
1688 #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15)
1689 #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16)
1690 #define BNX2_MISC_PERR_STATUS1_TASQ_PERR (1L<<17)
1691 #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18)
1692 #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19)
1693 #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20)
1694 #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21)
1695 #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22)
1696 #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23)
1697 #define BNX2_MISC_PERR_STATUS1_CPQ_PERR (1L<<24)
1698 #define BNX2_MISC_PERR_STATUS1_CSQ_PERR (1L<<25)
1699 #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26)
1700 #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27)
1701 #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28)
1702 #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29)
1705 #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
1706 #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1)
1707 #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2)
1708 #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3)
1709 #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4)
1710 #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5)
1711 #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6)
1715 #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
1716 #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
1717 #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
1718 #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
1720 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
1721 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3)
1722 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3)
1723 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3)
1727 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
1728 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11)
1729 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11)
1730 #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13)
1731 #define BNX2_MISC_LCPLL_CTRL0_RESERVED (1L<<14)
1732 #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15)
1733 #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16)
1734 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17)
1735 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18)
1736 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19)
1737 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20)
1738 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21)
1739 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22)
1740 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23)
1741 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24)
1742 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25)
1743 #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26)
1744 #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27)
1748 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5)
1749 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6)
1750 #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7)
1753 #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
1754 #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1)
1755 #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2)
1756 #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3)
1760 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15)
1761 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
1762 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15)
1765 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5)
1766 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
1767 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5)
1769 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
1770 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6)
1771 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6)
1772 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6)
1774 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
1775 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8)
1776 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8)
1777 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8)
1779 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
1780 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10)
1781 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
1782 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
1790 #define BNX2_NVM_COMMAND_RST (1L<<0)
1791 #define BNX2_NVM_COMMAND_DONE (1L<<3)
1792 #define BNX2_NVM_COMMAND_DOIT (1L<<4)
1793 #define BNX2_NVM_COMMAND_WR (1L<<5)
1794 #define BNX2_NVM_COMMAND_ERASE (1L<<6)
1795 #define BNX2_NVM_COMMAND_FIRST (1L<<7)
1796 #define BNX2_NVM_COMMAND_LAST (1L<<8)
1797 #define BNX2_NVM_COMMAND_WREN (1L<<16)
1798 #define BNX2_NVM_COMMAND_WRDI (1L<<17)
1799 #define BNX2_NVM_COMMAND_EWSR (1L<<18)
1800 #define BNX2_NVM_COMMAND_WRSR (1L<<19)
1801 #define BNX2_NVM_COMMAND_RD_ID (1L<<20)
1802 #define BNX2_NVM_COMMAND_RD_STATUS (1L<<21)
1803 #define BNX2_NVM_COMMAND_MODE_256 (1L<<22)
1810 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0L<<0)
1811 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1L<<0)
1812 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2L<<0)
1813 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3L<<0)
1814 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4L<<0)
1815 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5L<<0)
1816 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6L<<0)
1817 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7L<<0)
1818 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8L<<0)
1819 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9L<<0)
1820 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10L<<0)
1821 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11L<<0)
1822 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12L<<0)
1823 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13L<<0)
1824 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14L<<0)
1825 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15L<<0)
1826 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16L<<0)
1827 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17L<<0)
1828 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18L<<0)
1829 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19L<<0)
1833 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1834 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1835 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1836 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1837 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1838 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1839 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1840 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1L<<0)
1841 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2L<<0)
1842 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4L<<0)
1843 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8L<<0)
1847 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1848 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1849 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1850 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1851 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1852 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1853 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1854 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1L<<0)
1855 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2L<<0)
1856 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4L<<0)
1857 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8L<<0)
1861 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1862 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1863 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1864 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1865 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1866 #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1867 #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1868 #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI (1L<<0)
1869 #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI (2L<<0)
1870 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI (4L<<0)
1871 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI (8L<<0)
1874 #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
1875 #define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
1876 #define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
1877 #define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
1879 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1880 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1883 #define BNX2_NVM_CFG1_STRAP_CONTROL_0 (1L<<23)
1884 #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
1885 #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
1886 #define BNX2_NVM_CFG1_FW_USTRAP_1 (1L<<26)
1887 #define BNX2_NVM_CFG1_FW_USTRAP_0 (1L<<27)
1888 #define BNX2_NVM_CFG1_FW_USTRAP_2 (1L<<28)
1889 #define BNX2_NVM_CFG1_FW_USTRAP_3 (1L<<29)
1890 #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN (1L<<30)
1891 #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1906 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1907 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1908 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1909 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1910 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1911 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1912 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1913 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1914 #define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1915 #define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1916 #define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1917 #define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1918 #define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
1919 #define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
1920 #define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
1921 #define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
1924 #define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
1925 #define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1934 #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
1935 #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
1936 #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
1937 #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
1938 #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
1939 #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
1940 #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
1941 #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
1942 #define BNX2_NVM_CFG4_FLASH_VENDOR (1L<<3)
1943 #define BNX2_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
1944 #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL (1L<<3)
1946 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
1947 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1L<<4)
1948 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2L<<4)
1949 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3L<<4)
1950 #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY (1L<<6)
1955 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
1956 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0)
1959 #define BNX2_NVM_RECONFIG_RECONFIG_DONE (1L<<31)
1968 #define BNX2_DMA_COMMAND_ENABLE (1L<<0)
1971 #define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1972 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1973 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1974 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1975 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1976 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1977 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1978 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1979 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1980 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1981 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1982 #define BNX2_DMA_STATUS_GLOBAL_ERR_XI (1L<<0)
1983 #define BNX2_DMA_STATUS_BME_XI (1L<<4)
1986 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1987 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1988 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1989 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1990 #define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
1991 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1992 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1993 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1994 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1998 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
2008 #define BNX2_DMA_CONFIG_MAX_PL_128B_XI (0L<<12)
2009 #define BNX2_DMA_CONFIG_MAX_PL_256B_XI (1L<<12)
2010 #define BNX2_DMA_CONFIG_MAX_PL_512B_XI (2L<<12)
2011 #define BNX2_DMA_CONFIG_MAX_PL_EN_XI (1L<<15)
2013 #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI (0L<<16)
2014 #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI (1L<<16)
2015 #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI (2L<<16)
2016 #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI (3L<<16)
2017 #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI (4L<<16)
2018 #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI (5L<<16)
2019 #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI (1L<<19)
2020 #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI (1L<<31)
2028 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1L<<0)
2029 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER (1L<<1)
2030 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY (1L<<2)
2032 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN (1L<<7)
2033 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP (1L<<8)
2034 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER (1L<<9)
2035 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY (1L<<10)
2037 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN (1L<<15)
2038 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP (1L<<16)
2039 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER (1L<<17)
2040 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY (1L<<18)
2042 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN (1L<<23)
2043 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
2044 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
2045 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
2047 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
2050 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
2051 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
2052 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
2054 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
2055 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
2056 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
2057 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
2059 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
2062 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1L<<0)
2063 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER (1L<<1)
2064 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY (1L<<2)
2065 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD (1L<<3)
2067 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN (1L<<7)
2068 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP (1L<<8)
2069 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER (1L<<9)
2070 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY (1L<<10)
2071 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD (1L<<11)
2073 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN (1L<<15)
2074 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
2075 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
2076 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
2077 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD (1L<<27)
2079 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
2082 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
2083 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
2084 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
2085 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD (1L<<3)
2087 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
2088 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
2089 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
2090 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
2091 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD (1L<<11)
2093 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
2097 #define BNX2_DMA_ARBITER_WR_ARB_MODE (1L<<4)
2098 #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT (0L<<4)
2099 #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN (1L<<4)
2101 #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT (0L<<5)
2102 #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN (1L<<5)
2103 #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN (2L<<5)
2104 #define BNX2_DMA_ARBITER_ALT_MODE_EN (1L<<8)
2105 #define BNX2_DMA_ARBITER_RR_MODE (1L<<9)
2106 #define BNX2_DMA_ARBITER_TIMER_MODE (1L<<10)
2116 #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2119 #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2125 #define BNX2_DMA_TAG_RAM_00_MASTER_CTX (0L<<4)
2126 #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC (1L<<4)
2127 #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC (2L<<4)
2128 #define BNX2_DMA_TAG_RAM_00_MASTER_COM (3L<<4)
2129 #define BNX2_DMA_TAG_RAM_00_MASTER_CP (4L<<4)
2130 #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA (5L<<4)
2132 #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG (0L<<7)
2133 #define BNX2_DMA_TAG_RAM_00_SWAP_DATA (1L<<7)
2134 #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL (2L<<7)
2135 #define BNX2_DMA_TAG_RAM_00_FUNCTION (1L<<9)
2136 #define BNX2_DMA_TAG_RAM_00_VALID (1L<<10)
2141 #define BNX2_DMA_TAG_RAM_01_MASTER_CTX (0L<<4)
2142 #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC (1L<<4)
2143 #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC (2L<<4)
2144 #define BNX2_DMA_TAG_RAM_01_MASTER_COM (3L<<4)
2145 #define BNX2_DMA_TAG_RAM_01_MASTER_CP (4L<<4)
2146 #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA (5L<<4)
2148 #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG (0L<<7)
2149 #define BNX2_DMA_TAG_RAM_01_SWAP_DATA (1L<<7)
2150 #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL (2L<<7)
2151 #define BNX2_DMA_TAG_RAM_01_FUNCTION (1L<<9)
2152 #define BNX2_DMA_TAG_RAM_01_VALID (1L<<10)
2157 #define BNX2_DMA_TAG_RAM_02_MASTER_CTX (0L<<4)
2158 #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC (1L<<4)
2159 #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC (2L<<4)
2160 #define BNX2_DMA_TAG_RAM_02_MASTER_COM (3L<<4)
2161 #define BNX2_DMA_TAG_RAM_02_MASTER_CP (4L<<4)
2162 #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA (5L<<4)
2164 #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG (0L<<7)
2165 #define BNX2_DMA_TAG_RAM_02_SWAP_DATA (1L<<7)
2166 #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL (2L<<7)
2167 #define BNX2_DMA_TAG_RAM_02_FUNCTION (1L<<9)
2168 #define BNX2_DMA_TAG_RAM_02_VALID (1L<<10)
2173 #define BNX2_DMA_TAG_RAM_03_MASTER_CTX (0L<<4)
2174 #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC (1L<<4)
2175 #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC (2L<<4)
2176 #define BNX2_DMA_TAG_RAM_03_MASTER_COM (3L<<4)
2177 #define BNX2_DMA_TAG_RAM_03_MASTER_CP (4L<<4)
2178 #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA (5L<<4)
2180 #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG (0L<<7)
2181 #define BNX2_DMA_TAG_RAM_03_SWAP_DATA (1L<<7)
2182 #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL (2L<<7)
2183 #define BNX2_DMA_TAG_RAM_03_FUNCTION (1L<<9)
2184 #define BNX2_DMA_TAG_RAM_03_VALID (1L<<10)
2189 #define BNX2_DMA_TAG_RAM_04_MASTER_CTX (0L<<4)
2190 #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC (1L<<4)
2191 #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC (2L<<4)
2192 #define BNX2_DMA_TAG_RAM_04_MASTER_COM (3L<<4)
2193 #define BNX2_DMA_TAG_RAM_04_MASTER_CP (4L<<4)
2194 #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA (5L<<4)
2196 #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG (0L<<7)
2197 #define BNX2_DMA_TAG_RAM_04_SWAP_DATA (1L<<7)
2198 #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL (2L<<7)
2199 #define BNX2_DMA_TAG_RAM_04_FUNCTION (1L<<9)
2200 #define BNX2_DMA_TAG_RAM_04_VALID (1L<<10)
2205 #define BNX2_DMA_TAG_RAM_05_MASTER_CTX (0L<<4)
2206 #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC (1L<<4)
2207 #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC (2L<<4)
2208 #define BNX2_DMA_TAG_RAM_05_MASTER_COM (3L<<4)
2209 #define BNX2_DMA_TAG_RAM_05_MASTER_CP (4L<<4)
2210 #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA (5L<<4)
2212 #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG (0L<<7)
2213 #define BNX2_DMA_TAG_RAM_05_SWAP_DATA (1L<<7)
2214 #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL (2L<<7)
2215 #define BNX2_DMA_TAG_RAM_05_FUNCTION (1L<<9)
2216 #define BNX2_DMA_TAG_RAM_05_VALID (1L<<10)
2221 #define BNX2_DMA_TAG_RAM_06_MASTER_CTX (0L<<4)
2222 #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC (1L<<4)
2223 #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC (2L<<4)
2224 #define BNX2_DMA_TAG_RAM_06_MASTER_COM (3L<<4)
2225 #define BNX2_DMA_TAG_RAM_06_MASTER_CP (4L<<4)
2226 #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA (5L<<4)
2228 #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG (0L<<7)
2229 #define BNX2_DMA_TAG_RAM_06_SWAP_DATA (1L<<7)
2230 #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL (2L<<7)
2231 #define BNX2_DMA_TAG_RAM_06_FUNCTION (1L<<9)
2232 #define BNX2_DMA_TAG_RAM_06_VALID (1L<<10)
2237 #define BNX2_DMA_TAG_RAM_07_MASTER_CTX (0L<<4)
2238 #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC (1L<<4)
2239 #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC (2L<<4)
2240 #define BNX2_DMA_TAG_RAM_07_MASTER_COM (3L<<4)
2241 #define BNX2_DMA_TAG_RAM_07_MASTER_CP (4L<<4)
2242 #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA (5L<<4)
2244 #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG (0L<<7)
2245 #define BNX2_DMA_TAG_RAM_07_SWAP_DATA (1L<<7)
2246 #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL (2L<<7)
2247 #define BNX2_DMA_TAG_RAM_07_FUNCTION (1L<<9)
2248 #define BNX2_DMA_TAG_RAM_07_VALID (1L<<10)
2253 #define BNX2_DMA_TAG_RAM_08_MASTER_CTX (0L<<4)
2254 #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC (1L<<4)
2255 #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC (2L<<4)
2256 #define BNX2_DMA_TAG_RAM_08_MASTER_COM (3L<<4)
2257 #define BNX2_DMA_TAG_RAM_08_MASTER_CP (4L<<4)
2258 #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA (5L<<4)
2260 #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG (0L<<7)
2261 #define BNX2_DMA_TAG_RAM_08_SWAP_DATA (1L<<7)
2262 #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL (2L<<7)
2263 #define BNX2_DMA_TAG_RAM_08_FUNCTION (1L<<9)
2264 #define BNX2_DMA_TAG_RAM_08_VALID (1L<<10)
2269 #define BNX2_DMA_TAG_RAM_09_MASTER_CTX (0L<<4)
2270 #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC (1L<<4)
2271 #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC (2L<<4)
2272 #define BNX2_DMA_TAG_RAM_09_MASTER_COM (3L<<4)
2273 #define BNX2_DMA_TAG_RAM_09_MASTER_CP (4L<<4)
2274 #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA (5L<<4)
2276 #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG (0L<<7)
2277 #define BNX2_DMA_TAG_RAM_09_SWAP_DATA (1L<<7)
2278 #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL (2L<<7)
2279 #define BNX2_DMA_TAG_RAM_09_FUNCTION (1L<<9)
2280 #define BNX2_DMA_TAG_RAM_09_VALID (1L<<10)
2285 #define BNX2_DMA_TAG_RAM_10_MASTER_CTX (0L<<4)
2286 #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC (1L<<4)
2287 #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC (2L<<4)
2288 #define BNX2_DMA_TAG_RAM_10_MASTER_COM (3L<<4)
2289 #define BNX2_DMA_TAG_RAM_10_MASTER_CP (4L<<4)
2290 #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA (5L<<4)
2292 #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG (0L<<7)
2293 #define BNX2_DMA_TAG_RAM_10_SWAP_DATA (1L<<7)
2294 #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL (2L<<7)
2295 #define BNX2_DMA_TAG_RAM_10_FUNCTION (1L<<9)
2296 #define BNX2_DMA_TAG_RAM_10_VALID (1L<<10)
2301 #define BNX2_DMA_TAG_RAM_11_MASTER_CTX (0L<<4)
2302 #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC (1L<<4)
2303 #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC (2L<<4)
2304 #define BNX2_DMA_TAG_RAM_11_MASTER_COM (3L<<4)
2305 #define BNX2_DMA_TAG_RAM_11_MASTER_CP (4L<<4)
2306 #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA (5L<<4)
2308 #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG (0L<<7)
2309 #define BNX2_DMA_TAG_RAM_11_SWAP_DATA (1L<<7)
2310 #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL (2L<<7)
2311 #define BNX2_DMA_TAG_RAM_11_FUNCTION (1L<<9)
2312 #define BNX2_DMA_TAG_RAM_11_VALID (1L<<10)
2338 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
2339 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
2340 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
2379 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
2380 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
2381 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
2382 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
2387 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
2388 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
2389 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
2390 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
2395 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
2396 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
2397 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
2398 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
2409 #define BNX2_CTX_COMMAND_ENABLED (1L<<0)
2410 #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
2411 #define BNX2_CTX_COMMAND_DISABLE_PLRU (1L<<2)
2412 #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
2414 #define BNX2_CTX_COMMAND_MEM_INIT (1L<<13)
2416 #define BNX2_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2417 #define BNX2_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
2418 #define BNX2_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
2419 #define BNX2_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
2420 #define BNX2_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
2421 #define BNX2_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
2422 #define BNX2_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
2423 #define BNX2_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
2424 #define BNX2_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
2425 #define BNX2_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
2426 #define BNX2_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
2427 #define BNX2_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
2428 #define BNX2_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
2431 #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
2432 #define BNX2_CTX_STATUS_READ_STAT (1L<<16)
2433 #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
2434 #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
2435 #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
2436 #define BNX2_CTX_STATUS_EXT_READ_STAT (1L<<20)
2437 #define BNX2_CTX_STATUS_EXT_WRITE_STAT (1L<<21)
2438 #define BNX2_CTX_STATUS_MISS_STAT (1L<<22)
2439 #define BNX2_CTX_STATUS_HIT_STAT (1L<<23)
2440 #define BNX2_CTX_STATUS_DEAD_LOCK (1L<<24)
2441 #define BNX2_CTX_STATUS_USAGE_CNT_ERR (1L<<25)
2442 #define BNX2_CTX_STATUS_INVALID_PAGE (1L<<26)
2461 #define BNX2_CTX_LOCK_TYPE_VOID_XI (0L<<0)
2462 #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
2463 #define BNX2_CTX_LOCK_TYPE_TX_XI (2L<<0)
2464 #define BNX2_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
2465 #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
2467 #define BNX2_CTX_LOCK_GRANTED (1L<<26)
2472 #define BNX2_CTX_LOCK_STATUS (1L<<30)
2473 #define BNX2_CTX_LOCK_REQ (1L<<31)
2478 #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
2480 #define BNX2_CTX_CTX_CTRL_ATTR (1L<<26)
2481 #define BNX2_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
2482 #define BNX2_CTX_CTX_CTRL_READ_REQ (1L<<31)
2500 #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
2501 #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1)
2502 #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6)
2505 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19)
2506 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20)
2507 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21)
2508 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22)
2509 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23)
2510 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24)
2511 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25)
2512 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26)
2513 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27)
2514 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28)
2515 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29)
2544 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16)
2545 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17)
2546 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18)
2555 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
2556 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14)
2572 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
2573 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
2576 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
2582 #define BNX2_CTX_CAM_CTRL_RESET (1L<<27)
2583 #define BNX2_CTX_CAM_CTRL_INVALIDATE (1L<<28)
2584 #define BNX2_CTX_CAM_CTRL_SEARCH (1L<<29)
2585 #define BNX2_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
2586 #define BNX2_CTX_CAM_CTRL_READ_REQ (1L<<31)
2594 #define BNX2_EMAC_MODE_RESET (1L<<0)
2595 #define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
2597 #define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
2598 #define BNX2_EMAC_MODE_PORT_MII (1L<<2)
2599 #define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
2600 #define BNX2_EMAC_MODE_PORT_MII_10M (3L<<2)
2601 #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
2602 #define BNX2_EMAC_MODE_25G_MODE (1L<<5)
2603 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
2604 #define BNX2_EMAC_MODE_TX_BURST (1L<<8)
2605 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
2606 #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
2607 #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
2608 #define BNX2_EMAC_MODE_SERDES_MODE (1L<<12)
2609 #define BNX2_EMAC_MODE_BOND_OVRD (1L<<13)
2610 #define BNX2_EMAC_MODE_MPKT (1L<<18)
2611 #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
2612 #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
2615 #define BNX2_EMAC_STATUS_LINK (1L<<11)
2616 #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
2617 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13)
2618 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14)
2619 #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16)
2620 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17)
2621 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
2622 #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
2623 #define BNX2_EMAC_STATUS_MI_INT (1L<<23)
2624 #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
2625 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
2628 #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
2629 #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14)
2630 #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16)
2631 #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
2632 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
2633 #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
2634 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
2637 #define BNX2_EMAC_LED_OVERRIDE (1L<<0)
2638 #define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
2639 #define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
2640 #define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
2641 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
2642 #define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
2643 #define BNX2_EMAC_LED_TRAFFIC (1L<<6)
2644 #define BNX2_EMAC_LED_1000MB (1L<<7)
2645 #define BNX2_EMAC_LED_100MB (1L<<8)
2646 #define BNX2_EMAC_LED_10MB (1L<<9)
2647 #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
2648 #define BNX2_EMAC_LED_2500MB (1L<<11)
2649 #define BNX2_EMAC_LED_2500MB_OVERRIDE (1L<<12)
2651 #define BNX2_EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
2652 #define BNX2_EMAC_LED_ACTIVITY_SEL_1 (1L<<17)
2653 #define BNX2_EMAC_LED_ACTIVITY_SEL_2 (2L<<17)
2654 #define BNX2_EMAC_LED_ACTIVITY_SEL_3 (3L<<17)
2656 #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
2695 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
2700 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
2702 #define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
2703 #define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
2704 #define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
2705 #define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
2706 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
2707 #define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
2708 #define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
2709 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
2710 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
2711 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
2717 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
2724 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2725 #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
2726 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
2727 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
2728 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI (1L<<26)
2729 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI (1L<<26)
2730 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI (2L<<26)
2731 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI (2L<<26)
2732 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
2733 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
2734 #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
2735 #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
2736 #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
2739 #define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
2740 #define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
2743 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
2744 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
2745 #define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
2746 #define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
2747 #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
2748 #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
2749 #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
2750 #define BNX2_EMAC_MDIO_MODE_EXT_MDINT (1L<<13)
2753 #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI (1L<<31)
2756 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
2759 #define BNX2_EMAC_TX_MODE_RESET (1L<<0)
2760 #define BNX2_EMAC_TX_MODE_CS16_TEST (1L<<2)
2761 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
2762 #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
2763 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
2764 #define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
2765 #define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
2768 #define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
2769 #define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
2770 #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
2771 #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
2772 #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
2773 #define BNX2_EMAC_TX_STATUS_CS16_ERROR (1L<<5)
2781 #define BNX2_EMAC_RX_MODE_RESET (1L<<0)
2782 #define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
2783 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
2784 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
2785 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
2786 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
2787 #define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
2788 #define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
2789 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
2790 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
2791 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
2792 #define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
2795 #define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
2796 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
2797 #define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
2836 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
2837 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
2838 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
2839 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
2840 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
2841 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
2842 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
2867 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
2868 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
2869 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
2870 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
2871 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
2922 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
2923 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
2924 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
2925 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
2926 #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND (1L<<26)
2927 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
2928 #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
2932 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
2933 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
2934 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
2935 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
2936 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
2937 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
2938 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
2947 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
2949 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
2950 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
2951 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
2952 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
2953 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
2955 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
3017 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
3018 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
3020 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
3021 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
3022 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
3023 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
3024 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
3032 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
3059 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
3060 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
3080 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
3081 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
3082 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
3083 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
3084 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
3085 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
3086 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
3087 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
3088 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
3089 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
3090 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
3091 #define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
3118 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1L<<31)
3126 #define BNX2_RPM_COMMAND_ENABLED (1L<<0)
3127 #define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
3130 #define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
3131 #define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
3134 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
3135 #define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
3136 #define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
3137 #define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
3139 #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT (1L<<30)
3140 #define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
3145 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30)
3146 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31)
3162 #define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
3163 #define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
3164 #define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
3165 #define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
3167 #define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
3168 #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH (1L<<25)
3169 #define BNX2_RPM_SORT_USER0_ENA (1L<<31)
3173 #define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
3174 #define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
3175 #define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
3176 #define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
3178 #define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
3179 #define BNX2_RPM_SORT_USER1_ENA (1L<<31)
3183 #define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
3184 #define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
3185 #define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
3186 #define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
3188 #define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
3189 #define BNX2_RPM_SORT_USER2_ENA (1L<<31)
3193 #define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
3194 #define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
3195 #define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
3196 #define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
3198 #define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
3199 #define BNX2_RPM_SORT_USER3_ENA (1L<<31)
3209 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1L<<30)
3210 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1L<<31)
3215 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1L<<30)
3216 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1L<<31)
3221 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1L<<30)
3222 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1L<<31)
3227 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1L<<30)
3228 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1L<<31)
3233 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1L<<30)
3234 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1L<<31)
3239 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1L<<30)
3240 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1L<<31)
3245 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1L<<30)
3246 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1L<<31)
3251 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1L<<30)
3252 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1L<<31)
3262 #define BNX2_RPM_RC_CNTL_16_PRIORITY (1L<<11)
3263 #define BNX2_RPM_RC_CNTL_16_P4 (1L<<12)
3265 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START (0L<<13)
3266 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP (1L<<13)
3267 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP (2L<<13)
3268 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP (3L<<13)
3269 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA (4L<<13)
3270 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP (5L<<13)
3271 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6 (6L<<13)
3273 #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL (0L<<16)
3274 #define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL (1L<<16)
3275 #define BNX2_RPM_RC_CNTL_16_COMP_GREATER (2L<<16)
3276 #define BNX2_RPM_RC_CNTL_16_COMP_LESS (3L<<16)
3277 #define BNX2_RPM_RC_CNTL_16_MAP (1L<<18)
3278 #define BNX2_RPM_RC_CNTL_16_SBIT (1L<<19)
3280 #define BNX2_RPM_RC_CNTL_16_DISCARD (1L<<25)
3281 #define BNX2_RPM_RC_CNTL_16_MASK (1L<<26)
3282 #define BNX2_RPM_RC_CNTL_16_P1 (1L<<27)
3283 #define BNX2_RPM_RC_CNTL_16_P2 (1L<<28)
3284 #define BNX2_RPM_RC_CNTL_16_P3 (1L<<29)
3285 #define BNX2_RPM_RC_CNTL_16_NBIT (1L<<30)
3294 #define BNX2_RPM_RC_CNTL_17_PRIORITY (1L<<11)
3295 #define BNX2_RPM_RC_CNTL_17_P4 (1L<<12)
3297 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START (0L<<13)
3298 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP (1L<<13)
3299 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP (2L<<13)
3300 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP (3L<<13)
3301 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA (4L<<13)
3302 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP (5L<<13)
3303 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6 (6L<<13)
3305 #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL (0L<<16)
3306 #define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL (1L<<16)
3307 #define BNX2_RPM_RC_CNTL_17_COMP_GREATER (2L<<16)
3308 #define BNX2_RPM_RC_CNTL_17_COMP_LESS (3L<<16)
3309 #define BNX2_RPM_RC_CNTL_17_MAP (1L<<18)
3310 #define BNX2_RPM_RC_CNTL_17_SBIT (1L<<19)
3312 #define BNX2_RPM_RC_CNTL_17_DISCARD (1L<<25)
3313 #define BNX2_RPM_RC_CNTL_17_MASK (1L<<26)
3314 #define BNX2_RPM_RC_CNTL_17_P1 (1L<<27)
3315 #define BNX2_RPM_RC_CNTL_17_P2 (1L<<28)
3316 #define BNX2_RPM_RC_CNTL_17_P3 (1L<<29)
3317 #define BNX2_RPM_RC_CNTL_17_NBIT (1L<<30)
3326 #define BNX2_RPM_RC_CNTL_18_PRIORITY (1L<<11)
3327 #define BNX2_RPM_RC_CNTL_18_P4 (1L<<12)
3329 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START (0L<<13)
3330 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP (1L<<13)
3331 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP (2L<<13)
3332 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP (3L<<13)
3333 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA (4L<<13)
3334 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP (5L<<13)
3335 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6 (6L<<13)
3337 #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL (0L<<16)
3338 #define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL (1L<<16)
3339 #define BNX2_RPM_RC_CNTL_18_COMP_GREATER (2L<<16)
3340 #define BNX2_RPM_RC_CNTL_18_COMP_LESS (3L<<16)
3341 #define BNX2_RPM_RC_CNTL_18_MAP (1L<<18)
3342 #define BNX2_RPM_RC_CNTL_18_SBIT (1L<<19)
3344 #define BNX2_RPM_RC_CNTL_18_DISCARD (1L<<25)
3345 #define BNX2_RPM_RC_CNTL_18_MASK (1L<<26)
3346 #define BNX2_RPM_RC_CNTL_18_P1 (1L<<27)
3347 #define BNX2_RPM_RC_CNTL_18_P2 (1L<<28)
3348 #define BNX2_RPM_RC_CNTL_18_P3 (1L<<29)
3349 #define BNX2_RPM_RC_CNTL_18_NBIT (1L<<30)
3358 #define BNX2_RPM_RC_CNTL_19_PRIORITY (1L<<11)
3359 #define BNX2_RPM_RC_CNTL_19_P4 (1L<<12)
3361 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START (0L<<13)
3362 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP (1L<<13)
3363 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP (2L<<13)
3364 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP (3L<<13)
3365 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA (4L<<13)
3366 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP (5L<<13)
3367 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6 (6L<<13)
3369 #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL (0L<<16)
3370 #define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL (1L<<16)
3371 #define BNX2_RPM_RC_CNTL_19_COMP_GREATER (2L<<16)
3372 #define BNX2_RPM_RC_CNTL_19_COMP_LESS (3L<<16)
3373 #define BNX2_RPM_RC_CNTL_19_MAP (1L<<18)
3374 #define BNX2_RPM_RC_CNTL_19_SBIT (1L<<19)
3376 #define BNX2_RPM_RC_CNTL_19_DISCARD (1L<<25)
3377 #define BNX2_RPM_RC_CNTL_19_MASK (1L<<26)
3378 #define BNX2_RPM_RC_CNTL_19_P1 (1L<<27)
3379 #define BNX2_RPM_RC_CNTL_19_P2 (1L<<28)
3380 #define BNX2_RPM_RC_CNTL_19_P3 (1L<<29)
3381 #define BNX2_RPM_RC_CNTL_19_NBIT (1L<<30)
3390 #define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
3391 #define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
3393 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
3394 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
3395 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
3396 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
3397 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
3398 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP (5L<<13)
3399 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6 (6L<<13)
3401 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
3402 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
3403 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
3404 #define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
3405 #define BNX2_RPM_RC_CNTL_0_MAP_XI (1L<<18)
3406 #define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
3408 #define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
3410 #define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
3411 #define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
3412 #define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
3413 #define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
3414 #define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
3415 #define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
3426 #define BNX2_RPM_RC_CNTL_1_PRIORITY_XI (1L<<11)
3427 #define BNX2_RPM_RC_CNTL_1_P4_XI (1L<<12)
3429 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI (0L<<13)
3430 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI (1L<<13)
3431 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI (2L<<13)
3432 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI (3L<<13)
3433 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI (4L<<13)
3434 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI (5L<<13)
3435 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI (6L<<13)
3437 #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI (0L<<16)
3438 #define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI (1L<<16)
3439 #define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI (2L<<16)
3440 #define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI (3L<<16)
3441 #define BNX2_RPM_RC_CNTL_1_MAP_XI (1L<<18)
3442 #define BNX2_RPM_RC_CNTL_1_SBIT_XI (1L<<19)
3444 #define BNX2_RPM_RC_CNTL_1_DISCARD_XI (1L<<25)
3445 #define BNX2_RPM_RC_CNTL_1_MASK_XI (1L<<26)
3446 #define BNX2_RPM_RC_CNTL_1_P1_XI (1L<<27)
3447 #define BNX2_RPM_RC_CNTL_1_P2_XI (1L<<28)
3448 #define BNX2_RPM_RC_CNTL_1_P3_XI (1L<<29)
3449 #define BNX2_RPM_RC_CNTL_1_NBIT_XI (1L<<30)
3460 #define BNX2_RPM_RC_CNTL_2_PRIORITY_XI (1L<<11)
3461 #define BNX2_RPM_RC_CNTL_2_P4_XI (1L<<12)
3463 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI (0L<<13)
3464 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI (1L<<13)
3465 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI (2L<<13)
3466 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI (3L<<13)
3467 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI (4L<<13)
3468 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI (5L<<13)
3469 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI (6L<<13)
3471 #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI (0L<<16)
3472 #define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI (1L<<16)
3473 #define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI (2L<<16)
3474 #define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI (3L<<16)
3475 #define BNX2_RPM_RC_CNTL_2_MAP_XI (1L<<18)
3476 #define BNX2_RPM_RC_CNTL_2_SBIT_XI (1L<<19)
3478 #define BNX2_RPM_RC_CNTL_2_DISCARD_XI (1L<<25)
3479 #define BNX2_RPM_RC_CNTL_2_MASK_XI (1L<<26)
3480 #define BNX2_RPM_RC_CNTL_2_P1_XI (1L<<27)
3481 #define BNX2_RPM_RC_CNTL_2_P2_XI (1L<<28)
3482 #define BNX2_RPM_RC_CNTL_2_P3_XI (1L<<29)
3483 #define BNX2_RPM_RC_CNTL_2_NBIT_XI (1L<<30)
3494 #define BNX2_RPM_RC_CNTL_3_PRIORITY_XI (1L<<11)
3495 #define BNX2_RPM_RC_CNTL_3_P4_XI (1L<<12)
3497 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI (0L<<13)
3498 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI (1L<<13)
3499 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI (2L<<13)
3500 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI (3L<<13)
3501 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI (4L<<13)
3502 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI (5L<<13)
3503 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI (6L<<13)
3505 #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI (0L<<16)
3506 #define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI (1L<<16)
3507 #define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI (2L<<16)
3508 #define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI (3L<<16)
3509 #define BNX2_RPM_RC_CNTL_3_MAP_XI (1L<<18)
3510 #define BNX2_RPM_RC_CNTL_3_SBIT_XI (1L<<19)
3512 #define BNX2_RPM_RC_CNTL_3_DISCARD_XI (1L<<25)
3513 #define BNX2_RPM_RC_CNTL_3_MASK_XI (1L<<26)
3514 #define BNX2_RPM_RC_CNTL_3_P1_XI (1L<<27)
3515 #define BNX2_RPM_RC_CNTL_3_P2_XI (1L<<28)
3516 #define BNX2_RPM_RC_CNTL_3_P3_XI (1L<<29)
3517 #define BNX2_RPM_RC_CNTL_3_NBIT_XI (1L<<30)
3528 #define BNX2_RPM_RC_CNTL_4_PRIORITY_XI (1L<<11)
3529 #define BNX2_RPM_RC_CNTL_4_P4_XI (1L<<12)
3531 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI (0L<<13)
3532 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI (1L<<13)
3533 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI (2L<<13)
3534 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI (3L<<13)
3535 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI (4L<<13)
3536 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI (5L<<13)
3537 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI (6L<<13)
3539 #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI (0L<<16)
3540 #define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI (1L<<16)
3541 #define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI (2L<<16)
3542 #define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI (3L<<16)
3543 #define BNX2_RPM_RC_CNTL_4_MAP_XI (1L<<18)
3544 #define BNX2_RPM_RC_CNTL_4_SBIT_XI (1L<<19)
3546 #define BNX2_RPM_RC_CNTL_4_DISCARD_XI (1L<<25)
3547 #define BNX2_RPM_RC_CNTL_4_MASK_XI (1L<<26)
3548 #define BNX2_RPM_RC_CNTL_4_P1_XI (1L<<27)
3549 #define BNX2_RPM_RC_CNTL_4_P2_XI (1L<<28)
3550 #define BNX2_RPM_RC_CNTL_4_P3_XI (1L<<29)
3551 #define BNX2_RPM_RC_CNTL_4_NBIT_XI (1L<<30)
3562 #define BNX2_RPM_RC_CNTL_5_PRIORITY_XI (1L<<11)
3563 #define BNX2_RPM_RC_CNTL_5_P4_XI (1L<<12)
3565 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI (0L<<13)
3566 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI (1L<<13)
3567 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI (2L<<13)
3568 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI (3L<<13)
3569 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI (4L<<13)
3570 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI (5L<<13)
3571 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI (6L<<13)
3573 #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI (0L<<16)
3574 #define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI (1L<<16)
3575 #define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI (2L<<16)
3576 #define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI (3L<<16)
3577 #define BNX2_RPM_RC_CNTL_5_MAP_XI (1L<<18)
3578 #define BNX2_RPM_RC_CNTL_5_SBIT_XI (1L<<19)
3580 #define BNX2_RPM_RC_CNTL_5_DISCARD_XI (1L<<25)
3581 #define BNX2_RPM_RC_CNTL_5_MASK_XI (1L<<26)
3582 #define BNX2_RPM_RC_CNTL_5_P1_XI (1L<<27)
3583 #define BNX2_RPM_RC_CNTL_5_P2_XI (1L<<28)
3584 #define BNX2_RPM_RC_CNTL_5_P3_XI (1L<<29)
3585 #define BNX2_RPM_RC_CNTL_5_NBIT_XI (1L<<30)
3596 #define BNX2_RPM_RC_CNTL_6_PRIORITY_XI (1L<<11)
3597 #define BNX2_RPM_RC_CNTL_6_P4_XI (1L<<12)
3599 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI (0L<<13)
3600 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI (1L<<13)
3601 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI (2L<<13)
3602 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI (3L<<13)
3603 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI (4L<<13)
3604 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI (5L<<13)
3605 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI (6L<<13)
3607 #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI (0L<<16)
3608 #define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI (1L<<16)
3609 #define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI (2L<<16)
3610 #define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI (3L<<16)
3611 #define BNX2_RPM_RC_CNTL_6_MAP_XI (1L<<18)
3612 #define BNX2_RPM_RC_CNTL_6_SBIT_XI (1L<<19)
3614 #define BNX2_RPM_RC_CNTL_6_DISCARD_XI (1L<<25)
3615 #define BNX2_RPM_RC_CNTL_6_MASK_XI (1L<<26)
3616 #define BNX2_RPM_RC_CNTL_6_P1_XI (1L<<27)
3617 #define BNX2_RPM_RC_CNTL_6_P2_XI (1L<<28)
3618 #define BNX2_RPM_RC_CNTL_6_P3_XI (1L<<29)
3619 #define BNX2_RPM_RC_CNTL_6_NBIT_XI (1L<<30)
3630 #define BNX2_RPM_RC_CNTL_7_PRIORITY_XI (1L<<11)
3631 #define BNX2_RPM_RC_CNTL_7_P4_XI (1L<<12)
3633 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI (0L<<13)
3634 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI (1L<<13)
3635 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI (2L<<13)
3636 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI (3L<<13)
3637 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI (4L<<13)
3638 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI (5L<<13)
3639 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI (6L<<13)
3641 #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI (0L<<16)
3642 #define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI (1L<<16)
3643 #define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI (2L<<16)
3644 #define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI (3L<<16)
3645 #define BNX2_RPM_RC_CNTL_7_MAP_XI (1L<<18)
3646 #define BNX2_RPM_RC_CNTL_7_SBIT_XI (1L<<19)
3648 #define BNX2_RPM_RC_CNTL_7_DISCARD_XI (1L<<25)
3649 #define BNX2_RPM_RC_CNTL_7_MASK_XI (1L<<26)
3650 #define BNX2_RPM_RC_CNTL_7_P1_XI (1L<<27)
3651 #define BNX2_RPM_RC_CNTL_7_P2_XI (1L<<28)
3652 #define BNX2_RPM_RC_CNTL_7_P3_XI (1L<<29)
3653 #define BNX2_RPM_RC_CNTL_7_NBIT_XI (1L<<30)
3664 #define BNX2_RPM_RC_CNTL_8_PRIORITY_XI (1L<<11)
3665 #define BNX2_RPM_RC_CNTL_8_P4_XI (1L<<12)
3667 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI (0L<<13)
3668 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI (1L<<13)
3669 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI (2L<<13)
3670 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI (3L<<13)
3671 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI (4L<<13)
3672 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI (5L<<13)
3673 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI (6L<<13)
3675 #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI (0L<<16)
3676 #define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI (1L<<16)
3677 #define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI (2L<<16)
3678 #define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI (3L<<16)
3679 #define BNX2_RPM_RC_CNTL_8_MAP_XI (1L<<18)
3680 #define BNX2_RPM_RC_CNTL_8_SBIT_XI (1L<<19)
3682 #define BNX2_RPM_RC_CNTL_8_DISCARD_XI (1L<<25)
3683 #define BNX2_RPM_RC_CNTL_8_MASK_XI (1L<<26)
3684 #define BNX2_RPM_RC_CNTL_8_P1_XI (1L<<27)
3685 #define BNX2_RPM_RC_CNTL_8_P2_XI (1L<<28)
3686 #define BNX2_RPM_RC_CNTL_8_P3_XI (1L<<29)
3687 #define BNX2_RPM_RC_CNTL_8_NBIT_XI (1L<<30)
3698 #define BNX2_RPM_RC_CNTL_9_PRIORITY_XI (1L<<11)
3699 #define BNX2_RPM_RC_CNTL_9_P4_XI (1L<<12)
3701 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI (0L<<13)
3702 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI (1L<<13)
3703 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI (2L<<13)
3704 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI (3L<<13)
3705 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI (4L<<13)
3706 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI (5L<<13)
3707 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI (6L<<13)
3709 #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI (0L<<16)
3710 #define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI (1L<<16)
3711 #define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI (2L<<16)
3712 #define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI (3L<<16)
3713 #define BNX2_RPM_RC_CNTL_9_MAP_XI (1L<<18)
3714 #define BNX2_RPM_RC_CNTL_9_SBIT_XI (1L<<19)
3716 #define BNX2_RPM_RC_CNTL_9_DISCARD_XI (1L<<25)
3717 #define BNX2_RPM_RC_CNTL_9_MASK_XI (1L<<26)
3718 #define BNX2_RPM_RC_CNTL_9_P1_XI (1L<<27)
3719 #define BNX2_RPM_RC_CNTL_9_P2_XI (1L<<28)
3720 #define BNX2_RPM_RC_CNTL_9_P3_XI (1L<<29)
3721 #define BNX2_RPM_RC_CNTL_9_NBIT_XI (1L<<30)
3732 #define BNX2_RPM_RC_CNTL_10_PRIORITY_XI (1L<<11)
3733 #define BNX2_RPM_RC_CNTL_10_P4_XI (1L<<12)
3735 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI (0L<<13)
3736 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI (1L<<13)
3737 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI (2L<<13)
3738 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI (3L<<13)
3739 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI (4L<<13)
3740 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI (5L<<13)
3741 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI (6L<<13)
3743 #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI (0L<<16)
3744 #define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI (1L<<16)
3745 #define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI (2L<<16)
3746 #define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI (3L<<16)
3747 #define BNX2_RPM_RC_CNTL_10_MAP_XI (1L<<18)
3748 #define BNX2_RPM_RC_CNTL_10_SBIT_XI (1L<<19)
3750 #define BNX2_RPM_RC_CNTL_10_DISCARD_XI (1L<<25)
3751 #define BNX2_RPM_RC_CNTL_10_MASK_XI (1L<<26)
3752 #define BNX2_RPM_RC_CNTL_10_P1_XI (1L<<27)
3753 #define BNX2_RPM_RC_CNTL_10_P2_XI (1L<<28)
3754 #define BNX2_RPM_RC_CNTL_10_P3_XI (1L<<29)
3755 #define BNX2_RPM_RC_CNTL_10_NBIT_XI (1L<<30)
3766 #define BNX2_RPM_RC_CNTL_11_PRIORITY_XI (1L<<11)
3767 #define BNX2_RPM_RC_CNTL_11_P4_XI (1L<<12)
3769 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI (0L<<13)
3770 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI (1L<<13)
3771 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI (2L<<13)
3772 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI (3L<<13)
3773 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI (4L<<13)
3774 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI (5L<<13)
3775 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI (6L<<13)
3777 #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI (0L<<16)
3778 #define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI (1L<<16)
3779 #define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI (2L<<16)
3780 #define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI (3L<<16)
3781 #define BNX2_RPM_RC_CNTL_11_MAP_XI (1L<<18)
3782 #define BNX2_RPM_RC_CNTL_11_SBIT_XI (1L<<19)
3784 #define BNX2_RPM_RC_CNTL_11_DISCARD_XI (1L<<25)
3785 #define BNX2_RPM_RC_CNTL_11_MASK_XI (1L<<26)
3786 #define BNX2_RPM_RC_CNTL_11_P1_XI (1L<<27)
3787 #define BNX2_RPM_RC_CNTL_11_P2_XI (1L<<28)
3788 #define BNX2_RPM_RC_CNTL_11_P3_XI (1L<<29)
3789 #define BNX2_RPM_RC_CNTL_11_NBIT_XI (1L<<30)
3800 #define BNX2_RPM_RC_CNTL_12_PRIORITY_XI (1L<<11)
3801 #define BNX2_RPM_RC_CNTL_12_P4_XI (1L<<12)
3803 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI (0L<<13)
3804 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI (1L<<13)
3805 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI (2L<<13)
3806 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI (3L<<13)
3807 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI (4L<<13)
3808 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI (5L<<13)
3809 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI (6L<<13)
3811 #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI (0L<<16)
3812 #define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI (1L<<16)
3813 #define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI (2L<<16)
3814 #define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI (3L<<16)
3815 #define BNX2_RPM_RC_CNTL_12_MAP_XI (1L<<18)
3816 #define BNX2_RPM_RC_CNTL_12_SBIT_XI (1L<<19)
3818 #define BNX2_RPM_RC_CNTL_12_DISCARD_XI (1L<<25)
3819 #define BNX2_RPM_RC_CNTL_12_MASK_XI (1L<<26)
3820 #define BNX2_RPM_RC_CNTL_12_P1_XI (1L<<27)
3821 #define BNX2_RPM_RC_CNTL_12_P2_XI (1L<<28)
3822 #define BNX2_RPM_RC_CNTL_12_P3_XI (1L<<29)
3823 #define BNX2_RPM_RC_CNTL_12_NBIT_XI (1L<<30)
3834 #define BNX2_RPM_RC_CNTL_13_PRIORITY_XI (1L<<11)
3835 #define BNX2_RPM_RC_CNTL_13_P4_XI (1L<<12)
3837 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI (0L<<13)
3838 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI (1L<<13)
3839 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI (2L<<13)
3840 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI (3L<<13)
3841 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI (4L<<13)
3842 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI (5L<<13)
3843 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI (6L<<13)
3845 #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI (0L<<16)
3846 #define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI (1L<<16)
3847 #define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI (2L<<16)
3848 #define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI (3L<<16)
3849 #define BNX2_RPM_RC_CNTL_13_MAP_XI (1L<<18)
3850 #define BNX2_RPM_RC_CNTL_13_SBIT_XI (1L<<19)
3852 #define BNX2_RPM_RC_CNTL_13_DISCARD_XI (1L<<25)
3853 #define BNX2_RPM_RC_CNTL_13_MASK_XI (1L<<26)
3854 #define BNX2_RPM_RC_CNTL_13_P1_XI (1L<<27)
3855 #define BNX2_RPM_RC_CNTL_13_P2_XI (1L<<28)
3856 #define BNX2_RPM_RC_CNTL_13_P3_XI (1L<<29)
3857 #define BNX2_RPM_RC_CNTL_13_NBIT_XI (1L<<30)
3868 #define BNX2_RPM_RC_CNTL_14_PRIORITY_XI (1L<<11)
3869 #define BNX2_RPM_RC_CNTL_14_P4_XI (1L<<12)
3871 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI (0L<<13)
3872 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI (1L<<13)
3873 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI (2L<<13)
3874 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI (3L<<13)
3875 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI (4L<<13)
3876 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI (5L<<13)
3877 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI (6L<<13)
3879 #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI (0L<<16)
3880 #define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI (1L<<16)
3881 #define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI (2L<<16)
3882 #define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI (3L<<16)
3883 #define BNX2_RPM_RC_CNTL_14_MAP_XI (1L<<18)
3884 #define BNX2_RPM_RC_CNTL_14_SBIT_XI (1L<<19)
3886 #define BNX2_RPM_RC_CNTL_14_DISCARD_XI (1L<<25)
3887 #define BNX2_RPM_RC_CNTL_14_MASK_XI (1L<<26)
3888 #define BNX2_RPM_RC_CNTL_14_P1_XI (1L<<27)
3889 #define BNX2_RPM_RC_CNTL_14_P2_XI (1L<<28)
3890 #define BNX2_RPM_RC_CNTL_14_P3_XI (1L<<29)
3891 #define BNX2_RPM_RC_CNTL_14_NBIT_XI (1L<<30)
3902 #define BNX2_RPM_RC_CNTL_15_PRIORITY_XI (1L<<11)
3903 #define BNX2_RPM_RC_CNTL_15_P4_XI (1L<<12)
3905 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI (0L<<13)
3906 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI (1L<<13)
3907 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI (2L<<13)
3908 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI (3L<<13)
3909 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI (4L<<13)
3910 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI (5L<<13)
3911 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI (6L<<13)
3913 #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI (0L<<16)
3914 #define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI (1L<<16)
3915 #define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI (2L<<16)
3916 #define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI (3L<<16)
3917 #define BNX2_RPM_RC_CNTL_15_MAP_XI (1L<<18)
3918 #define BNX2_RPM_RC_CNTL_15_SBIT_XI (1L<<19)
3920 #define BNX2_RPM_RC_CNTL_15_DISCARD_XI (1L<<25)
3921 #define BNX2_RPM_RC_CNTL_15_MASK_XI (1L<<26)
3922 #define BNX2_RPM_RC_CNTL_15_P1_XI (1L<<27)
3923 #define BNX2_RPM_RC_CNTL_15_P2_XI (1L<<28)
3924 #define BNX2_RPM_RC_CNTL_15_P3_XI (1L<<29)
3925 #define BNX2_RPM_RC_CNTL_15_NBIT_XI (1L<<30)
3935 #define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE (1L<<31)
3939 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
3940 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
3941 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
3942 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
3943 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
3944 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
3945 #define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
3946 #define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
3947 #define BNX2_RPM_DEBUG0_DONE (1L<<24)
3948 #define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
3949 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
3950 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
3951 #define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
3952 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
3956 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
3957 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
3958 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
3959 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
3960 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
3961 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
3962 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
3963 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
3964 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
3965 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
3966 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
3967 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
3968 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
3973 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
3974 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
3975 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
3976 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
3981 #define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
3982 #define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
3983 #define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
3984 #define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
3985 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
3986 #define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
3987 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
3988 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
3992 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
3993 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
3994 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
3995 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
3996 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
3997 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
3998 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
4000 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
4001 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
4002 #define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
4016 #define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
4017 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
4018 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
4019 #define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
4022 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
4028 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
4035 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
4036 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
4037 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
4038 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
4039 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
4040 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
4041 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
4042 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
4043 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
4044 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
4045 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
4046 #define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
4057 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
4058 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
4059 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
4060 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
4061 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
4062 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
4063 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
4064 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
4065 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
4066 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
4067 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
4068 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
4069 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
4070 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
4071 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
4072 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
4073 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
4074 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
4075 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
4076 #define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
4077 #define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
4078 #define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
4079 #define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
4085 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
4087 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
4088 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
4089 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
4090 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
4092 #define BNX2_RPM_DEBUG9_EO_XI (1L<<5)
4093 #define BNX2_RPM_DEBUG9_AEOF_DE_XI (1L<<6)
4094 #define BNX2_RPM_DEBUG9_SO_XI (1L<<7)
4099 #define BNX2_RPM_DEBUG9_DATA_IN_VL_XI (1L<<30)
4100 #define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI (1L<<31)
4120 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD (1L<<28)
4121 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE (1L<<29)
4122 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT (1L<<30)
4123 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR (1L<<31)
4127 #define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR (1L<<30)
4128 #define BNX2_RPM_ACPI_PATTERN_CTRL_WR (1L<<31)
4176 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0L<<0)
4177 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1L<<0)
4178 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2L<<0)
4179 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3L<<0)
4181 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0L<<2)
4182 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI (1L<<2)
4183 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2)
4184 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2)
4201 #define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
4202 #define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
4203 #define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
4204 #define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL (1L<<3)
4205 #define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
4206 #define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
4207 #define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE (1L<<6)
4208 #define BNX2_RBUF_COMMAND_CU_ISOLATE_XI (1L<<5)
4209 #define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI (1L<<6)
4210 #define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI (1L<<7)
4222 ((((mtu) - 1500) * 31 / 1000) + 54)
4225 ((((mtu) - 1500) * 39 / 1000) + 66)
4232 #define BNX2_RBUF_FW_BUF_ALLOC_TYPE (1L<<16)
4233 #define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ (1L<<31)
4239 #define BNX2_RBUF_FW_BUF_FREE_TYPE (1L<<25)
4240 #define BNX2_RBUF_FW_BUF_FREE_FREE_REQ (1L<<31)
4246 #define BNX2_RBUF_FW_BUF_SEL_SEL_REQ (1L<<31)
4251 ((((mtu) - 1500) * 4 / 1000) + 5)
4254 ((((mtu) - 1500) * 2 / 100) + 30)
4262 ((((mtu) - 1500) * 12 / 1000) + 18)
4265 ((((mtu) - 1500) * 2 / 100) + 30)
4280 #define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
4281 #define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
4282 #define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
4283 #define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
4284 #define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
4285 #define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
4286 #define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
4287 #define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
4288 #define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
4289 #define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
4290 #define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
4291 #define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
4294 #define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
4295 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
4296 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
4297 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
4298 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
4299 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
4300 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
4303 #define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
4304 #define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
4305 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
4306 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
4307 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
4308 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
4309 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
4310 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
4311 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
4312 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
4313 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
4314 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
4315 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
4316 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
4318 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
4319 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
4320 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
4321 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
4322 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
4323 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
4324 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
4325 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
4326 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
4327 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
4328 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
4329 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
4330 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
4352 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
4356 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
4363 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4366 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4370 #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
4372 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
4373 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
4374 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
4375 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
4376 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
4377 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
4378 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
4379 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
4380 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
4381 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
4382 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
4383 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
4384 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
4385 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
4386 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
4387 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
4394 #define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
4395 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
4396 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
4397 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
4398 #define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
4399 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
4400 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
4401 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
4402 #define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
4403 #define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
4406 #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
4407 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
4408 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
4415 #define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
4416 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
4417 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
4418 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
4419 #define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
4420 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
4421 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
4422 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
4423 #define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
4424 #define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
4427 #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
4428 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
4429 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
4436 #define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
4437 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
4438 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
4439 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
4440 #define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
4441 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
4442 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
4443 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
4444 #define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
4445 #define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
4448 #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
4449 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
4450 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
4461 #define BNX2_MQ_COMMAND_ENABLED (1L<<0)
4462 #define BNX2_MQ_COMMAND_INIT (1L<<1)
4463 #define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
4464 #define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
4465 #define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
4466 #define BNX2_MQ_COMMAND_IDB_CFG_ERROR (1L<<7)
4467 #define BNX2_MQ_COMMAND_IDB_OVERFLOW (1L<<10)
4468 #define BNX2_MQ_COMMAND_NO_BIN_ERROR (1L<<11)
4469 #define BNX2_MQ_COMMAND_NO_MAP_ERROR (1L<<12)
4472 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
4473 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
4474 #define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
4475 #define BNX2_MQ_STATUS_IDB_OFLOW_STAT (1L<<19)
4478 #define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
4479 #define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
4480 #define BNX2_MQ_CONFIG_BIN_MQ_MODE (1L<<2)
4481 #define BNX2_MQ_CONFIG_DIS_IDB_DROP (1L<<3)
4483 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
4484 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
4485 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
4486 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
4487 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
4495 #define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
4579 #define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
4580 #define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
4581 #define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
4584 #define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
4585 #define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
4586 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
4587 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
4588 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
4589 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
4590 #define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
4594 #define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
4595 #define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
4596 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
4598 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
4599 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
4600 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
4601 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
4602 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
4603 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
4604 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
4605 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
4606 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
4607 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
4608 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
4609 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
4610 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
4614 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4617 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4627 #define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
4628 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
4629 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
4630 #define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
4631 #define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
4632 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
4633 #define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
4634 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
4635 #define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
4636 #define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
4639 #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
4640 #define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
4641 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4693 #define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
4694 #define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
4695 #define BNX2_TDMA_COMMAND_CS16_ERR (1L<<5)
4696 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
4697 #define BNX2_TDMA_COMMAND_MASK_CS1 (1L<<20)
4698 #define BNX2_TDMA_COMMAND_MASK_CS2 (1L<<21)
4699 #define BNX2_TDMA_COMMAND_MASK_CS3 (1L<<22)
4700 #define BNX2_TDMA_COMMAND_MASK_CS4 (1L<<23)
4701 #define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR (1L<<24)
4702 #define BNX2_TDMA_COMMAND_OFIFO_CLR (1L<<30)
4703 #define BNX2_TDMA_COMMAND_IFIFO_CLR (1L<<31)
4706 #define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
4707 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
4708 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
4709 #define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
4710 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
4711 #define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
4713 #define BNX2_TDMA_STATUS_OFIFO_OVERFLOW (1L<<30)
4714 #define BNX2_TDMA_STATUS_IFIFO_OVERFLOW (1L<<31)
4717 #define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
4718 #define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
4720 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0 (0L<<2)
4721 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1 (1L<<2)
4722 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2 (2L<<2)
4723 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3 (3L<<2)
4725 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
4730 #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
4731 #define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
4732 #define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
4733 #define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
4734 #define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
4735 #define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
4736 #define BNX2_TDMA_CONFIG_CMPL_ENTRY (1L<<17)
4737 #define BNX2_TDMA_CONFIG_OFIFO_CMP (1L<<19)
4738 #define BNX2_TDMA_CONFIG_OFIFO_CMP_3 (0L<<19)
4739 #define BNX2_TDMA_CONFIG_OFIFO_CMP_2 (1L<<19)
4742 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI (0L<<20)
4743 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI (1L<<20)
4744 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI (2L<<20)
4745 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI (3L<<20)
4746 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI (4L<<20)
4747 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI (5L<<20)
4748 #define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI (1L<<23)
4750 #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI (0L<<24)
4751 #define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI (1L<<24)
4752 #define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI (2L<<24)
4753 #define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI (3L<<24)
4754 #define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI (4L<<24)
4755 #define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI (5L<<24)
4756 #define BNX2_TDMA_CONFIG_HC_BYPASS_XI (1L<<27)
4758 #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI (0L<<28)
4759 #define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI (1L<<28)
4760 #define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI (2L<<28)
4761 #define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI (3L<<28)
4762 #define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI (4L<<28)
4763 #define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI (5L<<28)
4764 #define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI (1L<<31)
4772 #define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
4775 #define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
4776 #define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
4818 #define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
4819 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
4820 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
4821 #define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
4822 #define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
4823 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
4824 #define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
4825 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
4826 #define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
4827 #define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
4830 #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
4831 #define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
4832 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4843 #define BNX2_HC_COMMAND_ENABLE (1L<<0)
4844 #define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
4845 #define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
4846 #define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
4847 #define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
4849 #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
4850 #define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
4851 #define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
4852 #define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
4853 #define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
4854 #define BNX2_HC_COMMAND_MAIN_PWR_INT (1L<<22)
4855 #define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27)
4858 #define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
4859 #define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
4860 #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
4861 #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
4862 #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
4863 #define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
4864 #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
4865 #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
4866 #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
4867 #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
4870 #define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
4871 #define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
4872 #define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
4873 #define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
4874 #define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
4875 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
4876 #define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
4878 #define BNX2_HC_CONFIG_PER_MODE (1L<<16)
4879 #define BNX2_HC_CONFIG_ONE_SHOT (1L<<17)
4880 #define BNX2_HC_CONFIG_USE_INT_PARAM (1L<<18)
4881 #define BNX2_HC_CONFIG_SET_MASK_AT_RD (1L<<19)
4884 #define BNX2_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
4885 #define BNX2_HC_CONFIG_SB_ADDR_INC_128B (1L<<24)
4886 #define BNX2_HC_CONFIG_SB_ADDR_INC_256B (2L<<24)
4887 #define BNX2_HC_CONFIG_SB_ADDR_INC_512B (3L<<24)
4888 #define BNX2_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24)
4889 #define BNX2_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24)
4890 #define BNX2_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24)
4891 #define BNX2_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24)
4892 #define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29)
4893 #define BNX2_HC_CONFIG_UNMASK_ALL (1L<<30)
4894 #define BNX2_HC_CONFIG_TX_SEL (1L<<31)
4946 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
4947 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
4948 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
4949 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
4950 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
4951 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
4952 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
4953 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
4954 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
4955 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
4956 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
4957 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
4958 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
4959 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
4960 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
4961 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
4962 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
4963 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
4964 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
4965 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
4966 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
4967 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
4968 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
4969 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
4970 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
4971 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
4972 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
4973 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
4974 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
4975 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
4976 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
4977 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
4978 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
4979 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
4980 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
4981 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
4982 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
4983 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
4984 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
4985 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
4986 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
4987 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
4988 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
4989 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
4990 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
4991 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
4992 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
4993 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
4994 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
4995 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
4996 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
4997 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
4998 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
4999 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
5000 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
5001 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
5002 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
5003 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
5004 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
5005 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
5006 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
5007 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
5008 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
5009 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
5010 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
5011 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
5012 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
5013 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
5014 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
5015 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
5016 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
5017 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
5018 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
5019 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
5020 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
5021 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
5022 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
5023 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
5024 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
5025 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
5026 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
5027 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
5028 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
5029 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
5030 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
5031 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
5032 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
5033 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
5034 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
5035 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
5036 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
5037 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
5038 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
5039 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
5040 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
5041 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
5042 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
5043 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
5044 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
5045 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
5046 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
5047 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
5048 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
5049 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
5050 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
5051 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
5052 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
5053 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
5054 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
5055 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
5056 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
5057 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
5058 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
5059 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
5060 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
5061 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
5062 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
5063 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
5064 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
5065 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
5066 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
5067 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
5072 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0)
5073 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0)
5074 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0)
5075 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0)
5076 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0)
5077 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0)
5078 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0)
5079 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0)
5080 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0)
5081 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0)
5082 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0)
5083 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0)
5084 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0)
5085 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0)
5086 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0)
5087 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0)
5088 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0)
5089 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0)
5090 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0)
5091 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0)
5092 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0)
5093 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0)
5094 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0)
5095 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0)
5096 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0)
5097 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0)
5098 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0)
5099 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0)
5100 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0)
5101 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0)
5102 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0)
5103 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0)
5104 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0)
5105 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0)
5106 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0)
5107 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0)
5108 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0)
5109 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0)
5110 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0)
5111 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0)
5112 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0)
5113 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0)
5114 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0)
5115 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0)
5116 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0)
5117 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0)
5118 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0)
5119 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0)
5120 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0)
5121 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0)
5122 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0)
5123 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0)
5124 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0)
5125 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0)
5126 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0)
5127 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0)
5128 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0)
5129 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0)
5130 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0)
5131 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0)
5132 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0)
5133 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0)
5134 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0)
5135 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0)
5136 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0)
5137 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0)
5138 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0)
5139 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0)
5209 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
5210 #define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
5211 #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
5212 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
5213 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
5214 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
5215 #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
5216 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
5217 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
5218 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
5219 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
5221 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
5222 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
5223 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
5224 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
5225 #define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
5226 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
5227 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
5228 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
5229 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
5230 #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
5231 #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
5234 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
5235 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
5236 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
5239 #define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
5240 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
5241 #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
5242 #define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
5243 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
5244 #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
5245 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
5246 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
5247 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
5248 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
5249 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
5250 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
5252 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
5253 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
5254 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
5255 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
5256 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
5257 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
5258 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
5259 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
5261 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
5262 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
5263 #define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
5264 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
5265 #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
5267 #define BNX2_HC_VIS_1_INT_B (1L<<27)
5271 #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
5274 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
5286 #define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1)
5287 #define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2)
5288 #define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3)
5289 #define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4)
5290 #define BNX2_HC_SB_CONFIG_1_PER_MODE (1L<<16)
5291 #define BNX2_HC_SB_CONFIG_1_ONE_SHOT (1L<<17)
5292 #define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18)
5328 #define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1)
5329 #define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2)
5330 #define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3)
5331 #define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4)
5332 #define BNX2_HC_SB_CONFIG_2_PER_MODE (1L<<16)
5333 #define BNX2_HC_SB_CONFIG_2_ONE_SHOT (1L<<17)
5334 #define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18)
5370 #define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1)
5371 #define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2)
5372 #define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3)
5373 #define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4)
5374 #define BNX2_HC_SB_CONFIG_3_PER_MODE (1L<<16)
5375 #define BNX2_HC_SB_CONFIG_3_ONE_SHOT (1L<<17)
5376 #define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18)
5412 #define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1)
5413 #define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2)
5414 #define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3)
5415 #define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4)
5416 #define BNX2_HC_SB_CONFIG_4_PER_MODE (1L<<16)
5417 #define BNX2_HC_SB_CONFIG_4_ONE_SHOT (1L<<17)
5418 #define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18)
5454 #define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1)
5455 #define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2)
5456 #define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3)
5457 #define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4)
5458 #define BNX2_HC_SB_CONFIG_5_PER_MODE (1L<<16)
5459 #define BNX2_HC_SB_CONFIG_5_ONE_SHOT (1L<<17)
5460 #define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18)
5496 #define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1)
5497 #define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2)
5498 #define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3)
5499 #define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4)
5500 #define BNX2_HC_SB_CONFIG_6_PER_MODE (1L<<16)
5501 #define BNX2_HC_SB_CONFIG_6_ONE_SHOT (1L<<17)
5502 #define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18)
5538 #define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1)
5539 #define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2)
5540 #define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3)
5541 #define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4)
5542 #define BNX2_HC_SB_CONFIG_7_PER_MODE (1L<<16)
5543 #define BNX2_HC_SB_CONFIG_7_ONE_SHOT (1L<<17)
5544 #define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18)
5580 #define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1)
5581 #define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2)
5582 #define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3)
5583 #define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4)
5584 #define BNX2_HC_SB_CONFIG_8_PER_MODE (1L<<16)
5585 #define BNX2_HC_SB_CONFIG_8_ONE_SHOT (1L<<17)
5586 #define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18)
5621 #define BNX2_HC_SB_CONFIG_SIZE (BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1)
5622 #define BNX2_HC_COMP_PROD_TRIP_OFF (BNX2_HC_COMP_PROD_TRIP_1 - \
5624 #define BNX2_HC_COM_TICKS_OFF (BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1)
5625 #define BNX2_HC_CMD_TICKS_OFF (BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1)
5626 #define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
5628 #define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
5629 #define BNX2_HC_RX_QUICK_CONS_TRIP_OFF (BNX2_HC_RX_QUICK_CONS_TRIP_1 - \
5631 #define BNX2_HC_RX_TICKS_OFF (BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
5639 #define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
5640 #define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
5641 #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5642 #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5643 #define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
5644 #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
5645 #define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
5646 #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5647 #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5648 #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5649 #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5652 #define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
5653 #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
5654 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5655 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5656 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5657 #define BNX2_TXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
5658 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
5659 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5660 #define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
5661 #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5662 #define BNX2_TXP_CPU_STATE_INTERRUPT (1L<<12)
5663 #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5664 #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
5665 #define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
5668 #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5669 #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5670 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5671 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5672 #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5673 #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5674 #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5675 #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5676 #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5677 #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5678 #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5687 #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5692 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
5695 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
5699 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
5700 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5701 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
5708 #define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
5709 #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5710 #define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
5711 #define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
5712 #define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
5713 #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
5714 #define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
5715 #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
5716 #define BNX2_TXP_FTQ_CMD_POP (1L<<30)
5717 #define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
5720 #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
5721 #define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
5722 #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5734 #define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
5735 #define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
5736 #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5737 #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5738 #define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
5739 #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
5740 #define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
5741 #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5742 #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5743 #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5744 #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5747 #define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
5748 #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
5749 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5750 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5751 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5752 #define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED (1L<<6)
5753 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
5754 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5755 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
5756 #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5757 #define BNX2_TPAT_CPU_STATE_INTERRUPT (1L<<12)
5758 #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5759 #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
5760 #define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
5763 #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5764 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5765 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5766 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5767 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5768 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5769 #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5770 #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5771 #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5772 #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5773 #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5782 #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5787 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
5790 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
5794 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
5795 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5796 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
5803 #define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
5804 #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
5805 #define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
5806 #define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
5807 #define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
5808 #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
5809 #define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
5810 #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
5811 #define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
5812 #define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
5815 #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
5816 #define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
5817 #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5829 #define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
5830 #define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
5831 #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5832 #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5833 #define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
5834 #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
5835 #define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
5836 #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5837 #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5838 #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5839 #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5842 #define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
5843 #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
5844 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5845 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5846 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5847 #define BNX2_RXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
5848 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
5849 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5850 #define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
5851 #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5852 #define BNX2_RXP_CPU_STATE_INTERRUPT (1L<<12)
5853 #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5854 #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
5855 #define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
5858 #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5859 #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5860 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5861 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5862 #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5863 #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5864 #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5865 #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5866 #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5867 #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5868 #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5877 #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5882 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
5885 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
5889 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
5890 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5891 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
5896 #define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
5898 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
5899 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
5900 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
5901 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
5902 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
5903 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
5904 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
5905 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
5906 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
5907 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
5908 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
5909 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
5910 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
5911 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
5912 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
5913 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
5920 #define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
5921 #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
5922 #define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
5923 #define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
5924 #define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
5925 #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
5926 #define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
5927 #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
5928 #define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
5929 #define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
5932 #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
5933 #define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
5934 #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
5941 #define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
5942 #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5943 #define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
5944 #define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
5945 #define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
5946 #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
5947 #define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
5948 #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
5949 #define BNX2_RXP_FTQ_CMD_POP (1L<<30)
5950 #define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
5953 #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
5954 #define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
5955 #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5975 #define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
5976 #define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
5977 #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5978 #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5979 #define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
5980 #define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
5981 #define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
5982 #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5983 #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5984 #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5985 #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5988 #define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
5989 #define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
5990 #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5991 #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5992 #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5993 #define BNX2_COM_CPU_STATE_BAD_PC_HALTED (1L<<6)
5994 #define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
5995 #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5996 #define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
5997 #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5998 #define BNX2_COM_CPU_STATE_INTERRUPT (1L<<12)
5999 #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
6000 #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
6001 #define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
6004 #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
6005 #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
6006 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
6007 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
6008 #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
6009 #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
6010 #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
6011 #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
6012 #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
6013 #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
6014 #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
6023 #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
6028 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
6031 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
6035 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
6036 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6037 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
6042 #define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
6044 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
6045 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
6046 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
6047 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
6048 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
6049 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
6050 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
6051 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
6052 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
6053 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
6054 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
6055 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
6056 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
6057 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
6058 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
6059 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
6066 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
6067 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6068 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
6069 #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
6070 #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
6071 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
6072 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
6073 #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
6074 #define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
6075 #define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
6078 #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
6079 #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
6080 #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
6087 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
6088 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6089 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
6090 #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
6091 #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
6092 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
6093 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
6094 #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
6095 #define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
6096 #define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
6099 #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
6100 #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
6101 #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
6108 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
6109 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6110 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
6111 #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
6112 #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
6113 #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
6114 #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
6115 #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
6116 #define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
6117 #define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
6120 #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
6121 #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
6122 #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
6141 #define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
6142 #define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
6143 #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
6144 #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
6145 #define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
6146 #define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
6147 #define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
6148 #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
6149 #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
6150 #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
6151 #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
6154 #define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
6155 #define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
6156 #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
6157 #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
6158 #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
6159 #define BNX2_CP_CPU_STATE_BAD_PC_HALTED (1L<<6)
6160 #define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
6161 #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
6162 #define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
6163 #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
6164 #define BNX2_CP_CPU_STATE_INTERRUPT (1L<<12)
6165 #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
6166 #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
6167 #define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
6170 #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
6171 #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
6172 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
6173 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
6174 #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
6175 #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
6176 #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
6177 #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
6178 #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
6179 #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
6180 #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
6189 #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
6194 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
6197 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
6201 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
6202 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6203 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
6208 #define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
6210 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
6211 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
6212 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
6213 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
6214 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
6215 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
6216 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
6217 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
6218 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
6219 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
6220 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
6221 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
6222 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
6223 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
6224 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
6225 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
6232 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
6233 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6234 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
6235 #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
6236 #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
6237 #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
6238 #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
6239 #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
6240 #define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
6241 #define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
6244 #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
6245 #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
6246 #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
6260 #define BNX2_MCP_MCP_CONTROL_SMBUS_SEL (1L<<30)
6261 #define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE (1L<<31)
6264 #define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL (1L<<29)
6265 #define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (1L<<30)
6266 #define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT (1L<<31)
6269 #define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (1L<<31)
6273 #define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID (1L<<31)
6277 #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (1L<<30)
6278 #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (1L<<31)
6281 #define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET (1L<<31)
6285 #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN (1L<<29)
6286 #define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE (1L<<30)
6287 #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE (1L<<31)
6290 #define BNX2_MCP_ACCESS_LOCK_LOCK (1L<<31)
6293 #define BNX2_MCP_TOE_ID_FUNCTION_ID (1L<<31)
6304 #define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL (1L<<31)
6307 #define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL (1L<<31)
6310 #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL (1L<<31)
6313 #define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
6314 #define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
6315 #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
6316 #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
6317 #define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
6318 #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
6319 #define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
6320 #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
6321 #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
6322 #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
6323 #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
6326 #define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
6327 #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
6328 #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
6329 #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
6330 #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
6331 #define BNX2_MCP_CPU_STATE_BAD_PC_HALTED (1L<<6)
6332 #define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
6333 #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
6334 #define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
6335 #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
6336 #define BNX2_MCP_CPU_STATE_INTERRUPT (1L<<12)
6337 #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
6338 #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
6339 #define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
6342 #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
6343 #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
6344 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
6345 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
6346 #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
6347 #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
6348 #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
6349 #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
6350 #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
6351 #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
6352 #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
6361 #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
6366 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
6369 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
6373 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
6374 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6375 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
6382 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
6383 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6384 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
6385 #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
6386 #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
6387 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
6388 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
6389 #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
6390 #define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
6391 #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
6394 #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
6395 #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
6396 #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
6420 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
6533 #define MIN_ETHERNET_PACKET_SIZE (ETH_ZLEN - ETH_HLEN)
6543 #define BNX2_MAX_UNICAST_ADDRESSES (BNX2_END_UNICAST_ADDRESS_INDEX - \
6558 #define BNX2_MAX_TX_DESC_CNT (BNX2_TX_DESC_CNT - 1)
6563 #define BNX2_MAX_RX_DESC_CNT (BNX2_RX_DESC_CNT - 1)
6568 #define BNX2_NEXT_TX_BD(x) (((x) & (BNX2_MAX_TX_DESC_CNT - 1)) == \
6569 (BNX2_MAX_TX_DESC_CNT - 1)) ? \
6574 #define BNX2_NEXT_RX_BD(x) (((x) & (BNX2_MAX_RX_DESC_CNT - 1)) == \
6575 (BNX2_MAX_RX_DESC_CNT - 1)) ? \
6578 #define BNX2_RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
6579 #define BNX2_RX_PG_RING_IDX(x) ((x) & bp->rx_max_pg_ring_idx)
6581 #define BNX2_RX_RING(x) (((x) & ~BNX2_MAX_RX_DESC_CNT) >> (BNX2_PAGE_BITS - 4))
6587 #define CTX_MASK (CTX_SIZE - 1)
6593 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
6599 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
6658 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
6664 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
6670 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
6676 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
6682 #define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1)
6866 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6867 #define BNX2_CHIP(bp) (((bp)->chip_id) & 0xffff0000)
6872 #define BNX2_CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
6877 #define BNX2_CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
6878 #define BNX2_CHIP_BOND(bp) (((bp)->chip_id) & 0x0000000f)
6880 #define BNX2_CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
7007 readl(bp->regview + offset)
7010 writel(val, bp->regview + offset)
7013 writew(val, bp->regview + offset)
7067 #define RV2P_BD_PAGE_SIZE ((BNX2_PAGE_SIZE / 16) - 1)
7075 * pulse to determine when to switch to an OS-absent mode. */
7081 * running and there won't be any firmware-driver synchronization during a
7458 netdev_err(bp->dev, "DEBUG: %08x: %08x %08x %08x %08x\n", \