243 static void bnx2_init_napi(struct bnx2 *bp);
244 static void bnx2_del_napi(struct bnx2 *bp);
246 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)  in bnx2_tx_avail()  argument
259 	return bp->tx_ring_size - diff;  in bnx2_tx_avail()
263 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)  in bnx2_reg_rd_ind()  argument
268 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_reg_rd_ind()
269 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
270 	val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);  in bnx2_reg_rd_ind()
271 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_reg_rd_ind()
276 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_reg_wr_ind()  argument
280 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_reg_wr_ind()
281 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
282 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
283 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_reg_wr_ind()
287 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_shmem_wr()  argument
289 	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);  in bnx2_shmem_wr()
293 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)  in bnx2_shmem_rd()  argument
295 	return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);  in bnx2_shmem_rd()
299 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)  in bnx2_ctx_wr()  argument
304 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_ctx_wr()
305 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_ctx_wr()
308 		BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
309 		BNX2_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
312 			val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);  in bnx2_ctx_wr()
318 		BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
319 		BNX2_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
321 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_ctx_wr()
328 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_drv_ctl()  local
333 		bnx2_reg_wr_ind(bp, io->offset, io->data);  in bnx2_drv_ctl()
336 		io->data = bnx2_reg_rd_ind(bp, io->offset);  in bnx2_drv_ctl()
339 		bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);  in bnx2_drv_ctl()
347 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)  in bnx2_setup_cnic_irq_info()  argument
349 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_setup_cnic_irq_info()
350 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_setup_cnic_irq_info()
353 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_setup_cnic_irq_info()
356 		sb_id = bp->irq_nvecs;  in bnx2_setup_cnic_irq_info()
366 	cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;  in bnx2_setup_cnic_irq_info()
370 	cp->irq_arr[0].status_blk_map = bp->status_blk_mapping;  in bnx2_setup_cnic_irq_info()
378 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_register_cnic()  local
379 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_register_cnic()
387 	if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))  in bnx2_register_cnic()
390 	bp->cnic_data = data;  in bnx2_register_cnic()
391 	rcu_assign_pointer(bp->cnic_ops, ops);  in bnx2_register_cnic()
396 	bnx2_setup_cnic_irq_info(bp);  in bnx2_register_cnic()
403 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_unregister_cnic()  local
404 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_unregister_cnic()
405 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_unregister_cnic()
407 	mutex_lock(&bp->cnic_lock);  in bnx2_unregister_cnic()
410 	RCU_INIT_POINTER(bp->cnic_ops, NULL);  in bnx2_unregister_cnic()
411 	mutex_unlock(&bp->cnic_lock);  in bnx2_unregister_cnic()
418 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_cnic_probe()  local
419 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_cnic_probe()
425 	cp->chip_id = bp->chip_id;  in bnx2_cnic_probe()
426 	cp->pdev = bp->pdev;  in bnx2_cnic_probe()
427 	cp->io_base = bp->regview;  in bnx2_cnic_probe()
436 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
441 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_stop()
442 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_stop()
443 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_stop()
446 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_stop()
448 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_stop()
452 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
457 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_start()
458 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_start()
459 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_start()
461 		if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_cnic_start()
462 			struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_cnic_start()
467 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_start()
469 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_start()
475 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
480 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
487 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)  in bnx2_read_phy()  argument
492 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
493 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
496 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
497 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
502 	val1 = (bp->phy_addr << 21) | (reg << 16) |  in bnx2_read_phy()
505 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
510 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
514 			val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
530 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
531 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
534 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
535 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
544 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)  in bnx2_write_phy()  argument
549 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
550 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
553 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
554 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
559 	val1 = (bp->phy_addr << 21) | (reg << 16) | val |  in bnx2_write_phy()
562 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
567 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_write_phy()
579 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
580 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
583 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
584 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
593 bnx2_disable_int(struct bnx2 *bp)  in bnx2_disable_int()  argument
598 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_disable_int()
599 		bnapi = &bp->bnx2_napi[i];  in bnx2_disable_int()
600 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
603 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_disable_int()
607 bnx2_enable_int(struct bnx2 *bp)  in bnx2_enable_int()  argument
612 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_enable_int()
613 		bnapi = &bp->bnx2_napi[i];  in bnx2_enable_int()
615 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
620 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
624 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
628 bnx2_disable_int_sync(struct bnx2 *bp)  in bnx2_disable_int_sync()  argument
632 	atomic_inc(&bp->intr_sem);  in bnx2_disable_int_sync()
633 	if (!netif_running(bp->dev))  in bnx2_disable_int_sync()
636 	bnx2_disable_int(bp);  in bnx2_disable_int_sync()
637 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_disable_int_sync()
638 		synchronize_irq(bp->irq_tbl[i].vector);  in bnx2_disable_int_sync()
642 bnx2_napi_disable(struct bnx2 *bp)  in bnx2_napi_disable()  argument
646 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_disable()
647 		napi_disable(&bp->bnx2_napi[i].napi);  in bnx2_napi_disable()
651 bnx2_napi_enable(struct bnx2 *bp)  in bnx2_napi_enable()  argument
655 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_enable()
656 		napi_enable(&bp->bnx2_napi[i].napi);  in bnx2_napi_enable()
660 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)  in bnx2_netif_stop()  argument
663 		bnx2_cnic_stop(bp);  in bnx2_netif_stop()
664 	if (netif_running(bp->dev)) {  in bnx2_netif_stop()
665 		bnx2_napi_disable(bp);  in bnx2_netif_stop()
666 		netif_tx_disable(bp->dev);  in bnx2_netif_stop()
668 	bnx2_disable_int_sync(bp);  in bnx2_netif_stop()
669 	netif_carrier_off(bp->dev);	/* prevent tx timeout */  in bnx2_netif_stop()
673 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)  in bnx2_netif_start()  argument
675 	if (atomic_dec_and_test(&bp->intr_sem)) {  in bnx2_netif_start()
676 		if (netif_running(bp->dev)) {  in bnx2_netif_start()
677 			netif_tx_wake_all_queues(bp->dev);  in bnx2_netif_start()
678 			spin_lock_bh(&bp->phy_lock);  in bnx2_netif_start()
679 			if (bp->link_up)  in bnx2_netif_start()
680 				netif_carrier_on(bp->dev);  in bnx2_netif_start()
681 			spin_unlock_bh(&bp->phy_lock);  in bnx2_netif_start()
682 			bnx2_napi_enable(bp);  in bnx2_netif_start()
683 			bnx2_enable_int(bp);  in bnx2_netif_start()
685 				bnx2_cnic_start(bp);  in bnx2_netif_start()
691 bnx2_free_tx_mem(struct bnx2 *bp)  in bnx2_free_tx_mem()  argument
695 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_mem()
696 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_mem()
700 			dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_free_tx_mem()
711 bnx2_free_rx_mem(struct bnx2 *bp)  in bnx2_free_rx_mem()  argument
715 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_mem()
716 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_mem()
720 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_free_rx_mem()
722 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
730 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_free_rx_mem()
732 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
743 bnx2_alloc_tx_mem(struct bnx2 *bp)  in bnx2_alloc_tx_mem()  argument
747 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_alloc_tx_mem()
748 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_tx_mem()
756 			dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_alloc_tx_mem()
765 bnx2_alloc_rx_mem(struct bnx2 *bp)  in bnx2_alloc_rx_mem()  argument
769 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_alloc_rx_mem()
770 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_rx_mem()
775 			vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring));  in bnx2_alloc_rx_mem()
779 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_alloc_rx_mem()
781 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
790 		if (bp->rx_pg_ring_size) {  in bnx2_alloc_rx_mem()
793 						   bp->rx_max_pg_ring));  in bnx2_alloc_rx_mem()
799 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_alloc_rx_mem()
801 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
816 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_free_stats_blk()  local
818 	if (bp->status_blk) {  in bnx2_free_stats_blk()
819 		dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_free_stats_blk()
820 				  bp->status_blk,  in bnx2_free_stats_blk()
821 				  bp->status_blk_mapping);  in bnx2_free_stats_blk()
822 		bp->status_blk = NULL;  in bnx2_free_stats_blk()
823 		bp->stats_blk = NULL;  in bnx2_free_stats_blk()
832 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_alloc_stats_blk()  local
836 	if (bp->flags & BNX2_FLAG_MSIX_CAP)  in bnx2_alloc_stats_blk()
839 	bp->status_stats_size = status_blk_size +  in bnx2_alloc_stats_blk()
841 	status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_alloc_stats_blk()
842 					&bp->status_blk_mapping, GFP_KERNEL);  in bnx2_alloc_stats_blk()
846 	bp->status_blk = status_blk;  in bnx2_alloc_stats_blk()
847 	bp->stats_blk = status_blk + status_blk_size;  in bnx2_alloc_stats_blk()
848 	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;  in bnx2_alloc_stats_blk()
854 bnx2_free_mem(struct bnx2 *bp)  in bnx2_free_mem()  argument
857 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_free_mem()
859 	bnx2_free_tx_mem(bp);  in bnx2_free_mem()
860 	bnx2_free_rx_mem(bp);  in bnx2_free_mem()
862 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_free_mem()
863 		if (bp->ctx_blk[i]) {  in bnx2_free_mem()
864 			dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,  in bnx2_free_mem()
865 					  bp->ctx_blk[i],  in bnx2_free_mem()
866 					  bp->ctx_blk_mapping[i]);  in bnx2_free_mem()
867 			bp->ctx_blk[i] = NULL;  in bnx2_free_mem()
876 bnx2_alloc_mem(struct bnx2 *bp)  in bnx2_alloc_mem()  argument
881 	bnapi = &bp->bnx2_napi[0];  in bnx2_alloc_mem()
882 	bnapi->status_blk.msi = bp->status_blk;  in bnx2_alloc_mem()
887 	if (bp->flags & BNX2_FLAG_MSIX_CAP) {  in bnx2_alloc_mem()
888 		for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_alloc_mem()
891 			bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_mem()
893 			sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);  in bnx2_alloc_mem()
903 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_alloc_mem()
904 		bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;  in bnx2_alloc_mem()
905 		if (bp->ctx_pages == 0)  in bnx2_alloc_mem()
906 			bp->ctx_pages = 1;  in bnx2_alloc_mem()
907 		for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_alloc_mem()
908 			bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_mem()
910 						&bp->ctx_blk_mapping[i],  in bnx2_alloc_mem()
912 			if (!bp->ctx_blk[i])  in bnx2_alloc_mem()
917 	err = bnx2_alloc_rx_mem(bp);  in bnx2_alloc_mem()
921 	err = bnx2_alloc_tx_mem(bp);  in bnx2_alloc_mem()
928 	bnx2_free_mem(bp);  in bnx2_alloc_mem()
933 bnx2_report_fw_link(struct bnx2 *bp)  in bnx2_report_fw_link()  argument
937 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_report_fw_link()
940 	if (bp->link_up) {  in bnx2_report_fw_link()
943 		switch (bp->line_speed) {  in bnx2_report_fw_link()
945 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
951 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
957 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
963 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
972 		if (bp->autoneg) {  in bnx2_report_fw_link()
975 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
976 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
979 			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)  in bnx2_report_fw_link()
988 	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);  in bnx2_report_fw_link()
992 bnx2_xceiver_str(struct bnx2 *bp)  in bnx2_xceiver_str()  argument
994 	return (bp->phy_port == PORT_FIBRE) ? "SerDes" :  in bnx2_xceiver_str()
995 		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :  in bnx2_xceiver_str()
1000 bnx2_report_link(struct bnx2 *bp)  in bnx2_report_link()  argument
1002 	if (bp->link_up) {  in bnx2_report_link()
1003 		netif_carrier_on(bp->dev);  in bnx2_report_link()
1004 		netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",  in bnx2_report_link()
1005 			    bnx2_xceiver_str(bp),  in bnx2_report_link()
1006 			    bp->line_speed,  in bnx2_report_link()
1007 			    bp->duplex == DUPLEX_FULL ? "full" : "half");  in bnx2_report_link()
1009 		if (bp->flow_ctrl) {  in bnx2_report_link()
1010 			if (bp->flow_ctrl & FLOW_CTRL_RX) {  in bnx2_report_link()
1012 				if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_report_link()
1022 		netif_carrier_off(bp->dev);  in bnx2_report_link()
1023 		netdev_err(bp->dev, "NIC %s Link is Down\n",  in bnx2_report_link()
1024 			   bnx2_xceiver_str(bp));  in bnx2_report_link()
1027 	bnx2_report_fw_link(bp);  in bnx2_report_link()
1031 bnx2_resolve_flow_ctrl(struct bnx2 *bp)  in bnx2_resolve_flow_ctrl()  argument
1035 	bp->flow_ctrl = 0;  in bnx2_resolve_flow_ctrl()
1036 	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_resolve_flow_ctrl()
1039 		if (bp->duplex == DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1040 			bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_resolve_flow_ctrl()
1045 	if (bp->duplex != DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1049 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_resolve_flow_ctrl()
1050 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_resolve_flow_ctrl()
1053 		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_resolve_flow_ctrl()
1055 			bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1057 			bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1061 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_resolve_flow_ctrl()
1062 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_resolve_flow_ctrl()
1064 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_resolve_flow_ctrl()
1085 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1088 				bp->flow_ctrl = FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1093 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1101 			bp->flow_ctrl = FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1107 bnx2_5709s_linkup(struct bnx2 *bp)  in bnx2_5709s_linkup()  argument
1111 	bp->link_up = 1;  in bnx2_5709s_linkup()
1113 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);  in bnx2_5709s_linkup()
1114 	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);  in bnx2_5709s_linkup()
1115 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_5709s_linkup()
1117 	if ((bp->autoneg & AUTONEG_SPEED) == 0) {  in bnx2_5709s_linkup()
1118 		bp->line_speed = bp->req_line_speed;  in bnx2_5709s_linkup()
1119 		bp->duplex = bp->req_duplex;  in bnx2_5709s_linkup()
1125 			bp->line_speed = SPEED_10;  in bnx2_5709s_linkup()
1128 			bp->line_speed = SPEED_100;  in bnx2_5709s_linkup()
1132 			bp->line_speed = SPEED_1000;  in bnx2_5709s_linkup()
1135 			bp->line_speed = SPEED_2500;  in bnx2_5709s_linkup()
1139 		bp->duplex = DUPLEX_FULL;  in bnx2_5709s_linkup()
1141 		bp->duplex = DUPLEX_HALF;  in bnx2_5709s_linkup()
1146 bnx2_5708s_linkup(struct bnx2 *bp)  in bnx2_5708s_linkup()  argument
1150 	bp->link_up = 1;  in bnx2_5708s_linkup()
1151 	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_5708s_linkup()
1154 			bp->line_speed = SPEED_10;  in bnx2_5708s_linkup()
1157 			bp->line_speed = SPEED_100;  in bnx2_5708s_linkup()
1160 			bp->line_speed = SPEED_1000;  in bnx2_5708s_linkup()
1163 			bp->line_speed = SPEED_2500;  in bnx2_5708s_linkup()
1167 		bp->duplex = DUPLEX_FULL;  in bnx2_5708s_linkup()
1169 		bp->duplex = DUPLEX_HALF;  in bnx2_5708s_linkup()
1175 bnx2_5706s_linkup(struct bnx2 *bp)  in bnx2_5706s_linkup()  argument
1179 	bp->link_up = 1;  in bnx2_5706s_linkup()
1180 	bp->line_speed = SPEED_1000;  in bnx2_5706s_linkup()
1182 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706s_linkup()
1184 		bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1187 		bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1194 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_5706s_linkup()
1195 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_5706s_linkup()
1201 			bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1204 			bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1212 bnx2_copper_linkup(struct bnx2 *bp)  in bnx2_copper_linkup()  argument
1216 	bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1218 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_copper_linkup()
1222 		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);  in bnx2_copper_linkup()
1223 		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);  in bnx2_copper_linkup()
1227 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1228 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1231 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1232 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1235 			bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_copper_linkup()
1236 			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_copper_linkup()
1240 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1241 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1244 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1245 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1248 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1249 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1252 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1253 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1256 				bp->line_speed = 0;  in bnx2_copper_linkup()
1257 				bp->link_up = 0;  in bnx2_copper_linkup()
1263 			bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1266 			bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1269 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1272 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1276 	if (bp->link_up) {  in bnx2_copper_linkup()
1279 		bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);  in bnx2_copper_linkup()
1281 			bp->phy_flags |= BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1288 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)  in bnx2_init_rx_context()  argument
1296 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_init_rx_context()
1299 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);  in bnx2_init_rx_context()
1303 bnx2_init_all_rx_contexts(struct bnx2 *bp)  in bnx2_init_all_rx_contexts()  argument
1308 	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {  in bnx2_init_all_rx_contexts()
1311 		bnx2_init_rx_context(bp, cid);  in bnx2_init_all_rx_contexts()
1316 bnx2_set_mac_link(struct bnx2 *bp)  in bnx2_set_mac_link()  argument
1320 	BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1321 	if (bp->link_up && (bp->line_speed == SPEED_1000) &&  in bnx2_set_mac_link()
1322 		(bp->duplex == DUPLEX_HALF)) {  in bnx2_set_mac_link()
1323 		BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1327 	val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_link()
1333 	if (bp->link_up) {  in bnx2_set_mac_link()
1334 		switch (bp->line_speed) {  in bnx2_set_mac_link()
1336 				if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {  in bnx2_set_mac_link()
1357 	if (bp->duplex == DUPLEX_HALF)  in bnx2_set_mac_link()
1359 	BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1362 	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1364 	if (bp->flow_ctrl & FLOW_CTRL_RX)  in bnx2_set_mac_link()
1365 		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1366 	BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1369 	val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);  in bnx2_set_mac_link()
1372 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_set_mac_link()
1374 	BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1377 	BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1379 	bnx2_init_all_rx_contexts(bp);  in bnx2_set_mac_link()
1383 bnx2_enable_bmsr1(struct bnx2 *bp)  in bnx2_enable_bmsr1()  argument
1385 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_enable_bmsr1()
1386 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_enable_bmsr1()
1387 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_bmsr1()
1392 bnx2_disable_bmsr1(struct bnx2 *bp)  in bnx2_disable_bmsr1()  argument
1394 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_disable_bmsr1()
1395 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_disable_bmsr1()
1396 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_bmsr1()
1401 bnx2_test_and_enable_2g5(struct bnx2 *bp)  in bnx2_test_and_enable_2g5()  argument
1406 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_enable_2g5()
1409 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_test_and_enable_2g5()
1410 		bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_test_and_enable_2g5()
1412 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1413 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_enable_2g5()
1415 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_enable_2g5()
1418 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_enable_2g5()
1422 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1423 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_enable_2g5()
1430 bnx2_test_and_disable_2g5(struct bnx2 *bp)  in bnx2_test_and_disable_2g5()  argument
1435 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_disable_2g5()
1438 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1439 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_disable_2g5()
1441 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_disable_2g5()
1444 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_disable_2g5()
1448 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1449 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_disable_2g5()
1456 bnx2_enable_forced_2g5(struct bnx2 *bp)  in bnx2_enable_forced_2g5()  argument
1461 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_enable_forced_2g5()
1464 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_enable_forced_2g5()
1467 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1469 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_enable_forced_2g5()
1473 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_enable_forced_2g5()
1476 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1478 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1480 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_enable_forced_2g5()
1481 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1491 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_enable_forced_2g5()
1493 		if (bp->req_duplex == DUPLEX_FULL)  in bnx2_enable_forced_2g5()
1496 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_enable_forced_2g5()
1500 bnx2_disable_forced_2g5(struct bnx2 *bp)  in bnx2_disable_forced_2g5()  argument
1505 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_disable_forced_2g5()
1508 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_disable_forced_2g5()
1511 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1513 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_disable_forced_2g5()
1515 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_disable_forced_2g5()
1518 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1520 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1522 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_disable_forced_2g5()
1523 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1533 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_disable_forced_2g5()
1535 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_disable_forced_2g5()
1539 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)  in bnx2_5706s_force_link_dn()  argument
1543 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);  in bnx2_5706s_force_link_dn()
1544 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_5706s_force_link_dn()
1546 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);  in bnx2_5706s_force_link_dn()
1548 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);  in bnx2_5706s_force_link_dn()
1552 bnx2_set_link(struct bnx2 *bp)  in bnx2_set_link()  argument
1557 	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {  in bnx2_set_link()
1558 		bp->link_up = 1;  in bnx2_set_link()
1562 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_set_link()
1565 	link_up = bp->link_up;  in bnx2_set_link()
1567 	bnx2_enable_bmsr1(bp);  in bnx2_set_link()
1568 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1569 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1570 	bnx2_disable_bmsr1(bp);  in bnx2_set_link()
1572 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1573 	    (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {  in bnx2_set_link()
1576 		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {  in bnx2_set_link()
1577 			bnx2_5706s_force_link_dn(bp, 0);  in bnx2_set_link()
1578 			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_set_link()
1580 		val = BNX2_RD(bp, BNX2_EMAC_STATUS);  in bnx2_set_link()
1582 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_set_link()
1583 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1584 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1594 		bp->link_up = 1;  in bnx2_set_link()
1596 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_link()
1597 			if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_set_link()
1598 				bnx2_5706s_linkup(bp);  in bnx2_set_link()
1599 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_set_link()
1600 				bnx2_5708s_linkup(bp);  in bnx2_set_link()
1601 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_set_link()
1602 				bnx2_5709s_linkup(bp);  in bnx2_set_link()
1605 			bnx2_copper_linkup(bp);  in bnx2_set_link()
1607 		bnx2_resolve_flow_ctrl(bp);  in bnx2_set_link()
1610 		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1611 		    (bp->autoneg & AUTONEG_SPEED))  in bnx2_set_link()
1612 			bnx2_disable_forced_2g5(bp);  in bnx2_set_link()
1614 		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {  in bnx2_set_link()
1617 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_set_link()
1619 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_set_link()
1621 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_set_link()
1623 		bp->link_up = 0;  in bnx2_set_link()
1626 	if (bp->link_up != link_up) {  in bnx2_set_link()
1627 		bnx2_report_link(bp);  in bnx2_set_link()
1630 	bnx2_set_mac_link(bp);  in bnx2_set_link()
1636 bnx2_reset_phy(struct bnx2 *bp)  in bnx2_reset_phy()  argument
1641         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);  in bnx2_reset_phy()
1647 		bnx2_read_phy(bp, bp->mii_bmcr, &reg);  in bnx2_reset_phy()
1660 bnx2_phy_get_pause_adv(struct bnx2 *bp)  in bnx2_phy_get_pause_adv()  argument
1664 	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==  in bnx2_phy_get_pause_adv()
1667 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1674 	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {  in bnx2_phy_get_pause_adv()
1675 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1682 	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {  in bnx2_phy_get_pause_adv()
1683 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1696 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_remote_phy()  argument
1697 __releases(&bp->phy_lock)  in bnx2_setup_remote_phy()
1698 __acquires(&bp->phy_lock)  in bnx2_setup_remote_phy()
1702 	pause_adv = bnx2_phy_get_pause_adv(bp);  in bnx2_setup_remote_phy()
1704 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_remote_phy()
1706 		if (bp->advertising & ADVERTISED_10baseT_Half)  in bnx2_setup_remote_phy()
1708 		if (bp->advertising & ADVERTISED_10baseT_Full)  in bnx2_setup_remote_phy()
1710 		if (bp->advertising & ADVERTISED_100baseT_Half)  in bnx2_setup_remote_phy()
1712 		if (bp->advertising & ADVERTISED_100baseT_Full)  in bnx2_setup_remote_phy()
1714 		if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_remote_phy()
1716 		if (bp->advertising & ADVERTISED_2500baseX_Full)  in bnx2_setup_remote_phy()
1719 		if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_remote_phy()
1721 		else if (bp->req_line_speed == SPEED_1000)  in bnx2_setup_remote_phy()
1723 		else if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_remote_phy()
1724 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1728 		} else if (bp->req_line_speed == SPEED_10) {  in bnx2_setup_remote_phy()
1729 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1745 	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);  in bnx2_setup_remote_phy()
1747 	spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1748 	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);  in bnx2_setup_remote_phy()
1749 	spin_lock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1755 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_serdes_phy()  argument
1756 __releases(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1757 __acquires(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1762 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_setup_serdes_phy()
1763 		return bnx2_setup_remote_phy(bp, port);  in bnx2_setup_serdes_phy()
1765 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_setup_serdes_phy()
1769 		if (bp->req_line_speed == SPEED_2500) {  in bnx2_setup_serdes_phy()
1770 			if (!bnx2_test_and_enable_2g5(bp))  in bnx2_setup_serdes_phy()
1772 		} else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1773 			if (bnx2_test_and_disable_2g5(bp))  in bnx2_setup_serdes_phy()
1776 		bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1779 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1783 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_serdes_phy()
1784 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1785 				bnx2_enable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1786 			else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1787 				bnx2_disable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1791 		} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_setup_serdes_phy()
1792 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1798 		if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_serdes_phy()
1808 			if (bp->link_up) {  in bnx2_setup_serdes_phy()
1809 				bnx2_write_phy(bp, bp->mii_adv, adv &  in bnx2_setup_serdes_phy()
1812 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |  in bnx2_setup_serdes_phy()
1815 				bp->link_up = 0;  in bnx2_setup_serdes_phy()
1816 				netif_carrier_off(bp->dev);  in bnx2_setup_serdes_phy()
1817 				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1818 				bnx2_report_link(bp);  in bnx2_setup_serdes_phy()
1820 			bnx2_write_phy(bp, bp->mii_adv, adv);  in bnx2_setup_serdes_phy()
1821 			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1823 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1824 			bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1829 	bnx2_test_and_enable_2g5(bp);  in bnx2_setup_serdes_phy()
1831 	if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_serdes_phy()
1834 	new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_serdes_phy()
1836 	bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1837 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1839 	bp->serdes_an_pending = 0;  in bnx2_setup_serdes_phy()
1842 		if (bp->link_up) {  in bnx2_setup_serdes_phy()
1843 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_serdes_phy()
1844 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1846 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1849 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_serdes_phy()
1850 		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |  in bnx2_setup_serdes_phy()
1860 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_setup_serdes_phy()
1861 		bp->serdes_an_pending = 1;  in bnx2_setup_serdes_phy()
1862 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_setup_serdes_phy()
1864 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1865 		bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1872 	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1887 bnx2_set_default_remote_link(struct bnx2 *bp)  in bnx2_set_default_remote_link()  argument
1891 	if (bp->phy_port == PORT_TP)  in bnx2_set_default_remote_link()
1892 		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);  in bnx2_set_default_remote_link()
1894 		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);  in bnx2_set_default_remote_link()
1897 		bp->req_line_speed = 0;  in bnx2_set_default_remote_link()
1898 		bp->autoneg |= AUTONEG_SPEED;  in bnx2_set_default_remote_link()
1899 		bp->advertising = ADVERTISED_Autoneg;  in bnx2_set_default_remote_link()
1901 			bp->advertising |= ADVERTISED_10baseT_Half;  in bnx2_set_default_remote_link()
1903 			bp->advertising |= ADVERTISED_10baseT_Full;  in bnx2_set_default_remote_link()
1905 			bp->advertising |= ADVERTISED_100baseT_Half;  in bnx2_set_default_remote_link()
1907 			bp->advertising |= ADVERTISED_100baseT_Full;  in bnx2_set_default_remote_link()
1909 			bp->advertising |= ADVERTISED_1000baseT_Full;  in bnx2_set_default_remote_link()
1911 			bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_set_default_remote_link()
1913 		bp->autoneg = 0;  in bnx2_set_default_remote_link()
1914 		bp->advertising = 0;  in bnx2_set_default_remote_link()
1915 		bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_remote_link()
1917 			bp->req_line_speed = SPEED_10;  in bnx2_set_default_remote_link()
1919 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1922 			bp->req_line_speed = SPEED_100;  in bnx2_set_default_remote_link()
1924 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1927 			bp->req_line_speed = SPEED_1000;  in bnx2_set_default_remote_link()
1929 			bp->req_line_speed = SPEED_2500;  in bnx2_set_default_remote_link()
1934 bnx2_set_default_link(struct bnx2 *bp)  in bnx2_set_default_link()  argument
1936 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_set_default_link()
1937 		bnx2_set_default_remote_link(bp);  in bnx2_set_default_link()
1941 	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;  in bnx2_set_default_link()
1942 	bp->req_line_speed = 0;  in bnx2_set_default_link()
1943 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_default_link()
1946 		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1948 		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);  in bnx2_set_default_link()
1951 			bp->autoneg = 0;  in bnx2_set_default_link()
1952 			bp->req_line_speed = bp->line_speed = SPEED_1000;  in bnx2_set_default_link()
1953 			bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_link()
1956 		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1960 bnx2_send_heart_beat(struct bnx2 *bp)  in bnx2_send_heart_beat()  argument
1965 	spin_lock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1966 	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);  in bnx2_send_heart_beat()
1967 	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;  in bnx2_send_heart_beat()
1968 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1969 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
1970 	spin_unlock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1974 bnx2_remote_phy_event(struct bnx2 *bp)  in bnx2_remote_phy_event()  argument
1977 	u8 link_up = bp->link_up;  in bnx2_remote_phy_event()
1980 	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_remote_phy_event()
1983 		bnx2_send_heart_beat(bp);  in bnx2_remote_phy_event()
1988 		bp->link_up = 0;  in bnx2_remote_phy_event()
1992 		bp->link_up = 1;  in bnx2_remote_phy_event()
1994 		bp->duplex = DUPLEX_FULL;  in bnx2_remote_phy_event()
1997 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2000 				bp->line_speed = SPEED_10;  in bnx2_remote_phy_event()
2003 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2007 				bp->line_speed = SPEED_100;  in bnx2_remote_phy_event()
2010 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2013 				bp->line_speed = SPEED_1000;  in bnx2_remote_phy_event()
2016 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2019 				bp->line_speed = SPEED_2500;  in bnx2_remote_phy_event()
2022 				bp->line_speed = 0;  in bnx2_remote_phy_event()
2026 		bp->flow_ctrl = 0;  in bnx2_remote_phy_event()
2027 		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_remote_phy_event()
2029 			if (bp->duplex == DUPLEX_FULL)  in bnx2_remote_phy_event()
2030 				bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_remote_phy_event()
2033 				bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_remote_phy_event()
2035 				bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_remote_phy_event()
2038 		old_port = bp->phy_port;  in bnx2_remote_phy_event()
2040 			bp->phy_port = PORT_FIBRE;  in bnx2_remote_phy_event()
2042 			bp->phy_port = PORT_TP;  in bnx2_remote_phy_event()
2044 		if (old_port != bp->phy_port)  in bnx2_remote_phy_event()
2045 			bnx2_set_default_link(bp);  in bnx2_remote_phy_event()
2048 	if (bp->link_up != link_up)  in bnx2_remote_phy_event()
2049 		bnx2_report_link(bp);  in bnx2_remote_phy_event()
2051 	bnx2_set_mac_link(bp);  in bnx2_remote_phy_event()
2055 bnx2_set_remote_link(struct bnx2 *bp)  in bnx2_set_remote_link()  argument
2059 	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);  in bnx2_set_remote_link()
2062 			bnx2_remote_phy_event(bp);  in bnx2_set_remote_link()
2066 			bnx2_send_heart_beat(bp);  in bnx2_set_remote_link()
2073 bnx2_setup_copper_phy(struct bnx2 *bp)  in bnx2_setup_copper_phy()  argument
2074 __releases(&bp->phy_lock)  in bnx2_setup_copper_phy()
2075 __acquires(&bp->phy_lock)  in bnx2_setup_copper_phy()
2080 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_copper_phy()
2082 	bnx2_read_phy(bp, bp->mii_adv, &adv_reg);  in bnx2_setup_copper_phy()
2086 	new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);  in bnx2_setup_copper_phy()
2088 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_copper_phy()
2092 		new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_copper_phy()
2094 		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);  in bnx2_setup_copper_phy()
2097 		new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);  in bnx2_setup_copper_phy()
2102 			bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2103 			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);  in bnx2_setup_copper_phy()
2104 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |  in bnx2_setup_copper_phy()
2107 		else if (bp->link_up) {  in bnx2_setup_copper_phy()
2111 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2112 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2119 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2122 	if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_copper_phy()
2125 	if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_copper_phy()
2131 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2132 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2136 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_copper_phy()
2137 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2139 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2141 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2142 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2145 		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_copper_phy()
2152 			bp->line_speed = bp->req_line_speed;  in bnx2_setup_copper_phy()
2153 			bp->duplex = bp->req_duplex;  in bnx2_setup_copper_phy()
2154 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2155 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2158 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2159 		bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2165 bnx2_setup_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_phy()  argument
2166 __releases(&bp->phy_lock)  in bnx2_setup_phy()
2167 __acquires(&bp->phy_lock)  in bnx2_setup_phy()
2169 	if (bp->loopback == MAC_LOOPBACK)  in bnx2_setup_phy()
2172 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_setup_phy()
2173 		return bnx2_setup_serdes_phy(bp, port);  in bnx2_setup_phy()
2176 		return bnx2_setup_copper_phy(bp);  in bnx2_setup_phy()
2181 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5709s_phy()  argument
2185 	bp->mii_bmcr = MII_BMCR + 0x10;  in bnx2_init_5709s_phy()
2186 	bp->mii_bmsr = MII_BMSR + 0x10;  in bnx2_init_5709s_phy()
2187 	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;  in bnx2_init_5709s_phy()
2188 	bp->mii_adv = MII_ADVERTISE + 0x10;  in bnx2_init_5709s_phy()
2189 	bp->mii_lpa = MII_LPA + 0x10;  in bnx2_init_5709s_phy()
2190 	bp->mii_up1 = MII_BNX2_OVER1G_UP1;  in bnx2_init_5709s_phy()
2192 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);  in bnx2_init_5709s_phy()
2193 	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);  in bnx2_init_5709s_phy()
2195 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2197 		bnx2_reset_phy(bp);  in bnx2_init_5709s_phy()
2199 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);  in bnx2_init_5709s_phy()
2201 	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);  in bnx2_init_5709s_phy()
2204 	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);  in bnx2_init_5709s_phy()
2206 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_init_5709s_phy()
2207 	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);  in bnx2_init_5709s_phy()
2208 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_init_5709s_phy()
2212 	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);  in bnx2_init_5709s_phy()
2214 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);  in bnx2_init_5709s_phy()
2215 	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);  in bnx2_init_5709s_phy()
2217 	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);  in bnx2_init_5709s_phy()
2219 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);  in bnx2_init_5709s_phy()
2223 	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);  in bnx2_init_5709s_phy()
2225 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2231 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5708s_phy()  argument
2236 		bnx2_reset_phy(bp);  in bnx2_init_5708s_phy()
2238 	bp->mii_up1 = BCM5708S_UP1;  in bnx2_init_5708s_phy()
2240 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);  in bnx2_init_5708s_phy()
2241 	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);  in bnx2_init_5708s_phy()
2242 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2244 	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);  in bnx2_init_5708s_phy()
2246 	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);  in bnx2_init_5708s_phy()
2248 	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);  in bnx2_init_5708s_phy()
2250 	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);  in bnx2_init_5708s_phy()
2252 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {  in bnx2_init_5708s_phy()
2253 		bnx2_read_phy(bp, BCM5708S_UP1, &val);  in bnx2_init_5708s_phy()
2255 		bnx2_write_phy(bp, BCM5708S_UP1, val);  in bnx2_init_5708s_phy()
2258 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_5708s_phy()
2259 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_5708s_phy()
2260 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {  in bnx2_init_5708s_phy()
2262 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2264 		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);  in bnx2_init_5708s_phy()
2266 		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);  in bnx2_init_5708s_phy()
2267 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2270 	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &  in bnx2_init_5708s_phy()
2276 		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_5708s_phy()
2278 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2280 			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);  in bnx2_init_5708s_phy()
2281 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2289 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5706s_phy()  argument
2292 		bnx2_reset_phy(bp);  in bnx2_init_5706s_phy()
2294 	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_init_5706s_phy()
2296 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_5706s_phy()
2297 		BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2299 	if (bp->dev->mtu > ETH_DATA_LEN) {  in bnx2_init_5706s_phy()
2303 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2304 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2305 		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);  in bnx2_init_5706s_phy()
2307 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2308 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2309 		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);  in bnx2_init_5706s_phy()
2314 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2315 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2316 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_5706s_phy()
2318 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2319 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2320 		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);  in bnx2_init_5706s_phy()
2327 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_copper_phy()  argument
2332 		bnx2_reset_phy(bp);  in bnx2_init_copper_phy()
2334 	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {  in bnx2_init_copper_phy()
2335 		bnx2_write_phy(bp, 0x18, 0x0c00);  in bnx2_init_copper_phy()
2336 		bnx2_write_phy(bp, 0x17, 0x000a);  in bnx2_init_copper_phy()
2337 		bnx2_write_phy(bp, 0x15, 0x310b);  in bnx2_init_copper_phy()
2338 		bnx2_write_phy(bp, 0x17, 0x201f);  in bnx2_init_copper_phy()
2339 		bnx2_write_phy(bp, 0x15, 0x9506);  in bnx2_init_copper_phy()
2340 		bnx2_write_phy(bp, 0x17, 0x401f);  in bnx2_init_copper_phy()
2341 		bnx2_write_phy(bp, 0x15, 0x14e2);  in bnx2_init_copper_phy()
2342 		bnx2_write_phy(bp, 0x18, 0x0400);  in bnx2_init_copper_phy()
2345 	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {  in bnx2_init_copper_phy()
2346 		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,  in bnx2_init_copper_phy()
2348 		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_init_copper_phy()
2350 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);  in bnx2_init_copper_phy()
2353 	if (bp->dev->mtu > ETH_DATA_LEN) {  in bnx2_init_copper_phy()
2355 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2356 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2357 		bnx2_write_phy(bp, 0x18, val | 0x4000);  in bnx2_init_copper_phy()
2359 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2360 		bnx2_write_phy(bp, 0x10, val | 0x1);  in bnx2_init_copper_phy()
2363 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2364 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2365 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_copper_phy()
2367 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2368 		bnx2_write_phy(bp, 0x10, val & ~0x1);  in bnx2_init_copper_phy()
2372 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);  in bnx2_init_copper_phy()
2373 	bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);  in bnx2_init_copper_phy()
2377 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_copper_phy()
2380 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);  in bnx2_init_copper_phy()
2386 bnx2_init_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_phy()  argument
2387 __releases(&bp->phy_lock)  in bnx2_init_phy()
2388 __acquires(&bp->phy_lock)  in bnx2_init_phy()
2393 	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;  in bnx2_init_phy()
2394 	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;  in bnx2_init_phy()
2396 	bp->mii_bmcr = MII_BMCR;  in bnx2_init_phy()
2397 	bp->mii_bmsr = MII_BMSR;  in bnx2_init_phy()
2398 	bp->mii_bmsr1 = MII_BMSR;  in bnx2_init_phy()
2399 	bp->mii_adv = MII_ADVERTISE;  in bnx2_init_phy()
2400 	bp->mii_lpa = MII_LPA;  in bnx2_init_phy()
2402 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2404 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_phy()
2407 	bnx2_read_phy(bp, MII_PHYSID1, &val);  in bnx2_init_phy()
2408 	bp->phy_id = val << 16;  in bnx2_init_phy()
2409 	bnx2_read_phy(bp, MII_PHYSID2, &val);  in bnx2_init_phy()
2410 	bp->phy_id |= val & 0xffff;  in bnx2_init_phy()
2412 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_phy()
2413 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_phy()
2414 			rc = bnx2_init_5706s_phy(bp, reset_phy);  in bnx2_init_phy()
2415 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_phy()
2416 			rc = bnx2_init_5708s_phy(bp, reset_phy);  in bnx2_init_phy()
2417 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_phy()
2418 			rc = bnx2_init_5709s_phy(bp, reset_phy);  in bnx2_init_phy()
2421 		rc = bnx2_init_copper_phy(bp, reset_phy);  in bnx2_init_phy()
2426 		rc = bnx2_setup_phy(bp, bp->phy_port);  in bnx2_init_phy()
2432 bnx2_set_mac_loopback(struct bnx2 *bp)  in bnx2_set_mac_loopback()  argument
2436 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_loopback()
2439 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2440 	bp->link_up = 1;  in bnx2_set_mac_loopback()
2447 bnx2_set_phy_loopback(struct bnx2 *bp)  in bnx2_set_phy_loopback()  argument
2452 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2453 	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |  in bnx2_set_phy_loopback()
2455 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2460 		if (bnx2_test_link(bp) == 0)  in bnx2_set_phy_loopback()
2465 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_phy_loopback()
2471 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2472 	bp->link_up = 1;  in bnx2_set_phy_loopback()
2477 bnx2_dump_mcp_state(struct bnx2 *bp)  in bnx2_dump_mcp_state()  argument
2479 	struct net_device *dev = bp->dev;  in bnx2_dump_mcp_state()
2483 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_dump_mcp_state()
2491 		   bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));  in bnx2_dump_mcp_state()
2493 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),  in bnx2_dump_mcp_state()
2494 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),  in bnx2_dump_mcp_state()
2495 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));  in bnx2_dump_mcp_state()
2497 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2498 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2499 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));  in bnx2_dump_mcp_state()
2502 		   bnx2_shmem_rd(bp, BNX2_DRV_MB),  in bnx2_dump_mcp_state()
2503 		   bnx2_shmem_rd(bp, BNX2_FW_MB),  in bnx2_dump_mcp_state()
2504 		   bnx2_shmem_rd(bp, BNX2_LINK_STATUS));  in bnx2_dump_mcp_state()
2505 	pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));  in bnx2_dump_mcp_state()
2507 		   bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),  in bnx2_dump_mcp_state()
2508 		   bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));  in bnx2_dump_mcp_state()
2510 		bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));  in bnx2_dump_mcp_state()
2511 	DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);  in bnx2_dump_mcp_state()
2512 	DP_SHMEM_LINE(bp, 0x3cc);  in bnx2_dump_mcp_state()
2513 	DP_SHMEM_LINE(bp, 0x3dc);  in bnx2_dump_mcp_state()
2514 	DP_SHMEM_LINE(bp, 0x3ec);  in bnx2_dump_mcp_state()
2515 	netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));  in bnx2_dump_mcp_state()
2520 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)  in bnx2_fw_sync()  argument
2525 	bp->fw_wr_seq++;  in bnx2_fw_sync()
2526 	msg_data |= bp->fw_wr_seq;  in bnx2_fw_sync()
2527 	bp->fw_last_msg = msg_data;  in bnx2_fw_sync()
2529 	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2538 		val = bnx2_shmem_rd(bp, BNX2_FW_MB);  in bnx2_fw_sync()
2551 		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2554 			bnx2_dump_mcp_state(bp);  in bnx2_fw_sync()
2567 bnx2_init_5709_context(struct bnx2 *bp)  in bnx2_init_5709_context()  argument
2574 	BNX2_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2576 		val = BNX2_RD(bp, BNX2_CTX_COMMAND);  in bnx2_init_5709_context()
2584 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_init_5709_context()
2587 		if (bp->ctx_blk[i])  in bnx2_init_5709_context()
2588 			memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);  in bnx2_init_5709_context()
2592 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2593 			(bp->ctx_blk_mapping[i] & 0xffffffff) |  in bnx2_init_5709_context()
2595 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2596 			(u64) bp->ctx_blk_mapping[i] >> 32);  in bnx2_init_5709_context()
2597 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2601 			val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);  in bnx2_init_5709_context()
2615 bnx2_init_context(struct bnx2 *bp)  in bnx2_init_context()  argument
2626 		if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_context()
2647 			BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2648 			BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2652 				bnx2_ctx_wr(bp, vcid_addr, offset, 0);  in bnx2_init_context()
2658 bnx2_alloc_bad_rbuf(struct bnx2 *bp)  in bnx2_alloc_bad_rbuf()  argument
2668 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2674 	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2676 		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,  in bnx2_alloc_bad_rbuf()
2679 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);  in bnx2_alloc_bad_rbuf()
2689 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2700 		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);  in bnx2_alloc_bad_rbuf()
2707 bnx2_set_mac_addr(struct bnx2 *bp, const u8 *mac_addr, u32 pos)  in bnx2_set_mac_addr()  argument
2713 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2718 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2722 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_page()  argument
2732 	mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,  in bnx2_alloc_rx_page()
2734 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_page()
2747 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)  in bnx2_free_rx_page()  argument
2755 	dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),  in bnx2_free_rx_page()
2763 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_data()  argument
2771 	data = kmalloc(bp->rx_buf_size, gfp);  in bnx2_alloc_rx_data()
2775 	mapping = dma_map_single(&bp->pdev->dev,  in bnx2_alloc_rx_data()
2777 				 bp->rx_buf_use_size,  in bnx2_alloc_rx_data()
2779 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_data()
2790 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_alloc_rx_data()
2796 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)  in bnx2_phy_event_is_set()  argument
2806 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2808 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
2816 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_phy_int()  argument
2818 	spin_lock(&bp->phy_lock);  in bnx2_phy_int()
2820 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))  in bnx2_phy_int()
2821 		bnx2_set_link(bp);  in bnx2_phy_int()
2822 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))  in bnx2_phy_int()
2823 		bnx2_set_remote_link(bp);  in bnx2_phy_int()
2825 	spin_unlock(&bp->phy_lock);  in bnx2_phy_int()
2842 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_tx_int()  argument
2850 	index = (bnapi - bp->bnx2_napi);  in bnx2_tx_int()
2851 	txq = netdev_get_tx_queue(bp->dev, index);  in bnx2_tx_int()
2883 		dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_tx_int()
2895 			dma_unmap_page(&bp->pdev->dev,  in bnx2_tx_int()
2925 		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {  in bnx2_tx_int()
2928 		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))  in bnx2_tx_int()
2937 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_skb_pages()  argument
2994 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_data()  argument
3003 	dma_sync_single_for_device(&bp->pdev->dev,  in bnx2_reuse_rx_data()
3007 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_reuse_rx_data()
3024 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,  in bnx2_rx_skb()  argument
3032 	err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);  in bnx2_rx_skb()
3034 		bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);  in bnx2_rx_skb()
3040 			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_skb()
3045 	dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,  in bnx2_rx_skb()
3075 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,  in bnx2_rx_skb()
3100 			err = bnx2_alloc_rx_page(bp, rxr,  in bnx2_rx_skb()
3106 				bnx2_reuse_rx_skb_pages(bp, rxr, skb,  in bnx2_rx_skb()
3111 			dma_unmap_page(&bp->pdev->dev, mapping_old,  in bnx2_rx_skb()
3141 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_rx_int()  argument
3180 		dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,  in bnx2_rx_int()
3195 		} else if (len > bp->rx_jumbo_thresh) {  in bnx2_rx_int()
3196 			hdr_len = bp->rx_jumbo_thresh;  in bnx2_rx_int()
3206 			bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3213 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_int()
3220 		if (len <= bp->rx_copy_thresh) {  in bnx2_rx_int()
3221 			skb = netdev_alloc_skb(bp->dev, len + 6);  in bnx2_rx_int()
3223 				bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3235 			bnx2_reuse_rx_data(bp, rxr, data,  in bnx2_rx_int()
3239 			skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,  in bnx2_rx_int()
3245 		    !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))  in bnx2_rx_int()
3248 		skb->protocol = eth_type_trans(skb, bp->dev);  in bnx2_rx_int()
3250 		if (len > (bp->dev->mtu + ETH_HLEN) &&  in bnx2_rx_int()
3260 		if ((bp->dev->features & NETIF_F_RXCSUM) &&  in bnx2_rx_int()
3268 		if ((bp->dev->features & NETIF_F_RXHASH) &&  in bnx2_rx_int()
3274 		skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);  in bnx2_rx_int()
3295 		BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_rx_int()
3297 	BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);  in bnx2_rx_int()
3299 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3312 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi()  local
3315 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3320 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi()
3332 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi_1shot()  local
3337 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi_1shot()
3349 	struct bnx2 *bp = bnapi->bp;  in bnx2_interrupt()  local
3359 	    (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &  in bnx2_interrupt()
3363 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3370 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_interrupt()
3373 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_interrupt()
3420 bnx2_chk_missed_msi(struct bnx2 *bp)  in bnx2_chk_missed_msi()  argument
3422 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_chk_missed_msi()
3426 		msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);  in bnx2_chk_missed_msi()
3430 		if (bnapi->last_status_idx == bp->idle_chk_status_idx) {  in bnx2_chk_missed_msi()
3431 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3433 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3434 			bnx2_msi(bp->irq_tbl[0].vector, bnapi);  in bnx2_chk_missed_msi()
3438 	bp->idle_chk_status_idx = bnapi->last_status_idx;  in bnx2_chk_missed_msi()
3442 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_cnic()  argument
3450 	c_ops = rcu_dereference(bp->cnic_ops);  in bnx2_poll_cnic()
3452 		bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,  in bnx2_poll_cnic()
3458 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_link()  argument
3467 		bnx2_phy_int(bp, bnapi);  in bnx2_poll_link()
3472 		BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3473 			bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_poll_link()
3474 		BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_poll_link()
3478 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,  in bnx2_poll_work()  argument
3485 		bnx2_tx_int(bp, bnapi, 0);  in bnx2_poll_work()
3488 		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);  in bnx2_poll_work()
3496 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll_msix()  local
3501 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll_msix()
3511 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3523 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll()  local
3528 		bnx2_poll_link(bp, bnapi);  in bnx2_poll()
3530 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll()
3533 		bnx2_poll_cnic(bp, bnapi);  in bnx2_poll()
3548 			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {  in bnx2_poll()
3549 				BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3554 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3559 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3575 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_rx_mode()  local
3583 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3585 	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |  in bnx2_set_rx_mode()
3589 	     (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_set_rx_mode()
3599 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3622 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3637 			bnx2_set_mac_addr(bp, ha->addr,  in bnx2_set_rx_mode()
3646 	if (rx_mode != bp->rx_mode) {  in bnx2_set_rx_mode()
3647 		bp->rx_mode = rx_mode;  in bnx2_set_rx_mode()
3648 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3651 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3652 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3653 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3655 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3685 static void bnx2_release_firmware(struct bnx2 *bp)  in bnx2_release_firmware()  argument
3687 	if (bp->rv2p_firmware) {  in bnx2_release_firmware()
3688 		release_firmware(bp->mips_firmware);  in bnx2_release_firmware()
3689 		release_firmware(bp->rv2p_firmware);  in bnx2_release_firmware()
3690 		bp->rv2p_firmware = NULL;  in bnx2_release_firmware()
3694 static int bnx2_request_uncached_firmware(struct bnx2 *bp)  in bnx2_request_uncached_firmware()  argument
3701 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_request_uncached_firmware()
3703 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||  in bnx2_request_uncached_firmware()
3704 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))  in bnx2_request_uncached_firmware()
3713 	rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3719 	rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3724 	mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_request_uncached_firmware()
3725 	rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_request_uncached_firmware()
3726 	if (bp->mips_firmware->size < sizeof(*mips_fw) ||  in bnx2_request_uncached_firmware()
3727 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||  in bnx2_request_uncached_firmware()
3728 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||  in bnx2_request_uncached_firmware()
3729 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||  in bnx2_request_uncached_firmware()
3730 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||  in bnx2_request_uncached_firmware()
3731 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {  in bnx2_request_uncached_firmware()
3736 	if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||  in bnx2_request_uncached_firmware()
3737 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||  in bnx2_request_uncached_firmware()
3738 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {  in bnx2_request_uncached_firmware()
3747 	release_firmware(bp->rv2p_firmware);  in bnx2_request_uncached_firmware()
3748 	bp->rv2p_firmware = NULL;  in bnx2_request_uncached_firmware()
3750 	release_firmware(bp->mips_firmware);  in bnx2_request_uncached_firmware()
3754 static int bnx2_request_firmware(struct bnx2 *bp)  in bnx2_request_firmware()  argument
3756 	return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);  in bnx2_request_firmware()
3772 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,  in load_rv2p_fw()  argument
3783 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3794 		BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3796 		BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3800 		BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3803 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3810 			BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3813 			BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3816 			BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3822 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3825 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3832 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,  in load_cpu_fw()  argument
3841 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3843 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3844 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3850 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3857 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3864 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3871 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3878 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3885 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3889 	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);  in load_cpu_fw()
3892 	bnx2_reg_wr_ind(bp, cpu_reg->pc, val);  in load_cpu_fw()
3895 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3897 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3898 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3902 bnx2_init_cpus(struct bnx2 *bp)  in bnx2_init_cpus()  argument
3905 		(const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_init_cpus()
3907 		(const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_init_cpus()
3910 	load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);  in bnx2_init_cpus()
3911 	load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);  in bnx2_init_cpus()
3914 	load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);  in bnx2_init_cpus()
3917 	load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);  in bnx2_init_cpus()
3920 	load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);  in bnx2_init_cpus()
3923 	load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);  in bnx2_init_cpus()
3926 	load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);  in bnx2_init_cpus()
3930 bnx2_setup_wol(struct bnx2 *bp)  in bnx2_setup_wol()  argument
3935 	if (bp->wol) {  in bnx2_setup_wol()
3939 		autoneg = bp->autoneg;  in bnx2_setup_wol()
3940 		advertising = bp->advertising;  in bnx2_setup_wol()
3942 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3943 			bp->autoneg = AUTONEG_SPEED;  in bnx2_setup_wol()
3944 			bp->advertising = ADVERTISED_10baseT_Half |  in bnx2_setup_wol()
3951 		spin_lock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3952 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_setup_wol()
3953 		spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3955 		bp->autoneg = autoneg;  in bnx2_setup_wol()
3956 		bp->advertising = advertising;  in bnx2_setup_wol()
3958 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_setup_wol()
3960 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_setup_wol()
3967 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3971 			if (bp->line_speed == SPEED_2500)  in bnx2_setup_wol()
3975 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_setup_wol()
3979 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_setup_wol()
3982 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);  in bnx2_setup_wol()
3985 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_setup_wol()
3986 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_setup_wol()
3987 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);  in bnx2_setup_wol()
3990 		BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_setup_wol()
3995 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_setup_wol()
3997 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_setup_wol()
4004 	if (!(bp->flags & BNX2_FLAG_NO_WOL)) {  in bnx2_setup_wol()
4008 		if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {  in bnx2_setup_wol()
4009 			bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4015 		val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_setup_wol()
4016 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,  in bnx2_setup_wol()
4018 		bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4019 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);  in bnx2_setup_wol()
4025 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)  in bnx2_set_power_state()  argument
4031 		pci_enable_wake(bp->pdev, PCI_D0, false);  in bnx2_set_power_state()
4032 		pci_set_power_state(bp->pdev, PCI_D0);  in bnx2_set_power_state()
4034 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_power_state()
4037 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
4039 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_set_power_state()
4041 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4045 		bnx2_setup_wol(bp);  in bnx2_set_power_state()
4046 		pci_wake_from_d3(bp->pdev, bp->wol);  in bnx2_set_power_state()
4047 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_set_power_state()
4048 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {  in bnx2_set_power_state()
4050 			if (bp->wol)  in bnx2_set_power_state()
4051 				pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4055 		if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_set_power_state()
4062 			val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_set_power_state()
4065 			bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);  in bnx2_set_power_state()
4067 		pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4081 bnx2_acquire_nvram_lock(struct bnx2 *bp)  in bnx2_acquire_nvram_lock()  argument
4087 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4089 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_acquire_nvram_lock()
4103 bnx2_release_nvram_lock(struct bnx2 *bp)  in bnx2_release_nvram_lock()  argument
4109 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4112 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_release_nvram_lock()
4127 bnx2_enable_nvram_write(struct bnx2 *bp)  in bnx2_enable_nvram_write()  argument
4131 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_enable_nvram_write()
4132 	BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4134 	if (bp->flash_info->flags & BNX2_NV_WREN) {  in bnx2_enable_nvram_write()
4137 		BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4138 		BNX2_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4144 			val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_enable_nvram_write()
4156 bnx2_disable_nvram_write(struct bnx2 *bp)  in bnx2_disable_nvram_write()  argument
4160 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_disable_nvram_write()
4161 	BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4166 bnx2_enable_nvram_access(struct bnx2 *bp)  in bnx2_enable_nvram_access()  argument
4170 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_enable_nvram_access()
4172 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4177 bnx2_disable_nvram_access(struct bnx2 *bp)  in bnx2_disable_nvram_access()  argument
4181 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_disable_nvram_access()
4183 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4189 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)  in bnx2_nvram_erase_page()  argument
4194 	if (bp->flash_info->flags & BNX2_NV_BUFFERED)  in bnx2_nvram_erase_page()
4203 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4206 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4209 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4217 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_erase_page()
4229 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)  in bnx2_nvram_read_dword()  argument
4238 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_read_dword()
4239 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_read_dword()
4240 			   bp->flash_info->page_bits) +  in bnx2_nvram_read_dword()
4241 			  (offset % bp->flash_info->page_size);  in bnx2_nvram_read_dword()
4245 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4248 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4251 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4259 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_read_dword()
4261 			__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));  in bnx2_nvram_read_dword()
4274 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)  in bnx2_nvram_write_dword()  argument
4284 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_write_dword()
4285 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_write_dword()
4286 			  bp->flash_info->page_bits) +  in bnx2_nvram_write_dword()
4287 			 (offset % bp->flash_info->page_size);  in bnx2_nvram_write_dword()
4291 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4296 	BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4299 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4302 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4308 		if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)  in bnx2_nvram_write_dword()
4318 bnx2_init_nvram(struct bnx2 *bp)  in bnx2_init_nvram()  argument
4324 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_nvram()
4325 		bp->flash_info = &flash_5709;  in bnx2_init_nvram()
4330 	val = BNX2_RD(bp, BNX2_NVM_CFG1);  in bnx2_init_nvram()
4341 				bp->flash_info = flash;  in bnx2_init_nvram()
4359 				bp->flash_info = flash;  in bnx2_init_nvram()
4362 				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_init_nvram()
4366 				bnx2_enable_nvram_access(bp);  in bnx2_init_nvram()
4369 				BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4370 				BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4371 				BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4372 				BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4375 				bnx2_disable_nvram_access(bp);  in bnx2_init_nvram()
4376 				bnx2_release_nvram_lock(bp);  in bnx2_init_nvram()
4384 		bp->flash_info = NULL;  in bnx2_init_nvram()
4390 	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);  in bnx2_init_nvram()
4393 		bp->flash_size = val;  in bnx2_init_nvram()
4395 		bp->flash_size = bp->flash_info->total_size;  in bnx2_init_nvram()
4401 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,  in bnx2_nvram_read()  argument
4411 	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_read()
4415 	bnx2_enable_nvram_access(bp);  in bnx2_nvram_read()
4439 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4464 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4477 		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);  in bnx2_nvram_read()
4485 			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);  in bnx2_nvram_read()
4497 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4503 	bnx2_disable_nvram_access(bp);  in bnx2_nvram_read()
4505 	bnx2_release_nvram_lock(bp);  in bnx2_nvram_read()
4511 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,  in bnx2_nvram_write()  argument
4529 		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))  in bnx2_nvram_write()
4536 		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))  in bnx2_nvram_write()
4554 	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4570 		page_start -= (page_start % bp->flash_info->page_size);  in bnx2_nvram_write()
4572 		page_end = page_start + bp->flash_info->page_size;  in bnx2_nvram_write()
4580 		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_write()
4584 		bnx2_enable_nvram_access(bp);  in bnx2_nvram_write()
4587 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4592 			for (j = 0; j < bp->flash_info->page_size; j += 4) {  in bnx2_nvram_write()
4593 				if (j == (bp->flash_info->page_size - 4)) {  in bnx2_nvram_write()
4596 				rc = bnx2_nvram_read_dword(bp,  in bnx2_nvram_write()
4609 		if ((rc = bnx2_enable_nvram_write(bp)) != 0)  in bnx2_nvram_write()
4615 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4617 			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)  in bnx2_nvram_write()
4621 			bnx2_enable_nvram_write(bp);  in bnx2_nvram_write()
4626 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4639 				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&  in bnx2_nvram_write()
4644 			rc = bnx2_nvram_write_dword(bp, addr, buf,  in bnx2_nvram_write()
4656 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4663 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4674 		bnx2_disable_nvram_write(bp);  in bnx2_nvram_write()
4677 		bnx2_disable_nvram_access(bp);  in bnx2_nvram_write()
4678 		bnx2_release_nvram_lock(bp);  in bnx2_nvram_write()
4691 bnx2_init_fw_cap(struct bnx2 *bp)  in bnx2_init_fw_cap()  argument
4695 	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4696 	bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4698 	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))  in bnx2_init_fw_cap()
4699 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4701 	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);  in bnx2_init_fw_cap()
4706 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4710 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_init_fw_cap()
4714 		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4716 		link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_init_fw_cap()
4718 			bp->phy_port = PORT_FIBRE;  in bnx2_init_fw_cap()
4720 			bp->phy_port = PORT_TP;  in bnx2_init_fw_cap()
4726 	if (netif_running(bp->dev) && sig)  in bnx2_init_fw_cap()
4727 		bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);  in bnx2_init_fw_cap()
4731 bnx2_setup_msix_tbl(struct bnx2 *bp)  in bnx2_setup_msix_tbl()  argument
4733 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4735 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4736 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4740 bnx2_wait_dma_complete(struct bnx2 *bp)  in bnx2_wait_dma_complete()  argument
4749 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_wait_dma_complete()
4750 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_wait_dma_complete()
4751 		BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_wait_dma_complete()
4756 		val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);  in bnx2_wait_dma_complete()
4759 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_wait_dma_complete()
4761 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_wait_dma_complete()
4762 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_wait_dma_complete()
4766 			val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);  in bnx2_wait_dma_complete()
4777 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_chip()  argument
4785 	bnx2_wait_dma_complete(bp);  in bnx2_reset_chip()
4788 	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);  in bnx2_reset_chip()
4792 	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,  in bnx2_reset_chip()
4797 	val = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_reset_chip()
4799 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_reset_chip()
4800 		BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4801 		BNX2_RD(bp, BNX2_MISC_COMMAND);  in bnx2_reset_chip()
4807 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4815 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4821 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_reset_chip()
4822 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))  in bnx2_reset_chip()
4827 			val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);  in bnx2_reset_chip()
4842 	val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);  in bnx2_reset_chip()
4849 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);  in bnx2_reset_chip()
4853 	spin_lock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4854 	old_port = bp->phy_port;  in bnx2_reset_chip()
4855 	bnx2_init_fw_cap(bp);  in bnx2_reset_chip()
4856 	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&  in bnx2_reset_chip()
4857 	    old_port != bp->phy_port)  in bnx2_reset_chip()
4858 		bnx2_set_default_remote_link(bp);  in bnx2_reset_chip()
4859 	spin_unlock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4861 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_reset_chip()
4864 		BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4867 		rc = bnx2_alloc_bad_rbuf(bp);  in bnx2_reset_chip()
4870 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_reset_chip()
4871 		bnx2_setup_msix_tbl(bp);  in bnx2_reset_chip()
4873 		BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4881 bnx2_init_chip(struct bnx2 *bp)  in bnx2_init_chip()  argument
4887 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4900 	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))  in bnx2_init_chip()
4903 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&  in bnx2_init_chip()
4904 	    (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&  in bnx2_init_chip()
4905 	    !(bp->flags & BNX2_FLAG_PCIX))  in bnx2_init_chip()
4908 	BNX2_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4910 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_chip()
4911 		val = BNX2_RD(bp, BNX2_TDMA_CONFIG);  in bnx2_init_chip()
4913 		BNX2_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4916 	if (bp->flags & BNX2_FLAG_PCIX) {  in bnx2_init_chip()
4919 		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4921 		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4925 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4932 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4933 		rc = bnx2_init_5709_context(bp);  in bnx2_init_chip()
4937 		bnx2_init_context(bp);  in bnx2_init_chip()
4939 	bnx2_init_cpus(bp);  in bnx2_init_chip()
4941 	bnx2_init_nvram(bp);  in bnx2_init_chip()
4943 	bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_init_chip()
4945 	val = BNX2_RD(bp, BNX2_MQ_CONFIG);  in bnx2_init_chip()
4948 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4950 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_chip()
4954 	BNX2_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4957 	BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4958 	BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4961 	BNX2_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4964 	val = BNX2_RD(bp, BNX2_TBDR_CONFIG);  in bnx2_init_chip()
4967 	BNX2_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4969 	val = bp->mac_addr[0] +  in bnx2_init_chip()
4970 	      (bp->mac_addr[1] << 8) +  in bnx2_init_chip()
4971 	      (bp->mac_addr[2] << 16) +  in bnx2_init_chip()
4972 	      bp->mac_addr[3] +  in bnx2_init_chip()
4973 	      (bp->mac_addr[4] << 8) +  in bnx2_init_chip()
4974 	      (bp->mac_addr[5] << 16);  in bnx2_init_chip()
4975 	BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
4978 	mtu = bp->dev->mtu;  in bnx2_init_chip()
4982 	BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
4987 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));  in bnx2_init_chip()
4988 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));  in bnx2_init_chip()
4989 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));  in bnx2_init_chip()
4991 	memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);  in bnx2_init_chip()
4993 		bp->bnx2_napi[i].last_status_idx = 0;  in bnx2_init_chip()
4995 	bp->idle_chk_status_idx = 0xffff;  in bnx2_init_chip()
4998 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
5000 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
5001 		(u64) bp->status_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5002 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
5004 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
5005 		(u64) bp->stats_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5006 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
5007 		(u64) bp->stats_blk_mapping >> 32);  in bnx2_init_chip()
5009 	BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5010 		(bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);  in bnx2_init_chip()
5012 	BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5013 		(bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);  in bnx2_init_chip()
5015 	BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
5016 		(bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);  in bnx2_init_chip()
5018 	BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5020 	BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5022 	BNX2_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
5023 		(bp->com_ticks_int << 16) | bp->com_ticks);  in bnx2_init_chip()
5025 	BNX2_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
5026 		(bp->cmd_ticks_int << 16) | bp->cmd_ticks);  in bnx2_init_chip()
5028 	if (bp->flags & BNX2_FLAG_BROKEN_STATS)  in bnx2_init_chip()
5029 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
5031 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
5032 	BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
5034 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)  in bnx2_init_chip()
5041 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_init_chip()
5042 		BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
5048 	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)  in bnx2_init_chip()
5051 	BNX2_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5053 	if (bp->rx_ticks < 25)  in bnx2_init_chip()
5054 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);  in bnx2_init_chip()
5056 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);  in bnx2_init_chip()
5058 	for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_init_chip()
5062 		BNX2_WR(bp, base,  in bnx2_init_chip()
5067 		BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5068 			(bp->tx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5069 			 bp->tx_quick_cons_trip);  in bnx2_init_chip()
5071 		BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5072 			(bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5074 		BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5075 			(bp->rx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5076 			bp->rx_quick_cons_trip);  in bnx2_init_chip()
5078 		BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5079 			(bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5083 	BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5085 	BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5088 	bnx2_set_rx_mode(bp->dev);  in bnx2_init_chip()
5090 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
5091 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_init_chip()
5093 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5095 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,  in bnx2_init_chip()
5098 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5099 	BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);  in bnx2_init_chip()
5103 	bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_init_chip()
5109 bnx2_clear_ring_states(struct bnx2 *bp)  in bnx2_clear_ring_states()  argument
5117 		bnapi = &bp->bnx2_napi[i];  in bnx2_clear_ring_states()
5132 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)  in bnx2_init_tx_context()  argument
5137 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_tx_context()
5149 	bnx2_ctx_wr(bp, cid_addr, offset0, val);  in bnx2_init_tx_context()
5152 	bnx2_ctx_wr(bp, cid_addr, offset1, val);  in bnx2_init_tx_context()
5155 	bnx2_ctx_wr(bp, cid_addr, offset2, val);  in bnx2_init_tx_context()
5158 	bnx2_ctx_wr(bp, cid_addr, offset3, val);  in bnx2_init_tx_context()
5162 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_tx_ring()  argument
5169 	bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_tx_ring()
5177 	bp->tx_wake_thresh = bp->tx_ring_size / 2;  in bnx2_init_tx_ring()
5190 	bnx2_init_tx_context(bp, cid, txr);  in bnx2_init_tx_ring()
5218 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_rx_ring()  argument
5223 	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_rx_ring()
5234 			     bp->rx_buf_use_size, bp->rx_max_ring);  in bnx2_init_rx_ring()
5236 	bnx2_init_rx_context(bp, cid);  in bnx2_init_rx_ring()
5238 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_rx_ring()
5239 		val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);  in bnx2_init_rx_ring()
5240 		BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5243 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);  in bnx2_init_rx_ring()
5244 	if (bp->rx_pg_ring_size) {  in bnx2_init_rx_ring()
5247 				     PAGE_SIZE, bp->rx_max_pg_ring);  in bnx2_init_rx_ring()
5248 		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;  in bnx2_init_rx_ring()
5249 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);  in bnx2_init_rx_ring()
5250 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,  in bnx2_init_rx_ring()
5254 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5257 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5259 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_rx_ring()
5260 			BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5264 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5267 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5270 	for (i = 0; i < bp->rx_pg_ring_size; i++) {  in bnx2_init_rx_ring()
5271 		if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5272 			netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",  in bnx2_init_rx_ring()
5273 				    ring_num, i, bp->rx_pg_ring_size);  in bnx2_init_rx_ring()
5282 	for (i = 0; i < bp->rx_ring_size; i++) {  in bnx2_init_rx_ring()
5283 		if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5284 			netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",  in bnx2_init_rx_ring()
5285 				    ring_num, i, bp->rx_ring_size);  in bnx2_init_rx_ring()
5297 	BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_init_rx_ring()
5298 	BNX2_WR16(bp, rxr->rx_bidx_addr, prod);  in bnx2_init_rx_ring()
5300 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5304 bnx2_init_all_rings(struct bnx2 *bp)  in bnx2_init_all_rings()  argument
5309 	bnx2_clear_ring_states(bp);  in bnx2_init_all_rings()
5311 	BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5312 	for (i = 0; i < bp->num_tx_rings; i++)  in bnx2_init_all_rings()
5313 		bnx2_init_tx_ring(bp, i);  in bnx2_init_all_rings()
5315 	if (bp->num_tx_rings > 1)  in bnx2_init_all_rings()
5316 		BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5319 	BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5320 	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);  in bnx2_init_all_rings()
5322 	for (i = 0; i < bp->num_rx_rings; i++)  in bnx2_init_all_rings()
5323 		bnx2_init_rx_ring(bp, i);  in bnx2_init_all_rings()
5325 	if (bp->num_rx_rings > 1) {  in bnx2_init_all_rings()
5331 			tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;  in bnx2_init_all_rings()
5333 				BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5334 				BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5345 		BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5370 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)  in bnx2_set_rx_ring_size()  argument
5375 	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;  in bnx2_set_rx_ring_size()
5380 	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;  in bnx2_set_rx_ring_size()
5381 	bp->rx_pg_ring_size = 0;  in bnx2_set_rx_ring_size()
5382 	bp->rx_max_pg_ring = 0;  in bnx2_set_rx_ring_size()
5383 	bp->rx_max_pg_ring_idx = 0;  in bnx2_set_rx_ring_size()
5384 	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {  in bnx2_set_rx_ring_size()
5385 		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;  in bnx2_set_rx_ring_size()
5391 		bp->rx_pg_ring_size = jumbo_size;  in bnx2_set_rx_ring_size()
5392 		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,  in bnx2_set_rx_ring_size()
5394 		bp->rx_max_pg_ring_idx =  in bnx2_set_rx_ring_size()
5395 			(bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5397 		bp->rx_copy_thresh = 0;  in bnx2_set_rx_ring_size()
5400 	bp->rx_buf_use_size = rx_size;  in bnx2_set_rx_ring_size()
5402 	bp->rx_buf_size = kmalloc_size_roundup(  in bnx2_set_rx_ring_size()
5403 		SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +  in bnx2_set_rx_ring_size()
5405 	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;  in bnx2_set_rx_ring_size()
5406 	bp->rx_ring_size = size;  in bnx2_set_rx_ring_size()
5407 	bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);  in bnx2_set_rx_ring_size()
5408 	bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5412 bnx2_free_tx_skbs(struct bnx2 *bp)  in bnx2_free_tx_skbs()  argument
5416 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_skbs()
5417 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_skbs()
5434 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5445 				dma_unmap_page(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5452 		netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));  in bnx2_free_tx_skbs()
5457 bnx2_free_rx_skbs(struct bnx2 *bp)  in bnx2_free_rx_skbs()  argument
5461 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_skbs()
5462 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_skbs()
5469 		for (j = 0; j < bp->rx_max_ring_idx; j++) {  in bnx2_free_rx_skbs()
5476 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_rx_skbs()
5478 					 bp->rx_buf_use_size,  in bnx2_free_rx_skbs()
5485 		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)  in bnx2_free_rx_skbs()
5486 			bnx2_free_rx_page(bp, rxr, j);  in bnx2_free_rx_skbs()
5491 bnx2_free_skbs(struct bnx2 *bp)  in bnx2_free_skbs()  argument
5493 	bnx2_free_tx_skbs(bp);  in bnx2_free_skbs()
5494 	bnx2_free_rx_skbs(bp);  in bnx2_free_skbs()
5498 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_nic()  argument
5502 	rc = bnx2_reset_chip(bp, reset_code);  in bnx2_reset_nic()
5503 	bnx2_free_skbs(bp);  in bnx2_reset_nic()
5507 	if ((rc = bnx2_init_chip(bp)) != 0)  in bnx2_reset_nic()
5510 	bnx2_init_all_rings(bp);  in bnx2_reset_nic()
5515 bnx2_init_nic(struct bnx2 *bp, int reset_phy)  in bnx2_init_nic()  argument
5519 	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)  in bnx2_init_nic()
5522 	spin_lock_bh(&bp->phy_lock);  in bnx2_init_nic()
5523 	bnx2_init_phy(bp, reset_phy);  in bnx2_init_nic()
5524 	bnx2_set_link(bp);  in bnx2_init_nic()
5525 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_nic()
5526 		bnx2_remote_phy_event(bp);  in bnx2_init_nic()
5527 	spin_unlock_bh(&bp->phy_lock);  in bnx2_init_nic()
5532 bnx2_shutdown_chip(struct bnx2 *bp)  in bnx2_shutdown_chip()  argument
5536 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_shutdown_chip()
5538 	else if (bp->wol)  in bnx2_shutdown_chip()
5543 	return bnx2_reset_chip(bp, reset_code);  in bnx2_shutdown_chip()
5547 bnx2_test_registers(struct bnx2 *bp)  in bnx2_test_registers()  argument
5668 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_registers()
5682 		save_val = readl(bp->regview + offset);  in bnx2_test_registers()
5684 		writel(0, bp->regview + offset);  in bnx2_test_registers()
5686 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5695 		writel(0xffffffff, bp->regview + offset);  in bnx2_test_registers()
5697 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5706 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5710 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5718 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)  in bnx2_do_mem_test()  argument
5729 			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);  in bnx2_do_mem_test()
5731 			if (bnx2_reg_rd_ind(bp, start + offset) !=  in bnx2_do_mem_test()
5741 bnx2_test_memory(struct bnx2 *bp)  in bnx2_test_memory()  argument
5767 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_memory()
5773 		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,  in bnx2_test_memory()
5786 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)  in bnx2_run_loopback()  argument
5798 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;  in bnx2_run_loopback()
5807 		bp->loopback = MAC_LOOPBACK;  in bnx2_run_loopback()
5808 		bnx2_set_mac_loopback(bp);  in bnx2_run_loopback()
5811 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_run_loopback()
5814 		bp->loopback = PHY_LOOPBACK;  in bnx2_run_loopback()
5815 		bnx2_set_phy_loopback(bp);  in bnx2_run_loopback()
5820 	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);  in bnx2_run_loopback()
5821 	skb = netdev_alloc_skb(bp->dev, pkt_size);  in bnx2_run_loopback()
5825 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);  in bnx2_run_loopback()
5830 	map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,  in bnx2_run_loopback()
5832 	if (dma_mapping_error(&bp->pdev->dev, map)) {  in bnx2_run_loopback()
5837 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5838 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5840 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5858 	BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);  in bnx2_run_loopback()
5859 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5863 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5864 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5866 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5870 	dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);  in bnx2_run_loopback()
5887 	dma_sync_single_for_cpu(&bp->pdev->dev,  in bnx2_run_loopback()
5889 		bp->rx_buf_use_size, DMA_FROM_DEVICE);  in bnx2_run_loopback()
5914 	bp->loopback = 0;  in bnx2_run_loopback()
5924 bnx2_test_loopback(struct bnx2 *bp)  in bnx2_test_loopback()  argument
5928 	if (!netif_running(bp->dev))  in bnx2_test_loopback()
5931 	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_test_loopback()
5932 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5933 	bnx2_init_phy(bp, 1);  in bnx2_test_loopback()
5934 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5935 	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))  in bnx2_test_loopback()
5937 	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))  in bnx2_test_loopback()
5946 bnx2_test_nvram(struct bnx2 *bp)  in bnx2_test_nvram()  argument
5953 	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)  in bnx2_test_nvram()
5962 	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)  in bnx2_test_nvram()
5981 bnx2_test_link(struct bnx2 *bp)  in bnx2_test_link()  argument
5985 	if (!netif_running(bp->dev))  in bnx2_test_link()
5988 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_test_link()
5989 		if (bp->link_up)  in bnx2_test_link()
5993 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_link()
5994 	bnx2_enable_bmsr1(bp);  in bnx2_test_link()
5995 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
5996 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
5997 	bnx2_disable_bmsr1(bp);  in bnx2_test_link()
5998 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_link()
6007 bnx2_test_intr(struct bnx2 *bp)  in bnx2_test_intr()  argument
6012 	if (!netif_running(bp->dev))  in bnx2_test_intr()
6015 	status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;  in bnx2_test_intr()
6018 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6019 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_test_intr()
6022 		if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=  in bnx2_test_intr()
6038 bnx2_5706_serdes_has_link(struct bnx2 *bp)  in bnx2_5706_serdes_has_link()  argument
6042 	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)  in bnx2_5706_serdes_has_link()
6045 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);  in bnx2_5706_serdes_has_link()
6046 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);  in bnx2_5706_serdes_has_link()
6051 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_has_link()
6052 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6053 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6058 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);  in bnx2_5706_serdes_has_link()
6059 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6060 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6069 bnx2_5706_serdes_timer(struct bnx2 *bp)  in bnx2_5706_serdes_timer()  argument
6073 	spin_lock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6074 	if (bp->serdes_an_pending) {  in bnx2_5706_serdes_timer()
6075 		bp->serdes_an_pending--;  in bnx2_5706_serdes_timer()
6077 	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5706_serdes_timer()
6080 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6082 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6085 			if (bnx2_5706_serdes_has_link(bp)) {  in bnx2_5706_serdes_timer()
6088 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6089 				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6093 	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&  in bnx2_5706_serdes_timer()
6094 		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {  in bnx2_5706_serdes_timer()
6097 		bnx2_write_phy(bp, 0x17, 0x0f01);  in bnx2_5706_serdes_timer()
6098 		bnx2_read_phy(bp, 0x15, &phy2);  in bnx2_5706_serdes_timer()
6102 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6104 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6106 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6109 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6114 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_timer()
6115 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6116 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6118 		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {  in bnx2_5706_serdes_timer()
6119 			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {  in bnx2_5706_serdes_timer()
6120 				bnx2_5706s_force_link_dn(bp, 1);  in bnx2_5706_serdes_timer()
6121 				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_5706_serdes_timer()
6123 				bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6124 		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))  in bnx2_5706_serdes_timer()
6125 			bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6127 	spin_unlock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6131 bnx2_5708_serdes_timer(struct bnx2 *bp)  in bnx2_5708_serdes_timer()  argument
6133 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_5708_serdes_timer()
6136 	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {  in bnx2_5708_serdes_timer()
6137 		bp->serdes_an_pending = 0;  in bnx2_5708_serdes_timer()
6141 	spin_lock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6142 	if (bp->serdes_an_pending)  in bnx2_5708_serdes_timer()
6143 		bp->serdes_an_pending--;  in bnx2_5708_serdes_timer()
6144 	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5708_serdes_timer()
6147 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5708_serdes_timer()
6149 			bnx2_enable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6150 			bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;  in bnx2_5708_serdes_timer()
6152 			bnx2_disable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6153 			bp->serdes_an_pending = 2;  in bnx2_5708_serdes_timer()
6154 			bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6158 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6160 	spin_unlock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6166 	struct bnx2 *bp = from_timer(bp, t, timer);  in bnx2_timer()  local
6168 	if (!netif_running(bp->dev))  in bnx2_timer()
6171 	if (atomic_read(&bp->intr_sem) != 0)  in bnx2_timer()
6174 	if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==  in bnx2_timer()
6176 		bnx2_chk_missed_msi(bp);  in bnx2_timer()
6178 	bnx2_send_heart_beat(bp);  in bnx2_timer()
6180 	bp->stats_blk->stat_FwRxDrop =  in bnx2_timer()
6181 		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);  in bnx2_timer()
6184 	if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)  in bnx2_timer()
6185 		BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6188 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_timer()
6189 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_timer()
6190 			bnx2_5706_serdes_timer(bp);  in bnx2_timer()
6192 			bnx2_5708_serdes_timer(bp);  in bnx2_timer()
6196 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_timer()
6200 bnx2_request_irq(struct bnx2 *bp)  in bnx2_request_irq()  argument
6206 	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)  in bnx2_request_irq()
6211 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_request_irq()
6212 		irq = &bp->irq_tbl[i];  in bnx2_request_irq()
6214 				 &bp->bnx2_napi[i]);  in bnx2_request_irq()
6223 __bnx2_free_irq(struct bnx2 *bp)  in __bnx2_free_irq()  argument
6228 	for (i = 0; i < bp->irq_nvecs; i++) {  in __bnx2_free_irq()
6229 		irq = &bp->irq_tbl[i];  in __bnx2_free_irq()
6231 			free_irq(irq->vector, &bp->bnx2_napi[i]);  in __bnx2_free_irq()
6237 bnx2_free_irq(struct bnx2 *bp)  in bnx2_free_irq()  argument
6240 	__bnx2_free_irq(bp);  in bnx2_free_irq()
6241 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_free_irq()
6242 		pci_disable_msi(bp->pdev);  in bnx2_free_irq()
6243 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_free_irq()
6244 		pci_disable_msix(bp->pdev);  in bnx2_free_irq()
6246 	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);  in bnx2_free_irq()
6250 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)  in bnx2_enable_msix()  argument
6254 	struct net_device *dev = bp->dev;  in bnx2_enable_msix()
6255 	const int len = sizeof(bp->irq_tbl[0].name);  in bnx2_enable_msix()
6257 	bnx2_setup_msix_tbl(bp);  in bnx2_enable_msix()
6258 	BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6259 	BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6260 	BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6264 	BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);  in bnx2_enable_msix()
6275 	total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,  in bnx2_enable_msix()
6284 	bp->irq_nvecs = msix_vecs;  in bnx2_enable_msix()
6285 	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_enable_msix()
6287 		bp->irq_tbl[i].vector = msix_ent[i].vector;  in bnx2_enable_msix()
6288 		snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);  in bnx2_enable_msix()
6289 		bp->irq_tbl[i].handler = bnx2_msi_1shot;  in bnx2_enable_msix()
6294 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)  in bnx2_setup_int_mode()  argument
6299 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6300 		msix_vecs = max(cpus + 1, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6301 	else if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6302 		msix_vecs = max(cpus, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6304 		msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6308 	bp->irq_tbl[0].handler = bnx2_interrupt;  in bnx2_setup_int_mode()
6309 	strcpy(bp->irq_tbl[0].name, bp->dev->name);  in bnx2_setup_int_mode()
6310 	bp->irq_nvecs = 1;  in bnx2_setup_int_mode()
6311 	bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6313 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)  in bnx2_setup_int_mode()
6314 		bnx2_enable_msix(bp, msix_vecs);  in bnx2_setup_int_mode()
6316 	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&  in bnx2_setup_int_mode()
6317 	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_setup_int_mode()
6318 		if (pci_enable_msi(bp->pdev) == 0) {  in bnx2_setup_int_mode()
6319 			bp->flags |= BNX2_FLAG_USING_MSI;  in bnx2_setup_int_mode()
6320 			if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_int_mode()
6321 				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_setup_int_mode()
6322 				bp->irq_tbl[0].handler = bnx2_msi_1shot;  in bnx2_setup_int_mode()
6324 				bp->irq_tbl[0].handler = bnx2_msi;  in bnx2_setup_int_mode()
6326 			bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6330 	if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6331 		bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);  in bnx2_setup_int_mode()
6333 		bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6335 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6336 		bp->num_rx_rings = bp->irq_nvecs;  in bnx2_setup_int_mode()
6338 		bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6340 	netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);  in bnx2_setup_int_mode()
6342 	return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);  in bnx2_setup_int_mode()
6349 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_open()  local
6352 	rc = bnx2_request_firmware(bp);  in bnx2_open()
6358 	bnx2_disable_int(bp);  in bnx2_open()
6360 	rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_open()
6363 	bnx2_init_napi(bp);  in bnx2_open()
6364 	bnx2_napi_enable(bp);  in bnx2_open()
6365 	rc = bnx2_alloc_mem(bp);  in bnx2_open()
6369 	rc = bnx2_request_irq(bp);  in bnx2_open()
6373 	rc = bnx2_init_nic(bp, 1);  in bnx2_open()
6377 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_open()
6379 	atomic_set(&bp->intr_sem, 0);  in bnx2_open()
6381 	memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));  in bnx2_open()
6383 	bnx2_enable_int(bp);  in bnx2_open()
6385 	if (bp->flags & BNX2_FLAG_USING_MSI) {  in bnx2_open()
6389 		if (bnx2_test_intr(bp) != 0) {  in bnx2_open()
6390 …netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report …  in bnx2_open()
6392 			bnx2_disable_int(bp);  in bnx2_open()
6393 			bnx2_free_irq(bp);  in bnx2_open()
6395 			bnx2_setup_int_mode(bp, 1);  in bnx2_open()
6397 			rc = bnx2_init_nic(bp, 0);  in bnx2_open()
6400 				rc = bnx2_request_irq(bp);  in bnx2_open()
6403 				del_timer_sync(&bp->timer);  in bnx2_open()
6406 			bnx2_enable_int(bp);  in bnx2_open()
6409 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_open()
6411 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_open()
6419 	bnx2_napi_disable(bp);  in bnx2_open()
6420 	bnx2_free_skbs(bp);  in bnx2_open()
6421 	bnx2_free_irq(bp);  in bnx2_open()
6422 	bnx2_free_mem(bp);  in bnx2_open()
6423 	bnx2_del_napi(bp);  in bnx2_open()
6424 	bnx2_release_firmware(bp);  in bnx2_open()
6431 	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);  in bnx2_reset_task()  local
6436 	if (!netif_running(bp->dev)) {  in bnx2_reset_task()
6441 	bnx2_netif_stop(bp, true);  in bnx2_reset_task()
6443 	pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);  in bnx2_reset_task()
6446 		pci_restore_state(bp->pdev);  in bnx2_reset_task()
6447 		pci_save_state(bp->pdev);  in bnx2_reset_task()
6449 	rc = bnx2_init_nic(bp, 1);  in bnx2_reset_task()
6451 		netdev_err(bp->dev, "failed to reset NIC, closing\n");  in bnx2_reset_task()
6452 		bnx2_napi_enable(bp);  in bnx2_reset_task()
6453 		dev_close(bp->dev);  in bnx2_reset_task()
6458 	atomic_set(&bp->intr_sem, 1);  in bnx2_reset_task()
6459 	bnx2_netif_start(bp, true);  in bnx2_reset_task()
6466 bnx2_dump_ftq(struct bnx2 *bp)  in bnx2_dump_ftq()  argument
6470 	struct net_device *dev = bp->dev;  in bnx2_dump_ftq()
6494 			   bnx2_reg_rd_ind(bp, ftq_arr[i].off));  in bnx2_dump_ftq()
6499 			   reg, bnx2_reg_rd_ind(bp, reg),  in bnx2_dump_ftq()
6500 			   bnx2_reg_rd_ind(bp, reg + 4),  in bnx2_dump_ftq()
6501 			   bnx2_reg_rd_ind(bp, reg + 8),  in bnx2_dump_ftq()
6502 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6503 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6504 			   bnx2_reg_rd_ind(bp, reg + 0x20));  in bnx2_dump_ftq()
6509 		   BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);  in bnx2_dump_ftq()
6514 		BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);  in bnx2_dump_ftq()
6515 		BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,  in bnx2_dump_ftq()
6517 		BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);  in bnx2_dump_ftq()
6518 		while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &  in bnx2_dump_ftq()
6522 		cid = BNX2_RD(bp, BNX2_TBDC_CID);  in bnx2_dump_ftq()
6523 		bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);  in bnx2_dump_ftq()
6524 		valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);  in bnx2_dump_ftq()
6533 bnx2_dump_state(struct bnx2 *bp)  in bnx2_dump_state()  argument
6535 	struct net_device *dev = bp->dev;  in bnx2_dump_state()
6538 	pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);  in bnx2_dump_state()
6540 		   atomic_read(&bp->intr_sem), val1);  in bnx2_dump_state()
6541 	pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);  in bnx2_dump_state()
6542 	pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);  in bnx2_dump_state()
6545 		   BNX2_RD(bp, BNX2_EMAC_TX_STATUS),  in bnx2_dump_state()
6546 		   BNX2_RD(bp, BNX2_EMAC_RX_STATUS));  in bnx2_dump_state()
6548 		   BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));  in bnx2_dump_state()
6550 		   BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));  in bnx2_dump_state()
6551 	if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_dump_state()
6553 			   BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));  in bnx2_dump_state()
6559 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_tx_timeout()  local
6561 	bnx2_dump_ftq(bp);  in bnx2_tx_timeout()
6562 	bnx2_dump_state(bp);  in bnx2_tx_timeout()
6563 	bnx2_dump_mcp_state(bp);  in bnx2_tx_timeout()
6566 	schedule_work(&bp->reset_task);  in bnx2_tx_timeout()
6576 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_start_xmit()  local
6589 	bnapi = &bp->bnx2_napi[i];  in bnx2_start_xmit()
6593 	if (unlikely(bnx2_tx_avail(bp, txr) <  in bnx2_start_xmit()
6648 	mapping = dma_map_single(&bp->pdev->dev, skb->data, len,  in bnx2_start_xmit()
6650 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_start_xmit()
6678 		mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,  in bnx2_start_xmit()
6680 		if (dma_mapping_error(&bp->pdev->dev, mapping))  in bnx2_start_xmit()
6701 	BNX2_WR16(bp, txr->tx_bidx_addr, prod);  in bnx2_start_xmit()
6702 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
6706 	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {  in bnx2_start_xmit()
6715 		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)  in bnx2_start_xmit()
6729 	dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6737 		dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6750 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_close()  local
6752 	bnx2_disable_int_sync(bp);  in bnx2_close()
6753 	bnx2_napi_disable(bp);  in bnx2_close()
6755 	del_timer_sync(&bp->timer);  in bnx2_close()
6756 	bnx2_shutdown_chip(bp);  in bnx2_close()
6757 	bnx2_free_irq(bp);  in bnx2_close()
6758 	bnx2_free_skbs(bp);  in bnx2_close()
6759 	bnx2_free_mem(bp);  in bnx2_close()
6760 	bnx2_del_napi(bp);  in bnx2_close()
6761 	bp->link_up = 0;  in bnx2_close()
6762 	netif_carrier_off(bp->dev);  in bnx2_close()
6767 bnx2_save_stats(struct bnx2 *bp)  in bnx2_save_stats()  argument
6769 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_save_stats()
6770 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_save_stats()
6794 	GET_64BIT_NET_STATS64(bp->stats_blk->ctr) +		\
6795 	GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6798 	(unsigned long) (bp->stats_blk->ctr +			\
6799 			 bp->temp_stats_blk->ctr)
6804 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_stats64()  local
6806 	if (!bp->stats_blk)  in bnx2_get_stats64()
6853 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_get_stats64()
6854 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_stats64()
6879 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link_ksettings()  local
6884 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_get_link_ksettings()
6887 	} else if (bp->phy_port == PORT_FIBRE)  in bnx2_get_link_ksettings()
6895 		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_get_link_ksettings()
6907 	spin_lock_bh(&bp->phy_lock);  in bnx2_get_link_ksettings()
6908 	cmd->base.port = bp->phy_port;  in bnx2_get_link_ksettings()
6909 	advertising = bp->advertising;  in bnx2_get_link_ksettings()
6911 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_get_link_ksettings()
6918 		cmd->base.speed = bp->line_speed;  in bnx2_get_link_ksettings()
6919 		cmd->base.duplex = bp->duplex;  in bnx2_get_link_ksettings()
6920 		if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {  in bnx2_get_link_ksettings()
6921 			if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)  in bnx2_get_link_ksettings()
6931 	spin_unlock_bh(&bp->phy_lock);  in bnx2_get_link_ksettings()
6933 	cmd->base.phy_address = bp->phy_addr;  in bnx2_get_link_ksettings()
6947 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_link_ksettings()  local
6948 	u8 autoneg = bp->autoneg;  in bnx2_set_link_ksettings()
6949 	u8 req_duplex = bp->req_duplex;  in bnx2_set_link_ksettings()
6950 	u16 req_line_speed = bp->req_line_speed;  in bnx2_set_link_ksettings()
6951 	u32 advertising = bp->advertising;  in bnx2_set_link_ksettings()
6954 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_link_ksettings()
6959 	if (cmd->base.port != bp->phy_port &&  in bnx2_set_link_ksettings()
6960 	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))  in bnx2_set_link_ksettings()
6966 	if (!netif_running(dev) && cmd->base.port != bp->phy_port)  in bnx2_set_link_ksettings()
6996 			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_set_link_ksettings()
7007 	bp->autoneg = autoneg;  in bnx2_set_link_ksettings()
7008 	bp->advertising = advertising;  in bnx2_set_link_ksettings()
7009 	bp->req_line_speed = req_line_speed;  in bnx2_set_link_ksettings()
7010 	bp->req_duplex = req_duplex;  in bnx2_set_link_ksettings()
7017 		err = bnx2_setup_phy(bp, cmd->base.port);  in bnx2_set_link_ksettings()
7020 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_link_ksettings()
7028 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_drvinfo()  local
7031 	strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));  in bnx2_get_drvinfo()
7032 	strscpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));  in bnx2_get_drvinfo()
7048 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_regs()  local
7078 	if (!netif_running(bp->dev))  in bnx2_get_regs()
7085 		*p++ = BNX2_RD(bp, offset);  in bnx2_get_regs()
7098 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_wol()  local
7100 	if (bp->flags & BNX2_FLAG_NO_WOL) {  in bnx2_get_wol()
7106 		if (bp->wol)  in bnx2_get_wol()
7117 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_wol()  local
7123 		if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_set_wol()
7126 		bp->wol = 1;  in bnx2_set_wol()
7129 		bp->wol = 0;  in bnx2_set_wol()
7132 	device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_set_wol()
7140 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_nway_reset()  local
7146 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_nway_reset()
7150 	spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7152 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_nway_reset()
7155 		rc = bnx2_setup_remote_phy(bp, bp->phy_port);  in bnx2_nway_reset()
7156 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7161 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_nway_reset()
7162 		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_nway_reset()
7163 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7167 		spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7169 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_nway_reset()
7170 		bp->serdes_an_pending = 1;  in bnx2_nway_reset()
7171 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_nway_reset()
7174 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_nway_reset()
7176 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);  in bnx2_nway_reset()
7178 	spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7186 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link()  local
7188 	return bp->link_up;  in bnx2_get_link()
7194 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom_len()  local
7196 	if (!bp->flash_info)  in bnx2_get_eeprom_len()
7199 	return (int) bp->flash_size;  in bnx2_get_eeprom_len()
7206 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom()  local
7211 	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_get_eeprom()
7220 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_eeprom()  local
7225 	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_set_eeprom()
7235 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_coalesce()  local
7239 	coal->rx_coalesce_usecs = bp->rx_ticks;  in bnx2_get_coalesce()
7240 	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;  in bnx2_get_coalesce()
7241 	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;  in bnx2_get_coalesce()
7242 	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;  in bnx2_get_coalesce()
7244 	coal->tx_coalesce_usecs = bp->tx_ticks;  in bnx2_get_coalesce()
7245 	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;  in bnx2_get_coalesce()
7246 	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;  in bnx2_get_coalesce()
7247 	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;  in bnx2_get_coalesce()
7249 	coal->stats_block_coalesce_usecs = bp->stats_ticks;  in bnx2_get_coalesce()
7259 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_coalesce()  local
7261 	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;  in bnx2_set_coalesce()
7262 	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;  in bnx2_set_coalesce()
7264 	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;  in bnx2_set_coalesce()
7265 	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7267 	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7268 	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7270 	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7271 	if (bp->rx_quick_cons_trip_int > 0xff)  in bnx2_set_coalesce()
7272 		bp->rx_quick_cons_trip_int = 0xff;  in bnx2_set_coalesce()
7274 	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;  in bnx2_set_coalesce()
7275 	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;  in bnx2_set_coalesce()
7277 	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;  in bnx2_set_coalesce()
7278 	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7280 	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7281 	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7283 	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7284 	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =  in bnx2_set_coalesce()
7287 	bp->stats_ticks = coal->stats_block_coalesce_usecs;  in bnx2_set_coalesce()
7288 	if (bp->flags & BNX2_FLAG_BROKEN_STATS) {  in bnx2_set_coalesce()
7289 		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)  in bnx2_set_coalesce()
7290 			bp->stats_ticks = USEC_PER_SEC;  in bnx2_set_coalesce()
7292 	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)  in bnx2_set_coalesce()
7293 		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7294 	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7296 	if (netif_running(bp->dev)) {  in bnx2_set_coalesce()
7297 		bnx2_netif_stop(bp, true);  in bnx2_set_coalesce()
7298 		bnx2_init_nic(bp, 0);  in bnx2_set_coalesce()
7299 		bnx2_netif_start(bp, true);  in bnx2_set_coalesce()
7310 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ringparam()  local
7315 	ering->rx_pending = bp->rx_ring_size;  in bnx2_get_ringparam()
7316 	ering->rx_jumbo_pending = bp->rx_pg_ring_size;  in bnx2_get_ringparam()
7319 	ering->tx_pending = bp->tx_ring_size;  in bnx2_get_ringparam()
7323 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)  in bnx2_change_ring_size()  argument
7325 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7327 		bnx2_save_stats(bp);  in bnx2_change_ring_size()
7329 		bnx2_netif_stop(bp, true);  in bnx2_change_ring_size()
7330 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_change_ring_size()
7332 			bnx2_free_irq(bp);  in bnx2_change_ring_size()
7333 			bnx2_del_napi(bp);  in bnx2_change_ring_size()
7335 			__bnx2_free_irq(bp);  in bnx2_change_ring_size()
7337 		bnx2_free_skbs(bp);  in bnx2_change_ring_size()
7338 		bnx2_free_mem(bp);  in bnx2_change_ring_size()
7341 	bnx2_set_rx_ring_size(bp, rx);  in bnx2_change_ring_size()
7342 	bp->tx_ring_size = tx;  in bnx2_change_ring_size()
7344 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7348 			rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_change_ring_size()
7349 			bnx2_init_napi(bp);  in bnx2_change_ring_size()
7353 			rc = bnx2_alloc_mem(bp);  in bnx2_change_ring_size()
7356 			rc = bnx2_request_irq(bp);  in bnx2_change_ring_size()
7359 			rc = bnx2_init_nic(bp, 0);  in bnx2_change_ring_size()
7362 			bnx2_napi_enable(bp);  in bnx2_change_ring_size()
7363 			dev_close(bp->dev);  in bnx2_change_ring_size()
7367 		mutex_lock(&bp->cnic_lock);  in bnx2_change_ring_size()
7369 		if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)  in bnx2_change_ring_size()
7370 			bnx2_setup_cnic_irq_info(bp);  in bnx2_change_ring_size()
7371 		mutex_unlock(&bp->cnic_lock);  in bnx2_change_ring_size()
7373 		bnx2_netif_start(bp, true);  in bnx2_change_ring_size()
7383 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_ringparam()  local
7392 	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,  in bnx2_set_ringparam()
7400 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_pauseparam()  local
7402 	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);  in bnx2_get_pauseparam()
7403 	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);  in bnx2_get_pauseparam()
7404 	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);  in bnx2_get_pauseparam()
7410 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_pauseparam()  local
7412 	bp->req_flow_ctrl = 0;  in bnx2_set_pauseparam()
7414 		bp->req_flow_ctrl |= FLOW_CTRL_RX;  in bnx2_set_pauseparam()
7416 		bp->req_flow_ctrl |= FLOW_CTRL_TX;  in bnx2_set_pauseparam()
7419 		bp->autoneg |= AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7422 		bp->autoneg &= ~AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7426 		spin_lock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7427 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_set_pauseparam()
7428 		spin_unlock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7588 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_self_test()  local
7594 		bnx2_netif_stop(bp, true);  in bnx2_self_test()
7595 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);  in bnx2_self_test()
7596 		bnx2_free_skbs(bp);  in bnx2_self_test()
7598 		if (bnx2_test_registers(bp) != 0) {  in bnx2_self_test()
7602 		if (bnx2_test_memory(bp) != 0) {  in bnx2_self_test()
7606 		if ((buf[2] = bnx2_test_loopback(bp)) != 0)  in bnx2_self_test()
7609 		if (!netif_running(bp->dev))  in bnx2_self_test()
7610 			bnx2_shutdown_chip(bp);  in bnx2_self_test()
7612 			bnx2_init_nic(bp, 1);  in bnx2_self_test()
7613 			bnx2_netif_start(bp, true);  in bnx2_self_test()
7618 			if (bp->link_up)  in bnx2_self_test()
7624 	if (bnx2_test_nvram(bp) != 0) {  in bnx2_self_test()
7628 	if (bnx2_test_intr(bp) != 0) {  in bnx2_self_test()
7633 	if (bnx2_test_link(bp) != 0) {  in bnx2_self_test()
7659 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ethtool_stats()  local
7661 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_get_ethtool_stats()
7662 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_get_ethtool_stats()
7670 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_get_ethtool_stats()
7671 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||  in bnx2_get_ethtool_stats()
7672 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||  in bnx2_get_ethtool_stats()
7673 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_ethtool_stats()
7705 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_phys_id()  local
7709 		bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_set_phys_id()
7710 		BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7714 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7723 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7727 		BNX2_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7728 		BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
7738 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_features()  local
7747 	    !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&  in bnx2_set_features()
7749 		bnx2_netif_stop(bp, false);  in bnx2_set_features()
7752 		bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);  in bnx2_set_features()
7753 		bnx2_netif_start(bp, false);  in bnx2_set_features()
7763 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_channels()  local
7767 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_get_channels()
7776 	channels->rx_count = bp->num_rx_rings;  in bnx2_get_channels()
7777 	channels->tx_count = bp->num_tx_rings;  in bnx2_get_channels()
7785 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_channels()  local
7790 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_set_channels()
7798 	bp->num_req_rx_rings = channels->rx_count;  in bnx2_set_channels()
7799 	bp->num_req_tx_rings = channels->tx_count;  in bnx2_set_channels()
7802 		rc = bnx2_change_ring_size(bp, bp->rx_ring_size,  in bnx2_set_channels()
7803 					   bp->tx_ring_size, true);  in bnx2_set_channels()
7846 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_ioctl()  local
7851 		data->phy_id = bp->phy_addr;  in bnx2_ioctl()
7857 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7863 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7864 		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);  in bnx2_ioctl()
7865 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7873 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7879 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7880 		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);  in bnx2_ioctl()
7881 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7897 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mac_addr()  local
7904 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_change_mac_addr()
7913 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mtu()  local
7916 	return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,  in bnx2_change_mtu()
7924 	struct bnx2 *bp = netdev_priv(dev);  in poll_bnx2()  local
7927 	for (i = 0; i < bp->irq_nvecs; i++) {  in poll_bnx2()
7928 		struct bnx2_irq *irq = &bp->irq_tbl[i];  in poll_bnx2()
7931 		irq->handler(irq->vector, &bp->bnx2_napi[i]);  in poll_bnx2()
7938 bnx2_get_5709_media(struct bnx2 *bp)  in bnx2_get_5709_media()  argument
7940 	u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);  in bnx2_get_5709_media()
7947 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7956 	if (bp->func == 0) {  in bnx2_get_5709_media()
7961 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7969 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7976 bnx2_get_pci_speed(struct bnx2 *bp)  in bnx2_get_pci_speed()  argument
7980 	reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);  in bnx2_get_pci_speed()
7984 		bp->flags |= BNX2_FLAG_PCIX;  in bnx2_get_pci_speed()
7986 		clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);  in bnx2_get_pci_speed()
7991 			bp->bus_speed_mhz = 133;  in bnx2_get_pci_speed()
7995 			bp->bus_speed_mhz = 100;  in bnx2_get_pci_speed()
8000 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
8005 			bp->bus_speed_mhz = 50;  in bnx2_get_pci_speed()
8011 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8017 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
8019 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8023 		bp->flags |= BNX2_FLAG_PCI_32BIT;  in bnx2_get_pci_speed()
8028 bnx2_read_vpd_fw_ver(struct bnx2 *bp)  in bnx2_read_vpd_fw_ver()  argument
8042 	rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data, BNX2_VPD_LEN);  in bnx2_read_vpd_fw_ver()
8066 	memcpy(bp->fw_version, &data[j], len);  in bnx2_read_vpd_fw_ver()
8067 	bp->fw_version[len] = ' ';  in bnx2_read_vpd_fw_ver()
8076 	struct bnx2 *bp;  in bnx2_init_board()  local
8082 	bp = netdev_priv(dev);  in bnx2_init_board()
8084 	bp->flags = 0;  in bnx2_init_board()
8085 	bp->phy_flags = 0;  in bnx2_init_board()
8087 	bp->temp_stats_blk =  in bnx2_init_board()
8090 	if (!bp->temp_stats_blk) {  in bnx2_init_board()
8117 	bp->pm_cap = pdev->pm_cap;  in bnx2_init_board()
8118 	if (bp->pm_cap == 0) {  in bnx2_init_board()
8125 	bp->dev = dev;  in bnx2_init_board()
8126 	bp->pdev = pdev;  in bnx2_init_board()
8128 	spin_lock_init(&bp->phy_lock);  in bnx2_init_board()
8129 	spin_lock_init(&bp->indirect_lock);  in bnx2_init_board()
8131 	mutex_init(&bp->cnic_lock);  in bnx2_init_board()
8133 	INIT_WORK(&bp->reset_task, bnx2_reset_task);  in bnx2_init_board()
8135 	bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +  in bnx2_init_board()
8137 	if (!bp->regview) {  in bnx2_init_board()
8147 	BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8151 	bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_init_board()
8153 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_board()
8159 		bp->flags |= BNX2_FLAG_PCIE;  in bnx2_init_board()
8160 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_board()
8161 			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;  in bnx2_init_board()
8163 		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);  in bnx2_init_board()
8164 		if (bp->pcix_cap == 0) {  in bnx2_init_board()
8170 		bp->flags |= BNX2_FLAG_BROKEN_STATS;  in bnx2_init_board()
8173 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8174 	    BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {  in bnx2_init_board()
8176 			bp->flags |= BNX2_FLAG_MSIX_CAP;  in bnx2_init_board()
8179 	if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&  in bnx2_init_board()
8180 	    BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {  in bnx2_init_board()
8182 			bp->flags |= BNX2_FLAG_MSI_CAP;  in bnx2_init_board()
8186 	if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8205 	if (!(bp->flags & BNX2_FLAG_PCIE))  in bnx2_init_board()
8206 		bnx2_get_pci_speed(bp);  in bnx2_init_board()
8209 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8210 		reg = BNX2_RD(bp, PCI_COMMAND);  in bnx2_init_board()
8212 		BNX2_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()
8213 	} else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&  in bnx2_init_board()
8214 		!(bp->flags & BNX2_FLAG_PCIX)) {  in bnx2_init_board()
8221 	bnx2_init_nvram(bp);  in bnx2_init_board()
8223 	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);  in bnx2_init_board()
8225 	if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)  in bnx2_init_board()
8226 		bp->func = 1;  in bnx2_init_board()
8230 		u32 off = bp->func << 2;  in bnx2_init_board()
8232 		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);  in bnx2_init_board()
8234 		bp->shmem_base = HOST_VIEW_SHMEM_BASE;  in bnx2_init_board()
8239 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);  in bnx2_init_board()
8248 	bnx2_read_vpd_fw_ver(bp);  in bnx2_init_board()
8250 	j = strlen(bp->fw_version);  in bnx2_init_board()
8251 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);  in bnx2_init_board()
8256 			bp->fw_version[j++] = 'b';  in bnx2_init_board()
8257 			bp->fw_version[j++] = 'c';  in bnx2_init_board()
8258 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8263 				bp->fw_version[j++] = (num / k) + '0';  in bnx2_init_board()
8268 			bp->fw_version[j++] = '.';  in bnx2_init_board()
8270 	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_init_board()
8272 		bp->wol = 1;  in bnx2_init_board()
8275 		bp->flags |= BNX2_FLAG_ASF_ENABLE;  in bnx2_init_board()
8278 			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8284 	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8288 		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);  in bnx2_init_board()
8291 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8293 			reg = bnx2_reg_rd_ind(bp, addr + i * 4);  in bnx2_init_board()
8295 			memcpy(&bp->fw_version[j], &reg, 4);  in bnx2_init_board()
8300 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);  in bnx2_init_board()
8301 	bp->mac_addr[0] = (u8) (reg >> 8);  in bnx2_init_board()
8302 	bp->mac_addr[1] = (u8) reg;  in bnx2_init_board()
8304 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);  in bnx2_init_board()
8305 	bp->mac_addr[2] = (u8) (reg >> 24);  in bnx2_init_board()
8306 	bp->mac_addr[3] = (u8) (reg >> 16);  in bnx2_init_board()
8307 	bp->mac_addr[4] = (u8) (reg >> 8);  in bnx2_init_board()
8308 	bp->mac_addr[5] = (u8) reg;  in bnx2_init_board()
8310 	bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;  in bnx2_init_board()
8311 	bnx2_set_rx_ring_size(bp, 255);  in bnx2_init_board()
8313 	bp->tx_quick_cons_trip_int = 2;  in bnx2_init_board()
8314 	bp->tx_quick_cons_trip = 20;  in bnx2_init_board()
8315 	bp->tx_ticks_int = 18;  in bnx2_init_board()
8316 	bp->tx_ticks = 80;  in bnx2_init_board()
8318 	bp->rx_quick_cons_trip_int = 2;  in bnx2_init_board()
8319 	bp->rx_quick_cons_trip = 12;  in bnx2_init_board()
8320 	bp->rx_ticks_int = 18;  in bnx2_init_board()
8321 	bp->rx_ticks = 18;  in bnx2_init_board()
8323 	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_init_board()
8325 	bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_init_board()
8327 	bp->phy_addr = 1;  in bnx2_init_board()
8335 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_board()
8336 		bnx2_get_5709_media(bp);  in bnx2_init_board()
8337 	else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)  in bnx2_init_board()
8338 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_init_board()
8340 	bp->phy_port = PORT_TP;  in bnx2_init_board()
8341 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_board()
8342 		bp->phy_port = PORT_FIBRE;  in bnx2_init_board()
8343 		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_board()
8345 			bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8346 			bp->wol = 0;  in bnx2_init_board()
8348 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {  in bnx2_init_board()
8355 				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;  in bnx2_init_board()
8357 			bp->phy_addr = 2;  in bnx2_init_board()
8359 				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;  in bnx2_init_board()
8361 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||  in bnx2_init_board()
8362 		   BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8363 		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;  in bnx2_init_board()
8364 	else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8365 		 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||  in bnx2_init_board()
8366 		  BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))  in bnx2_init_board()
8367 		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;  in bnx2_init_board()
8369 	bnx2_init_fw_cap(bp);  in bnx2_init_board()
8371 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_board()
8372 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_board()
8373 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||  in bnx2_init_board()
8374 	    !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {  in bnx2_init_board()
8375 		bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8376 		bp->wol = 0;  in bnx2_init_board()
8379 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_init_board()
8380 		device_set_wakeup_capable(&bp->pdev->dev, false);  in bnx2_init_board()
8382 		device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_init_board()
8384 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8385 		bp->tx_quick_cons_trip_int =  in bnx2_init_board()
8386 			bp->tx_quick_cons_trip;  in bnx2_init_board()
8387 		bp->tx_ticks_int = bp->tx_ticks;  in bnx2_init_board()
8388 		bp->rx_quick_cons_trip_int =  in bnx2_init_board()
8389 			bp->rx_quick_cons_trip;  in bnx2_init_board()
8390 		bp->rx_ticks_int = bp->rx_ticks;  in bnx2_init_board()
8391 		bp->comp_prod_trip_int = bp->comp_prod_trip;  in bnx2_init_board()
8392 		bp->com_ticks_int = bp->com_ticks;  in bnx2_init_board()
8393 		bp->cmd_ticks_int = bp->cmd_ticks;  in bnx2_init_board()
8406 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {  in bnx2_init_board()
8422 	bnx2_set_default_link(bp);  in bnx2_init_board()
8423 	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;  in bnx2_init_board()
8425 	timer_setup(&bp->timer, bnx2_timer, 0);  in bnx2_init_board()
8426 	bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);  in bnx2_init_board()
8429 	if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)  in bnx2_init_board()
8430 		bp->cnic_eth_dev.max_iscsi_conn =  in bnx2_init_board()
8431 			(bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &  in bnx2_init_board()
8433 	bp->cnic_probe = bnx2_cnic_probe;  in bnx2_init_board()
8440 	pci_iounmap(pdev, bp->regview);  in bnx2_init_board()
8441 	bp->regview = NULL;  in bnx2_init_board()
8450 	kfree(bp->temp_stats_blk);  in bnx2_init_board()
8456 bnx2_bus_string(struct bnx2 *bp, char *str)  in bnx2_bus_string()  argument
8460 	if (bp->flags & BNX2_FLAG_PCIE) {  in bnx2_bus_string()
8464 		if (bp->flags & BNX2_FLAG_PCIX)  in bnx2_bus_string()
8466 		if (bp->flags & BNX2_FLAG_PCI_32BIT)  in bnx2_bus_string()
8470 		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);  in bnx2_bus_string()
8476 bnx2_del_napi(struct bnx2 *bp)  in bnx2_del_napi()  argument
8480 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_del_napi()
8481 		netif_napi_del(&bp->bnx2_napi[i].napi);  in bnx2_del_napi()
8485 bnx2_init_napi(struct bnx2 *bp)  in bnx2_init_napi()  argument
8489 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_init_napi()
8490 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_init_napi()
8498 		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll);  in bnx2_init_napi()
8499 		bnapi->bp = bp;  in bnx2_init_napi()
8524 	struct bnx2 *bp;  in bnx2_init_one()  local
8529 	dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);  in bnx2_init_one()
8541 	bp = netdev_priv(dev);  in bnx2_init_one()
8552 		bnx2_wait_dma_complete(bp);  in bnx2_init_one()
8554 	eth_hw_addr_set(dev, bp->mac_addr);  in bnx2_init_one()
8560 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_one()
8570 	if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_init_one()
8580 		    ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',  in bnx2_init_one()
8581 		    ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),  in bnx2_init_one()
8582 		    bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),  in bnx2_init_one()
8588 	pci_iounmap(pdev, bp->regview);  in bnx2_init_one()
8601 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_remove_one()  local
8605 	del_timer_sync(&bp->timer);  in bnx2_remove_one()
8606 	cancel_work_sync(&bp->reset_task);  in bnx2_remove_one()
8608 	pci_iounmap(bp->pdev, bp->regview);  in bnx2_remove_one()
8611 	kfree(bp->temp_stats_blk);  in bnx2_remove_one()
8613 	bnx2_release_firmware(bp);  in bnx2_remove_one()
8626 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_suspend()  local
8629 		cancel_work_sync(&bp->reset_task);  in bnx2_suspend()
8630 		bnx2_netif_stop(bp, true);  in bnx2_suspend()
8632 		del_timer_sync(&bp->timer);  in bnx2_suspend()
8633 		bnx2_shutdown_chip(bp);  in bnx2_suspend()
8634 		__bnx2_free_irq(bp);  in bnx2_suspend()
8635 		bnx2_free_skbs(bp);  in bnx2_suspend()
8637 	bnx2_setup_wol(bp);  in bnx2_suspend()
8645 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_resume()  local
8650 	bnx2_set_power_state(bp, PCI_D0);  in bnx2_resume()
8652 	bnx2_request_irq(bp);  in bnx2_resume()
8653 	bnx2_init_nic(bp, 1);  in bnx2_resume()
8654 	bnx2_netif_start(bp, true);  in bnx2_resume()
8678 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_error_detected()  local
8689 		bnx2_netif_stop(bp, true);  in bnx2_io_error_detected()
8690 		del_timer_sync(&bp->timer);  in bnx2_io_error_detected()
8691 		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_io_error_detected()
8710 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_slot_reset()  local
8724 			err = bnx2_init_nic(bp, 1);  in bnx2_io_slot_reset()
8731 		bnx2_napi_enable(bp);  in bnx2_io_slot_reset()
8749 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_resume()  local
8753 		bnx2_netif_start(bp, true);  in bnx2_io_resume()
8762 	struct bnx2 *bp;  in bnx2_shutdown()  local
8767 	bp = netdev_priv(dev);  in bnx2_shutdown()
8768 	if (!bp)  in bnx2_shutdown()
8773 		dev_close(bp->dev);  in bnx2_shutdown()
8776 		bnx2_set_power_state(bp, PCI_D3hot);  in bnx2_shutdown()