Lines Matching +full:adv +full:- +full:extra +full:- +full:delay
3 * Copyright (c) 2004-2014 Broadcom Corporation
4 * Copyright (c) 2014-2015 QLogic Corporation
30 #include <linux/dma-mapping.h>
34 #include <linux/delay.h>
61 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
62 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
63 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
64 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
65 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
104 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
107 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
109 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
110 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
111 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
112 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
113 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
114 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
151 "EEPROM - slow"},
157 /* Saifun SA25F010 (non-buffered flash) */
162 "Non-buffered flash (128kB)"},
163 /* Saifun SA25F020 (non-buffered flash) */
168 "Non-buffered flash (256kB)"},
174 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
178 "Entry 0101: ST M45PE10 (128kB non-buffered)"},
179 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
183 "Entry 0110: ST M45PE20 (256kB non-buffered)"},
184 /* Saifun SA25F005 (non-buffered flash) */
189 "Non-buffered flash (64kB)"},
194 "EEPROM - fast"},
253 diff = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons); in bnx2_tx_avail()
259 return bp->tx_ring_size - diff; in bnx2_tx_avail()
268 spin_lock_irqsave(&bp->indirect_lock, flags); in bnx2_reg_rd_ind()
271 spin_unlock_irqrestore(&bp->indirect_lock, flags); in bnx2_reg_rd_ind()
280 spin_lock_irqsave(&bp->indirect_lock, flags); in bnx2_reg_wr_ind()
283 spin_unlock_irqrestore(&bp->indirect_lock, flags); in bnx2_reg_wr_ind()
289 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); in bnx2_shmem_wr()
295 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); in bnx2_shmem_rd()
304 spin_lock_irqsave(&bp->indirect_lock, flags); in bnx2_ctx_wr()
321 spin_unlock_irqrestore(&bp->indirect_lock, flags); in bnx2_ctx_wr()
329 struct drv_ctl_io *io = &info->data.io; in bnx2_drv_ctl()
331 switch (info->cmd) { in bnx2_drv_ctl()
333 bnx2_reg_wr_ind(bp, io->offset, io->data); in bnx2_drv_ctl()
336 io->data = bnx2_reg_rd_ind(bp, io->offset); in bnx2_drv_ctl()
339 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); in bnx2_drv_ctl()
342 return -EINVAL; in bnx2_drv_ctl()
349 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_setup_cnic_irq_info()
350 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_setup_cnic_irq_info()
353 if (bp->flags & BNX2_FLAG_USING_MSIX) { in bnx2_setup_cnic_irq_info()
354 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; in bnx2_setup_cnic_irq_info()
355 bnapi->cnic_present = 0; in bnx2_setup_cnic_irq_info()
356 sb_id = bp->irq_nvecs; in bnx2_setup_cnic_irq_info()
357 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
359 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; in bnx2_setup_cnic_irq_info()
360 bnapi->cnic_tag = bnapi->last_status_idx; in bnx2_setup_cnic_irq_info()
361 bnapi->cnic_present = 1; in bnx2_setup_cnic_irq_info()
363 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
366 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; in bnx2_setup_cnic_irq_info()
367 cp->irq_arr[0].status_blk = (void *) in bnx2_setup_cnic_irq_info()
368 ((unsigned long) bnapi->status_blk.msi + in bnx2_setup_cnic_irq_info()
370 cp->irq_arr[0].status_blk_map = bp->status_blk_mapping; in bnx2_setup_cnic_irq_info()
371 cp->irq_arr[0].status_blk_num = sb_id; in bnx2_setup_cnic_irq_info()
372 cp->num_irq = 1; in bnx2_setup_cnic_irq_info()
379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_register_cnic()
382 return -EINVAL; in bnx2_register_cnic()
384 if (cp->drv_state & CNIC_DRV_STATE_REGD) in bnx2_register_cnic()
385 return -EBUSY; in bnx2_register_cnic()
388 return -ENODEV; in bnx2_register_cnic()
390 bp->cnic_data = data; in bnx2_register_cnic()
391 rcu_assign_pointer(bp->cnic_ops, ops); in bnx2_register_cnic()
393 cp->num_irq = 0; in bnx2_register_cnic()
394 cp->drv_state = CNIC_DRV_STATE_REGD; in bnx2_register_cnic()
404 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_unregister_cnic()
405 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_unregister_cnic()
407 mutex_lock(&bp->cnic_lock); in bnx2_unregister_cnic()
408 cp->drv_state = 0; in bnx2_unregister_cnic()
409 bnapi->cnic_present = 0; in bnx2_unregister_cnic()
410 RCU_INIT_POINTER(bp->cnic_ops, NULL); in bnx2_unregister_cnic()
411 mutex_unlock(&bp->cnic_lock); in bnx2_unregister_cnic()
419 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_cnic_probe()
421 if (!cp->max_iscsi_conn) in bnx2_cnic_probe()
424 cp->drv_owner = THIS_MODULE; in bnx2_cnic_probe()
425 cp->chip_id = bp->chip_id; in bnx2_cnic_probe()
426 cp->pdev = bp->pdev; in bnx2_cnic_probe()
427 cp->io_base = bp->regview; in bnx2_cnic_probe()
428 cp->drv_ctl = bnx2_drv_ctl; in bnx2_cnic_probe()
429 cp->drv_register_cnic = bnx2_register_cnic; in bnx2_cnic_probe()
430 cp->drv_unregister_cnic = bnx2_unregister_cnic; in bnx2_cnic_probe()
441 mutex_lock(&bp->cnic_lock); in bnx2_cnic_stop()
442 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2_cnic_stop()
443 lockdep_is_held(&bp->cnic_lock)); in bnx2_cnic_stop()
446 c_ops->cnic_ctl(bp->cnic_data, &info); in bnx2_cnic_stop()
448 mutex_unlock(&bp->cnic_lock); in bnx2_cnic_stop()
457 mutex_lock(&bp->cnic_lock); in bnx2_cnic_start()
458 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2_cnic_start()
459 lockdep_is_held(&bp->cnic_lock)); in bnx2_cnic_start()
461 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { in bnx2_cnic_start()
462 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_cnic_start()
464 bnapi->cnic_tag = bnapi->last_status_idx; in bnx2_cnic_start()
467 c_ops->cnic_ctl(bp->cnic_data, &info); in bnx2_cnic_start()
469 mutex_unlock(&bp->cnic_lock); in bnx2_cnic_start()
492 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_read_phy()
502 val1 = (bp->phy_addr << 21) | (reg << 16) | in bnx2_read_phy()
523 ret = -EBUSY; in bnx2_read_phy()
530 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_read_phy()
549 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_write_phy()
559 val1 = (bp->phy_addr << 21) | (reg << 16) | val | in bnx2_write_phy()
575 ret = -EBUSY; in bnx2_write_phy()
579 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_write_phy()
598 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_disable_int()
599 bnapi = &bp->bnx2_napi[i]; in bnx2_disable_int()
600 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_disable_int()
612 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_enable_int()
613 bnapi = &bp->bnx2_napi[i]; in bnx2_enable_int()
615 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_enable_int()
618 bnapi->last_status_idx); in bnx2_enable_int()
620 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_enable_int()
622 bnapi->last_status_idx); in bnx2_enable_int()
624 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); in bnx2_enable_int()
632 atomic_inc(&bp->intr_sem); in bnx2_disable_int_sync()
633 if (!netif_running(bp->dev)) in bnx2_disable_int_sync()
637 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_disable_int_sync()
638 synchronize_irq(bp->irq_tbl[i].vector); in bnx2_disable_int_sync()
646 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_disable()
647 napi_disable(&bp->bnx2_napi[i].napi); in bnx2_napi_disable()
655 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_enable()
656 napi_enable(&bp->bnx2_napi[i].napi); in bnx2_napi_enable()
664 if (netif_running(bp->dev)) { in bnx2_netif_stop()
666 netif_tx_disable(bp->dev); in bnx2_netif_stop()
669 netif_carrier_off(bp->dev); /* prevent tx timeout */ in bnx2_netif_stop()
675 if (atomic_dec_and_test(&bp->intr_sem)) { in bnx2_netif_start()
676 if (netif_running(bp->dev)) { in bnx2_netif_start()
677 netif_tx_wake_all_queues(bp->dev); in bnx2_netif_start()
678 spin_lock_bh(&bp->phy_lock); in bnx2_netif_start()
679 if (bp->link_up) in bnx2_netif_start()
680 netif_carrier_on(bp->dev); in bnx2_netif_start()
681 spin_unlock_bh(&bp->phy_lock); in bnx2_netif_start()
695 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_mem()
696 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_tx_mem()
697 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_free_tx_mem()
699 if (txr->tx_desc_ring) { in bnx2_free_tx_mem()
700 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, in bnx2_free_tx_mem()
701 txr->tx_desc_ring, in bnx2_free_tx_mem()
702 txr->tx_desc_mapping); in bnx2_free_tx_mem()
703 txr->tx_desc_ring = NULL; in bnx2_free_tx_mem()
705 kfree(txr->tx_buf_ring); in bnx2_free_tx_mem()
706 txr->tx_buf_ring = NULL; in bnx2_free_tx_mem()
715 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_mem()
716 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_rx_mem()
717 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_free_rx_mem()
720 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_free_rx_mem()
721 if (rxr->rx_desc_ring[j]) in bnx2_free_rx_mem()
722 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, in bnx2_free_rx_mem()
723 rxr->rx_desc_ring[j], in bnx2_free_rx_mem()
724 rxr->rx_desc_mapping[j]); in bnx2_free_rx_mem()
725 rxr->rx_desc_ring[j] = NULL; in bnx2_free_rx_mem()
727 vfree(rxr->rx_buf_ring); in bnx2_free_rx_mem()
728 rxr->rx_buf_ring = NULL; in bnx2_free_rx_mem()
730 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_free_rx_mem()
731 if (rxr->rx_pg_desc_ring[j]) in bnx2_free_rx_mem()
732 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, in bnx2_free_rx_mem()
733 rxr->rx_pg_desc_ring[j], in bnx2_free_rx_mem()
734 rxr->rx_pg_desc_mapping[j]); in bnx2_free_rx_mem()
735 rxr->rx_pg_desc_ring[j] = NULL; in bnx2_free_rx_mem()
737 vfree(rxr->rx_pg_ring); in bnx2_free_rx_mem()
738 rxr->rx_pg_ring = NULL; in bnx2_free_rx_mem()
747 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_alloc_tx_mem()
748 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_alloc_tx_mem()
749 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_alloc_tx_mem()
751 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); in bnx2_alloc_tx_mem()
752 if (!txr->tx_buf_ring) in bnx2_alloc_tx_mem()
753 return -ENOMEM; in bnx2_alloc_tx_mem()
755 txr->tx_desc_ring = in bnx2_alloc_tx_mem()
756 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, in bnx2_alloc_tx_mem()
757 &txr->tx_desc_mapping, GFP_KERNEL); in bnx2_alloc_tx_mem()
758 if (!txr->tx_desc_ring) in bnx2_alloc_tx_mem()
759 return -ENOMEM; in bnx2_alloc_tx_mem()
769 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_alloc_rx_mem()
770 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_alloc_rx_mem()
771 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_alloc_rx_mem()
774 rxr->rx_buf_ring = in bnx2_alloc_rx_mem()
775 vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring)); in bnx2_alloc_rx_mem()
776 if (!rxr->rx_buf_ring) in bnx2_alloc_rx_mem()
777 return -ENOMEM; in bnx2_alloc_rx_mem()
779 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_alloc_rx_mem()
780 rxr->rx_desc_ring[j] = in bnx2_alloc_rx_mem()
781 dma_alloc_coherent(&bp->pdev->dev, in bnx2_alloc_rx_mem()
783 &rxr->rx_desc_mapping[j], in bnx2_alloc_rx_mem()
785 if (!rxr->rx_desc_ring[j]) in bnx2_alloc_rx_mem()
786 return -ENOMEM; in bnx2_alloc_rx_mem()
790 if (bp->rx_pg_ring_size) { in bnx2_alloc_rx_mem()
791 rxr->rx_pg_ring = in bnx2_alloc_rx_mem()
793 bp->rx_max_pg_ring)); in bnx2_alloc_rx_mem()
794 if (!rxr->rx_pg_ring) in bnx2_alloc_rx_mem()
795 return -ENOMEM; in bnx2_alloc_rx_mem()
799 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_alloc_rx_mem()
800 rxr->rx_pg_desc_ring[j] = in bnx2_alloc_rx_mem()
801 dma_alloc_coherent(&bp->pdev->dev, in bnx2_alloc_rx_mem()
803 &rxr->rx_pg_desc_mapping[j], in bnx2_alloc_rx_mem()
805 if (!rxr->rx_pg_desc_ring[j]) in bnx2_alloc_rx_mem()
806 return -ENOMEM; in bnx2_alloc_rx_mem()
818 if (bp->status_blk) { in bnx2_free_stats_blk()
819 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, in bnx2_free_stats_blk()
820 bp->status_blk, in bnx2_free_stats_blk()
821 bp->status_blk_mapping); in bnx2_free_stats_blk()
822 bp->status_blk = NULL; in bnx2_free_stats_blk()
823 bp->stats_blk = NULL; in bnx2_free_stats_blk()
836 if (bp->flags & BNX2_FLAG_MSIX_CAP) in bnx2_alloc_stats_blk()
839 bp->status_stats_size = status_blk_size + in bnx2_alloc_stats_blk()
841 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, in bnx2_alloc_stats_blk()
842 &bp->status_blk_mapping, GFP_KERNEL); in bnx2_alloc_stats_blk()
844 return -ENOMEM; in bnx2_alloc_stats_blk()
846 bp->status_blk = status_blk; in bnx2_alloc_stats_blk()
847 bp->stats_blk = status_blk + status_blk_size; in bnx2_alloc_stats_blk()
848 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; in bnx2_alloc_stats_blk()
857 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_free_mem()
862 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_free_mem()
863 if (bp->ctx_blk[i]) { in bnx2_free_mem()
864 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, in bnx2_free_mem()
865 bp->ctx_blk[i], in bnx2_free_mem()
866 bp->ctx_blk_mapping[i]); in bnx2_free_mem()
867 bp->ctx_blk[i] = NULL; in bnx2_free_mem()
871 if (bnapi->status_blk.msi) in bnx2_free_mem()
872 bnapi->status_blk.msi = NULL; in bnx2_free_mem()
881 bnapi = &bp->bnx2_napi[0]; in bnx2_alloc_mem()
882 bnapi->status_blk.msi = bp->status_blk; in bnx2_alloc_mem()
883 bnapi->hw_tx_cons_ptr = in bnx2_alloc_mem()
884 &bnapi->status_blk.msi->status_tx_quick_consumer_index0; in bnx2_alloc_mem()
885 bnapi->hw_rx_cons_ptr = in bnx2_alloc_mem()
886 &bnapi->status_blk.msi->status_rx_quick_consumer_index0; in bnx2_alloc_mem()
887 if (bp->flags & BNX2_FLAG_MSIX_CAP) { in bnx2_alloc_mem()
888 for (i = 1; i < bp->irq_nvecs; i++) { in bnx2_alloc_mem()
891 bnapi = &bp->bnx2_napi[i]; in bnx2_alloc_mem()
893 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i); in bnx2_alloc_mem()
894 bnapi->status_blk.msix = sblk; in bnx2_alloc_mem()
895 bnapi->hw_tx_cons_ptr = in bnx2_alloc_mem()
896 &sblk->status_tx_quick_consumer_index; in bnx2_alloc_mem()
897 bnapi->hw_rx_cons_ptr = in bnx2_alloc_mem()
898 &sblk->status_rx_quick_consumer_index; in bnx2_alloc_mem()
899 bnapi->int_num = i << 24; in bnx2_alloc_mem()
904 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; in bnx2_alloc_mem()
905 if (bp->ctx_pages == 0) in bnx2_alloc_mem()
906 bp->ctx_pages = 1; in bnx2_alloc_mem()
907 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_alloc_mem()
908 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, in bnx2_alloc_mem()
910 &bp->ctx_blk_mapping[i], in bnx2_alloc_mem()
912 if (!bp->ctx_blk[i]) in bnx2_alloc_mem()
929 return -ENOMEM; in bnx2_alloc_mem()
937 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_report_fw_link()
940 if (bp->link_up) { in bnx2_report_fw_link()
943 switch (bp->line_speed) { in bnx2_report_fw_link()
945 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
951 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
957 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
963 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
972 if (bp->autoneg) { in bnx2_report_fw_link()
975 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_report_fw_link()
976 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_report_fw_link()
979 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) in bnx2_report_fw_link()
994 return (bp->phy_port == PORT_FIBRE) ? "SerDes" : in bnx2_xceiver_str()
995 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : in bnx2_xceiver_str()
1002 if (bp->link_up) { in bnx2_report_link()
1003 netif_carrier_on(bp->dev); in bnx2_report_link()
1004 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", in bnx2_report_link()
1006 bp->line_speed, in bnx2_report_link()
1007 bp->duplex == DUPLEX_FULL ? "full" : "half"); in bnx2_report_link()
1009 if (bp->flow_ctrl) { in bnx2_report_link()
1010 if (bp->flow_ctrl & FLOW_CTRL_RX) { in bnx2_report_link()
1012 if (bp->flow_ctrl & FLOW_CTRL_TX) in bnx2_report_link()
1022 netif_carrier_off(bp->dev); in bnx2_report_link()
1023 netdev_err(bp->dev, "NIC %s Link is Down\n", in bnx2_report_link()
1035 bp->flow_ctrl = 0; in bnx2_resolve_flow_ctrl()
1036 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != in bnx2_resolve_flow_ctrl()
1039 if (bp->duplex == DUPLEX_FULL) { in bnx2_resolve_flow_ctrl()
1040 bp->flow_ctrl = bp->req_flow_ctrl; in bnx2_resolve_flow_ctrl()
1045 if (bp->duplex != DUPLEX_FULL) { in bnx2_resolve_flow_ctrl()
1049 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_resolve_flow_ctrl()
1055 bp->flow_ctrl |= FLOW_CTRL_TX; in bnx2_resolve_flow_ctrl()
1057 bp->flow_ctrl |= FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1061 bnx2_read_phy(bp, bp->mii_adv, &local_adv); in bnx2_resolve_flow_ctrl()
1062 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); in bnx2_resolve_flow_ctrl()
1064 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_resolve_flow_ctrl()
1081 /* See Table 28B-3 of 802.3ab-1999 spec. */ in bnx2_resolve_flow_ctrl()
1085 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1088 bp->flow_ctrl = FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1093 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1101 bp->flow_ctrl = FLOW_CTRL_TX; in bnx2_resolve_flow_ctrl()
1111 bp->link_up = 1; in bnx2_5709s_linkup()
1117 if ((bp->autoneg & AUTONEG_SPEED) == 0) { in bnx2_5709s_linkup()
1118 bp->line_speed = bp->req_line_speed; in bnx2_5709s_linkup()
1119 bp->duplex = bp->req_duplex; in bnx2_5709s_linkup()
1125 bp->line_speed = SPEED_10; in bnx2_5709s_linkup()
1128 bp->line_speed = SPEED_100; in bnx2_5709s_linkup()
1132 bp->line_speed = SPEED_1000; in bnx2_5709s_linkup()
1135 bp->line_speed = SPEED_2500; in bnx2_5709s_linkup()
1139 bp->duplex = DUPLEX_FULL; in bnx2_5709s_linkup()
1141 bp->duplex = DUPLEX_HALF; in bnx2_5709s_linkup()
1150 bp->link_up = 1; in bnx2_5708s_linkup()
1154 bp->line_speed = SPEED_10; in bnx2_5708s_linkup()
1157 bp->line_speed = SPEED_100; in bnx2_5708s_linkup()
1160 bp->line_speed = SPEED_1000; in bnx2_5708s_linkup()
1163 bp->line_speed = SPEED_2500; in bnx2_5708s_linkup()
1167 bp->duplex = DUPLEX_FULL; in bnx2_5708s_linkup()
1169 bp->duplex = DUPLEX_HALF; in bnx2_5708s_linkup()
1179 bp->link_up = 1; in bnx2_5706s_linkup()
1180 bp->line_speed = SPEED_1000; in bnx2_5706s_linkup()
1182 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5706s_linkup()
1184 bp->duplex = DUPLEX_FULL; in bnx2_5706s_linkup()
1187 bp->duplex = DUPLEX_HALF; in bnx2_5706s_linkup()
1194 bnx2_read_phy(bp, bp->mii_adv, &local_adv); in bnx2_5706s_linkup()
1195 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); in bnx2_5706s_linkup()
1201 bp->duplex = DUPLEX_FULL; in bnx2_5706s_linkup()
1204 bp->duplex = DUPLEX_HALF; in bnx2_5706s_linkup()
1216 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX; in bnx2_copper_linkup()
1218 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_copper_linkup()
1227 bp->line_speed = SPEED_1000; in bnx2_copper_linkup()
1228 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1231 bp->line_speed = SPEED_1000; in bnx2_copper_linkup()
1232 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1235 bnx2_read_phy(bp, bp->mii_adv, &local_adv); in bnx2_copper_linkup()
1236 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); in bnx2_copper_linkup()
1240 bp->line_speed = SPEED_100; in bnx2_copper_linkup()
1241 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1244 bp->line_speed = SPEED_100; in bnx2_copper_linkup()
1245 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1248 bp->line_speed = SPEED_10; in bnx2_copper_linkup()
1249 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1252 bp->line_speed = SPEED_10; in bnx2_copper_linkup()
1253 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1256 bp->line_speed = 0; in bnx2_copper_linkup()
1257 bp->link_up = 0; in bnx2_copper_linkup()
1263 bp->line_speed = SPEED_100; in bnx2_copper_linkup()
1266 bp->line_speed = SPEED_10; in bnx2_copper_linkup()
1269 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1272 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1276 if (bp->link_up) { in bnx2_copper_linkup()
1281 bp->phy_flags |= BNX2_PHY_FLAG_MDIX; in bnx2_copper_linkup()
1296 if (bp->flow_ctrl & FLOW_CTRL_TX) in bnx2_init_rx_context()
1308 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { in bnx2_init_all_rx_contexts()
1321 if (bp->link_up && (bp->line_speed == SPEED_1000) && in bnx2_set_mac_link()
1322 (bp->duplex == DUPLEX_HALF)) { in bnx2_set_mac_link()
1333 if (bp->link_up) { in bnx2_set_mac_link()
1334 switch (bp->line_speed) { in bnx2_set_mac_link()
1357 if (bp->duplex == DUPLEX_HALF) in bnx2_set_mac_link()
1362 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; in bnx2_set_mac_link()
1364 if (bp->flow_ctrl & FLOW_CTRL_RX) in bnx2_set_mac_link()
1365 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; in bnx2_set_mac_link()
1366 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); in bnx2_set_mac_link()
1372 if (bp->flow_ctrl & FLOW_CTRL_TX) in bnx2_set_mac_link()
1385 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_enable_bmsr1()
1394 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_disable_bmsr1()
1406 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_test_and_enable_2g5()
1409 if (bp->autoneg & AUTONEG_SPEED) in bnx2_test_and_enable_2g5()
1410 bp->advertising |= ADVERTISED_2500baseX_Full; in bnx2_test_and_enable_2g5()
1415 bnx2_read_phy(bp, bp->mii_up1, &up1); in bnx2_test_and_enable_2g5()
1418 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_enable_2g5()
1435 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_test_and_disable_2g5()
1441 bnx2_read_phy(bp, bp->mii_up1, &up1); in bnx2_test_and_disable_2g5()
1444 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_disable_2g5()
1461 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_enable_forced_2g5()
1478 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_enable_forced_2g5()
1481 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_enable_forced_2g5()
1491 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_enable_forced_2g5()
1493 if (bp->req_duplex == DUPLEX_FULL) in bnx2_enable_forced_2g5()
1496 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_enable_forced_2g5()
1505 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_disable_forced_2g5()
1520 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_disable_forced_2g5()
1523 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_disable_forced_2g5()
1533 if (bp->autoneg & AUTONEG_SPEED) in bnx2_disable_forced_2g5()
1535 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_disable_forced_2g5()
1557 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { in bnx2_set_link()
1558 bp->link_up = 1; in bnx2_set_link()
1562 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_set_link()
1565 link_up = bp->link_up; in bnx2_set_link()
1568 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_set_link()
1569 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_set_link()
1572 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_set_link()
1576 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { in bnx2_set_link()
1578 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; in bnx2_set_link()
1594 bp->link_up = 1; in bnx2_set_link()
1596 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_set_link()
1610 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_set_link()
1611 (bp->autoneg & AUTONEG_SPEED)) in bnx2_set_link()
1614 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { in bnx2_set_link()
1617 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_set_link()
1619 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_set_link()
1621 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_set_link()
1623 bp->link_up = 0; in bnx2_set_link()
1626 if (bp->link_up != link_up) { in bnx2_set_link()
1641 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); in bnx2_reset_phy()
1647 bnx2_read_phy(bp, bp->mii_bmcr, ®); in bnx2_reset_phy()
1654 return -EBUSY; in bnx2_reset_phy()
1662 u32 adv = 0; in bnx2_phy_get_pause_adv() local
1664 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == in bnx2_phy_get_pause_adv()
1667 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_phy_get_pause_adv()
1668 adv = ADVERTISE_1000XPAUSE; in bnx2_phy_get_pause_adv()
1671 adv = ADVERTISE_PAUSE_CAP; in bnx2_phy_get_pause_adv()
1674 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { in bnx2_phy_get_pause_adv()
1675 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_phy_get_pause_adv()
1676 adv = ADVERTISE_1000XPSE_ASYM; in bnx2_phy_get_pause_adv()
1679 adv = ADVERTISE_PAUSE_ASYM; in bnx2_phy_get_pause_adv()
1682 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { in bnx2_phy_get_pause_adv()
1683 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_phy_get_pause_adv()
1684 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; in bnx2_phy_get_pause_adv()
1687 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; in bnx2_phy_get_pause_adv()
1690 return adv; in bnx2_phy_get_pause_adv()
1697 __releases(&bp->phy_lock) in bnx2_setup_remote_phy()
1698 __acquires(&bp->phy_lock) in bnx2_setup_remote_phy()
1704 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_setup_remote_phy()
1706 if (bp->advertising & ADVERTISED_10baseT_Half) in bnx2_setup_remote_phy()
1708 if (bp->advertising & ADVERTISED_10baseT_Full) in bnx2_setup_remote_phy()
1710 if (bp->advertising & ADVERTISED_100baseT_Half) in bnx2_setup_remote_phy()
1712 if (bp->advertising & ADVERTISED_100baseT_Full) in bnx2_setup_remote_phy()
1714 if (bp->advertising & ADVERTISED_1000baseT_Full) in bnx2_setup_remote_phy()
1716 if (bp->advertising & ADVERTISED_2500baseX_Full) in bnx2_setup_remote_phy()
1719 if (bp->req_line_speed == SPEED_2500) in bnx2_setup_remote_phy()
1721 else if (bp->req_line_speed == SPEED_1000) in bnx2_setup_remote_phy()
1723 else if (bp->req_line_speed == SPEED_100) { in bnx2_setup_remote_phy()
1724 if (bp->req_duplex == DUPLEX_FULL) in bnx2_setup_remote_phy()
1728 } else if (bp->req_line_speed == SPEED_10) { in bnx2_setup_remote_phy()
1729 if (bp->req_duplex == DUPLEX_FULL) in bnx2_setup_remote_phy()
1747 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_remote_phy()
1749 spin_lock_bh(&bp->phy_lock); in bnx2_setup_remote_phy()
1756 __releases(&bp->phy_lock) in bnx2_setup_serdes_phy()
1757 __acquires(&bp->phy_lock) in bnx2_setup_serdes_phy()
1759 u32 adv, bmcr; in bnx2_setup_serdes_phy() local
1762 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_setup_serdes_phy()
1765 if (!(bp->autoneg & AUTONEG_SPEED)) { in bnx2_setup_serdes_phy()
1769 if (bp->req_line_speed == SPEED_2500) { in bnx2_setup_serdes_phy()
1772 } else if (bp->req_line_speed == SPEED_1000) { in bnx2_setup_serdes_phy()
1776 bnx2_read_phy(bp, bp->mii_adv, &adv); in bnx2_setup_serdes_phy()
1777 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); in bnx2_setup_serdes_phy()
1779 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_setup_serdes_phy()
1784 if (bp->req_line_speed == SPEED_2500) in bnx2_setup_serdes_phy()
1786 else if (bp->req_line_speed == SPEED_1000) { in bnx2_setup_serdes_phy()
1792 if (bp->req_line_speed == SPEED_2500) in bnx2_setup_serdes_phy()
1798 if (bp->req_duplex == DUPLEX_FULL) { in bnx2_setup_serdes_phy()
1799 adv |= ADVERTISE_1000XFULL; in bnx2_setup_serdes_phy()
1803 adv |= ADVERTISE_1000XHALF; in bnx2_setup_serdes_phy()
1808 if (bp->link_up) { in bnx2_setup_serdes_phy()
1809 bnx2_write_phy(bp, bp->mii_adv, adv & in bnx2_setup_serdes_phy()
1812 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | in bnx2_setup_serdes_phy()
1815 bp->link_up = 0; in bnx2_setup_serdes_phy()
1816 netif_carrier_off(bp->dev); in bnx2_setup_serdes_phy()
1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1820 bnx2_write_phy(bp, bp->mii_adv, adv); in bnx2_setup_serdes_phy()
1821 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1831 if (bp->advertising & ADVERTISED_1000baseT_Full) in bnx2_setup_serdes_phy()
1836 bnx2_read_phy(bp, bp->mii_adv, &adv); in bnx2_setup_serdes_phy()
1837 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_setup_serdes_phy()
1839 bp->serdes_an_pending = 0; in bnx2_setup_serdes_phy()
1840 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { in bnx2_setup_serdes_phy()
1842 if (bp->link_up) { in bnx2_setup_serdes_phy()
1843 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_serdes_phy()
1844 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_serdes_phy()
1846 spin_lock_bh(&bp->phy_lock); in bnx2_setup_serdes_phy()
1849 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_serdes_phy()
1850 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | in bnx2_setup_serdes_phy()
1852 /* Speed up link-up time when the link partner in bnx2_setup_serdes_phy()
1860 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; in bnx2_setup_serdes_phy()
1861 bp->serdes_an_pending = 1; in bnx2_setup_serdes_phy()
1862 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_setup_serdes_phy()
1872 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1891 if (bp->phy_port == PORT_TP) in bnx2_set_default_remote_link()
1897 bp->req_line_speed = 0; in bnx2_set_default_remote_link()
1898 bp->autoneg |= AUTONEG_SPEED; in bnx2_set_default_remote_link()
1899 bp->advertising = ADVERTISED_Autoneg; in bnx2_set_default_remote_link()
1901 bp->advertising |= ADVERTISED_10baseT_Half; in bnx2_set_default_remote_link()
1903 bp->advertising |= ADVERTISED_10baseT_Full; in bnx2_set_default_remote_link()
1905 bp->advertising |= ADVERTISED_100baseT_Half; in bnx2_set_default_remote_link()
1907 bp->advertising |= ADVERTISED_100baseT_Full; in bnx2_set_default_remote_link()
1909 bp->advertising |= ADVERTISED_1000baseT_Full; in bnx2_set_default_remote_link()
1911 bp->advertising |= ADVERTISED_2500baseX_Full; in bnx2_set_default_remote_link()
1913 bp->autoneg = 0; in bnx2_set_default_remote_link()
1914 bp->advertising = 0; in bnx2_set_default_remote_link()
1915 bp->req_duplex = DUPLEX_FULL; in bnx2_set_default_remote_link()
1917 bp->req_line_speed = SPEED_10; in bnx2_set_default_remote_link()
1919 bp->req_duplex = DUPLEX_HALF; in bnx2_set_default_remote_link()
1922 bp->req_line_speed = SPEED_100; in bnx2_set_default_remote_link()
1924 bp->req_duplex = DUPLEX_HALF; in bnx2_set_default_remote_link()
1927 bp->req_line_speed = SPEED_1000; in bnx2_set_default_remote_link()
1929 bp->req_line_speed = SPEED_2500; in bnx2_set_default_remote_link()
1936 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_set_default_link()
1941 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; in bnx2_set_default_link()
1942 bp->req_line_speed = 0; in bnx2_set_default_link()
1943 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_set_default_link()
1946 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; in bnx2_set_default_link()
1951 bp->autoneg = 0; in bnx2_set_default_link()
1952 bp->req_line_speed = bp->line_speed = SPEED_1000; in bnx2_set_default_link()
1953 bp->req_duplex = DUPLEX_FULL; in bnx2_set_default_link()
1956 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; in bnx2_set_default_link()
1965 spin_lock(&bp->indirect_lock); in bnx2_send_heart_beat()
1966 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); in bnx2_send_heart_beat()
1967 addr = bp->shmem_base + BNX2_DRV_PULSE_MB; in bnx2_send_heart_beat()
1970 spin_unlock(&bp->indirect_lock); in bnx2_send_heart_beat()
1977 u8 link_up = bp->link_up; in bnx2_remote_phy_event()
1988 bp->link_up = 0; in bnx2_remote_phy_event()
1992 bp->link_up = 1; in bnx2_remote_phy_event()
1994 bp->duplex = DUPLEX_FULL; in bnx2_remote_phy_event()
1997 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
2000 bp->line_speed = SPEED_10; in bnx2_remote_phy_event()
2003 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
2007 bp->line_speed = SPEED_100; in bnx2_remote_phy_event()
2010 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
2013 bp->line_speed = SPEED_1000; in bnx2_remote_phy_event()
2016 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
2019 bp->line_speed = SPEED_2500; in bnx2_remote_phy_event()
2022 bp->line_speed = 0; in bnx2_remote_phy_event()
2026 bp->flow_ctrl = 0; in bnx2_remote_phy_event()
2027 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != in bnx2_remote_phy_event()
2029 if (bp->duplex == DUPLEX_FULL) in bnx2_remote_phy_event()
2030 bp->flow_ctrl = bp->req_flow_ctrl; in bnx2_remote_phy_event()
2033 bp->flow_ctrl |= FLOW_CTRL_TX; in bnx2_remote_phy_event()
2035 bp->flow_ctrl |= FLOW_CTRL_RX; in bnx2_remote_phy_event()
2038 old_port = bp->phy_port; in bnx2_remote_phy_event()
2040 bp->phy_port = PORT_FIBRE; in bnx2_remote_phy_event()
2042 bp->phy_port = PORT_TP; in bnx2_remote_phy_event()
2044 if (old_port != bp->phy_port) in bnx2_remote_phy_event()
2048 if (bp->link_up != link_up) in bnx2_remote_phy_event()
2074 __releases(&bp->phy_lock) in bnx2_setup_copper_phy()
2075 __acquires(&bp->phy_lock) in bnx2_setup_copper_phy()
2080 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_setup_copper_phy()
2082 bnx2_read_phy(bp, bp->mii_adv, &adv_reg); in bnx2_setup_copper_phy()
2086 new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising); in bnx2_setup_copper_phy()
2088 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_setup_copper_phy()
2097 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising); in bnx2_setup_copper_phy()
2102 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2104 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | in bnx2_setup_copper_phy()
2107 else if (bp->link_up) { in bnx2_setup_copper_phy()
2109 /* or vice-versa. */ in bnx2_setup_copper_phy()
2119 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2122 if (bp->req_line_speed == SPEED_100) { in bnx2_setup_copper_phy()
2125 if (bp->req_duplex == DUPLEX_FULL) { in bnx2_setup_copper_phy()
2131 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2132 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2136 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_copper_phy()
2137 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_copper_phy()
2139 spin_lock_bh(&bp->phy_lock); in bnx2_setup_copper_phy()
2141 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2142 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2145 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_copper_phy()
2152 bp->line_speed = bp->req_line_speed; in bnx2_setup_copper_phy()
2153 bp->duplex = bp->req_duplex; in bnx2_setup_copper_phy()
2166 __releases(&bp->phy_lock) in bnx2_setup_phy()
2167 __acquires(&bp->phy_lock) in bnx2_setup_phy()
2169 if (bp->loopback == MAC_LOOPBACK) in bnx2_setup_phy()
2172 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_setup_phy()
2185 bp->mii_bmcr = MII_BMCR + 0x10; in bnx2_init_5709s_phy()
2186 bp->mii_bmsr = MII_BMSR + 0x10; in bnx2_init_5709s_phy()
2187 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; in bnx2_init_5709s_phy()
2188 bp->mii_adv = MII_ADVERTISE + 0x10; in bnx2_init_5709s_phy()
2189 bp->mii_lpa = MII_LPA + 0x10; in bnx2_init_5709s_phy()
2190 bp->mii_up1 = MII_BNX2_OVER1G_UP1; in bnx2_init_5709s_phy()
2208 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) in bnx2_init_5709s_phy()
2238 bp->mii_up1 = BCM5708S_UP1; in bnx2_init_5708s_phy()
2252 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { in bnx2_init_5708s_phy()
2294 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_init_5706s_phy()
2299 if (bp->dev->mtu > ETH_DATA_LEN) { in bnx2_init_5706s_phy()
2334 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { in bnx2_init_copper_phy()
2345 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { in bnx2_init_copper_phy()
2353 if (bp->dev->mtu > ETH_DATA_LEN) { in bnx2_init_copper_phy()
2376 /* auto-mdix */ in bnx2_init_copper_phy()
2387 __releases(&bp->phy_lock) in bnx2_init_phy()
2388 __acquires(&bp->phy_lock) in bnx2_init_phy()
2393 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; in bnx2_init_phy()
2394 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; in bnx2_init_phy()
2396 bp->mii_bmcr = MII_BMCR; in bnx2_init_phy()
2397 bp->mii_bmsr = MII_BMSR; in bnx2_init_phy()
2398 bp->mii_bmsr1 = MII_BMSR; in bnx2_init_phy()
2399 bp->mii_adv = MII_ADVERTISE; in bnx2_init_phy()
2400 bp->mii_lpa = MII_LPA; in bnx2_init_phy()
2404 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_init_phy()
2408 bp->phy_id = val << 16; in bnx2_init_phy()
2410 bp->phy_id |= val & 0xffff; in bnx2_init_phy()
2412 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_init_phy()
2426 rc = bnx2_setup_phy(bp, bp->phy_port); in bnx2_init_phy()
2440 bp->link_up = 1; in bnx2_set_mac_loopback()
2452 spin_lock_bh(&bp->phy_lock); in bnx2_set_phy_loopback()
2453 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | in bnx2_set_phy_loopback()
2455 spin_unlock_bh(&bp->phy_lock); in bnx2_set_phy_loopback()
2472 bp->link_up = 1; in bnx2_set_phy_loopback()
2479 struct net_device *dev = bp->dev; in bnx2_dump_mcp_state()
2482 netdev_err(dev, "<--- start MCP states dump --->\n"); in bnx2_dump_mcp_state()
2516 netdev_err(dev, "<--- end MCP states dump --->\n"); in bnx2_dump_mcp_state()
2525 bp->fw_wr_seq++; in bnx2_fw_sync()
2526 msg_data |= bp->fw_wr_seq; in bnx2_fw_sync()
2527 bp->fw_last_msg = msg_data; in bnx2_fw_sync()
2557 return -EBUSY; in bnx2_fw_sync()
2561 return -EIO; in bnx2_fw_sync()
2573 val |= (BNX2_PAGE_BITS - 8) << 16; in bnx2_init_5709_context()
2582 return -EBUSY; in bnx2_init_5709_context()
2584 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_init_5709_context()
2587 if (bp->ctx_blk[i]) in bnx2_init_5709_context()
2588 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); in bnx2_init_5709_context()
2590 return -ENOMEM; in bnx2_init_5709_context()
2593 (bp->ctx_blk_mapping[i] & 0xffffffff) | in bnx2_init_5709_context()
2596 (u64) bp->ctx_blk_mapping[i] >> 32); in bnx2_init_5709_context()
2607 ret = -EBUSY; in bnx2_init_5709_context()
2624 vcid--; in bnx2_init_context()
2666 return -ENOMEM; in bnx2_alloc_bad_rbuf()
2695 good_mbuf_cnt--; in bnx2_alloc_bad_rbuf()
2725 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; in bnx2_alloc_rx_page()
2727 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; in bnx2_alloc_rx_page()
2731 return -ENOMEM; in bnx2_alloc_rx_page()
2732 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, in bnx2_alloc_rx_page()
2734 if (dma_mapping_error(&bp->pdev->dev, mapping)) { in bnx2_alloc_rx_page()
2736 return -EIO; in bnx2_alloc_rx_page()
2739 rx_pg->page = page; in bnx2_alloc_rx_page()
2741 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_alloc_rx_page()
2742 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_page()
2749 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; in bnx2_free_rx_page()
2750 struct page *page = rx_pg->page; in bnx2_free_rx_page()
2755 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping), in bnx2_free_rx_page()
2759 rx_pg->page = NULL; in bnx2_free_rx_page()
2766 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index]; in bnx2_alloc_rx_data()
2769 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; in bnx2_alloc_rx_data()
2771 data = kmalloc(bp->rx_buf_size, gfp); in bnx2_alloc_rx_data()
2773 return -ENOMEM; in bnx2_alloc_rx_data()
2775 mapping = dma_map_single(&bp->pdev->dev, in bnx2_alloc_rx_data()
2777 bp->rx_buf_use_size, in bnx2_alloc_rx_data()
2779 if (dma_mapping_error(&bp->pdev->dev, mapping)) { in bnx2_alloc_rx_data()
2781 return -EIO; in bnx2_alloc_rx_data()
2784 rx_buf->data = data; in bnx2_alloc_rx_data()
2787 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_alloc_rx_data()
2788 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_data()
2790 rxr->rx_prod_bseq += bp->rx_buf_use_size; in bnx2_alloc_rx_data()
2798 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_phy_event_is_set()
2802 new_link_state = sblk->status_attn_bits & event; in bnx2_phy_event_is_set()
2803 old_link_state = sblk->status_attn_bits_ack & event; in bnx2_phy_event_is_set()
2818 spin_lock(&bp->phy_lock); in bnx2_phy_int()
2825 spin_unlock(&bp->phy_lock); in bnx2_phy_int()
2834 cons = READ_ONCE(*bnapi->hw_tx_cons_ptr); in bnx2_get_hw_tx_cons()
2844 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_tx_int()
2850 index = (bnapi - bp->bnx2_napi); in bnx2_tx_int()
2851 txq = netdev_get_tx_queue(bp->dev, index); in bnx2_tx_int()
2854 sw_cons = txr->tx_cons; in bnx2_tx_int()
2863 tx_buf = &txr->tx_buf_ring[sw_ring_cons]; in bnx2_tx_int()
2864 skb = tx_buf->skb; in bnx2_tx_int()
2867 prefetch(&skb->end); in bnx2_tx_int()
2870 if (tx_buf->is_gso) { in bnx2_tx_int()
2873 last_idx = sw_cons + tx_buf->nr_frags + 1; in bnx2_tx_int()
2874 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; in bnx2_tx_int()
2878 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { in bnx2_tx_int()
2883 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), in bnx2_tx_int()
2886 tx_buf->skb = NULL; in bnx2_tx_int()
2887 last = tx_buf->nr_frags; in bnx2_tx_int()
2894 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)]; in bnx2_tx_int()
2895 dma_unmap_page(&bp->pdev->dev, in bnx2_tx_int()
2897 skb_frag_size(&skb_shinfo(skb)->frags[i]), in bnx2_tx_int()
2903 tx_bytes += skb->len; in bnx2_tx_int()
2914 txr->hw_tx_cons = hw_cons; in bnx2_tx_int()
2915 txr->tx_cons = sw_cons; in bnx2_tx_int()
2925 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { in bnx2_tx_int()
2928 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) in bnx2_tx_int()
2944 u16 cons = rxr->rx_pg_cons; in bnx2_reuse_rx_skb_pages()
2946 cons_rx_pg = &rxr->rx_pg_ring[cons]; in bnx2_reuse_rx_skb_pages()
2957 shinfo->nr_frags--; in bnx2_reuse_rx_skb_pages()
2958 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]); in bnx2_reuse_rx_skb_pages()
2960 cons_rx_pg->page = page; in bnx2_reuse_rx_skb_pages()
2964 hw_prod = rxr->rx_pg_prod; in bnx2_reuse_rx_skb_pages()
2969 prod_rx_pg = &rxr->rx_pg_ring[prod]; in bnx2_reuse_rx_skb_pages()
2970 cons_rx_pg = &rxr->rx_pg_ring[cons]; in bnx2_reuse_rx_skb_pages()
2971 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)] in bnx2_reuse_rx_skb_pages()
2973 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)] in bnx2_reuse_rx_skb_pages()
2977 prod_rx_pg->page = cons_rx_pg->page; in bnx2_reuse_rx_skb_pages()
2978 cons_rx_pg->page = NULL; in bnx2_reuse_rx_skb_pages()
2982 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; in bnx2_reuse_rx_skb_pages()
2983 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; in bnx2_reuse_rx_skb_pages()
2989 rxr->rx_pg_prod = hw_prod; in bnx2_reuse_rx_skb_pages()
2990 rxr->rx_pg_cons = cons; in bnx2_reuse_rx_skb_pages()
3000 cons_rx_buf = &rxr->rx_buf_ring[cons]; in bnx2_reuse_rx_data()
3001 prod_rx_buf = &rxr->rx_buf_ring[prod]; in bnx2_reuse_rx_data()
3003 dma_sync_single_for_device(&bp->pdev->dev, in bnx2_reuse_rx_data()
3007 rxr->rx_prod_bseq += bp->rx_buf_use_size; in bnx2_reuse_rx_data()
3009 prod_rx_buf->data = data; in bnx2_reuse_rx_data()
3017 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)]; in bnx2_reuse_rx_data()
3018 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)]; in bnx2_reuse_rx_data()
3019 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; in bnx2_reuse_rx_data()
3020 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; in bnx2_reuse_rx_data()
3038 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; in bnx2_rx_skb()
3045 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, in bnx2_rx_skb()
3052 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET); in bnx2_rx_skb()
3059 u16 pg_cons = rxr->rx_pg_cons; in bnx2_rx_skb()
3060 u16 pg_prod = rxr->rx_pg_prod; in bnx2_rx_skb()
3062 frag_size = len + 4 - hdr_len; in bnx2_rx_skb()
3071 unsigned int tail = 4 - frag_len; in bnx2_rx_skb()
3073 rxr->rx_pg_cons = pg_cons; in bnx2_rx_skb()
3074 rxr->rx_pg_prod = pg_prod; in bnx2_rx_skb()
3076 pages - i); in bnx2_rx_skb()
3077 skb->len -= tail; in bnx2_rx_skb()
3079 skb->tail -= tail; in bnx2_rx_skb()
3082 &skb_shinfo(skb)->frags[i - 1]; in bnx2_rx_skb()
3084 skb->data_len -= tail; in bnx2_rx_skb()
3088 rx_pg = &rxr->rx_pg_ring[pg_cons]; in bnx2_rx_skb()
3094 if (i == pages - 1) in bnx2_rx_skb()
3095 frag_len -= 4; in bnx2_rx_skb()
3097 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); in bnx2_rx_skb()
3098 rx_pg->page = NULL; in bnx2_rx_skb()
3104 rxr->rx_pg_cons = pg_cons; in bnx2_rx_skb()
3105 rxr->rx_pg_prod = pg_prod; in bnx2_rx_skb()
3107 pages - i); in bnx2_rx_skb()
3111 dma_unmap_page(&bp->pdev->dev, mapping_old, in bnx2_rx_skb()
3114 frag_size -= frag_len; in bnx2_rx_skb()
3115 skb->data_len += frag_len; in bnx2_rx_skb()
3116 skb->truesize += PAGE_SIZE; in bnx2_rx_skb()
3117 skb->len += frag_len; in bnx2_rx_skb()
3122 rxr->rx_pg_prod = pg_prod; in bnx2_rx_skb()
3123 rxr->rx_pg_cons = pg_cons; in bnx2_rx_skb()
3133 cons = READ_ONCE(*bnapi->hw_rx_cons_ptr); in bnx2_get_hw_rx_cons()
3143 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_rx_int()
3152 sw_cons = rxr->rx_cons; in bnx2_rx_int()
3153 sw_prod = rxr->rx_prod; in bnx2_rx_int()
3171 rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; in bnx2_rx_int()
3172 data = rx_buf->data; in bnx2_rx_int()
3173 rx_buf->data = NULL; in bnx2_rx_int()
3180 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, in bnx2_rx_int()
3185 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx]; in bnx2_rx_int()
3186 prefetch(get_l2_fhdr(next_rx_buf->data)); in bnx2_rx_int()
3188 len = rx_hdr->l2_fhdr_pkt_len; in bnx2_rx_int()
3189 status = rx_hdr->l2_fhdr_status; in bnx2_rx_int()
3193 hdr_len = rx_hdr->l2_fhdr_ip_xsum; in bnx2_rx_int()
3195 } else if (len > bp->rx_jumbo_thresh) { in bnx2_rx_int()
3196 hdr_len = bp->rx_jumbo_thresh; in bnx2_rx_int()
3211 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; in bnx2_rx_int()
3218 len -= 4; in bnx2_rx_int()
3220 if (len <= bp->rx_copy_thresh) { in bnx2_rx_int()
3221 skb = netdev_alloc_skb(bp->dev, len + 6); in bnx2_rx_int()
3229 memcpy(skb->data, in bnx2_rx_int()
3230 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6, in bnx2_rx_int()
3245 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) in bnx2_rx_int()
3246 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag); in bnx2_rx_int()
3248 skb->protocol = eth_type_trans(skb, bp->dev); in bnx2_rx_int()
3250 if (len > (bp->dev->mtu + ETH_HLEN) && in bnx2_rx_int()
3251 skb->protocol != htons(0x8100) && in bnx2_rx_int()
3252 skb->protocol != htons(ETH_P_8021AD)) { in bnx2_rx_int()
3260 if ((bp->dev->features & NETIF_F_RXCSUM) && in bnx2_rx_int()
3266 skb->ip_summed = CHECKSUM_UNNECESSARY; in bnx2_rx_int()
3268 if ((bp->dev->features & NETIF_F_RXHASH) && in bnx2_rx_int()
3271 skb_set_hash(skb, rx_hdr->l2_fhdr_hash, in bnx2_rx_int()
3274 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); in bnx2_rx_int()
3275 napi_gro_receive(&bnapi->napi, skb); in bnx2_rx_int()
3291 rxr->rx_cons = sw_cons; in bnx2_rx_int()
3292 rxr->rx_prod = sw_prod; in bnx2_rx_int()
3295 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); in bnx2_rx_int()
3297 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod); in bnx2_rx_int()
3299 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); in bnx2_rx_int()
3305 /* MSI ISR - The only difference between this and the INTx ISR
3312 struct bnx2 *bp = bnapi->bp; in bnx2_msi()
3314 prefetch(bnapi->status_blk.msi); in bnx2_msi()
3320 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi()
3323 napi_schedule(&bnapi->napi); in bnx2_msi()
3332 struct bnx2 *bp = bnapi->bp; in bnx2_msi_1shot()
3334 prefetch(bnapi->status_blk.msi); in bnx2_msi_1shot()
3337 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi_1shot()
3340 napi_schedule(&bnapi->napi); in bnx2_msi_1shot()
3349 struct bnx2 *bp = bnapi->bp; in bnx2_interrupt()
3350 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_interrupt()
3358 if ((sblk->status_idx == bnapi->last_status_idx) && in bnx2_interrupt()
3373 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_interrupt()
3376 if (napi_schedule_prep(&bnapi->napi)) { in bnx2_interrupt()
3377 bnapi->last_status_idx = sblk->status_idx; in bnx2_interrupt()
3378 __napi_schedule(&bnapi->napi); in bnx2_interrupt()
3387 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_has_fast_work()
3388 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_has_fast_work()
3390 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || in bnx2_has_fast_work()
3391 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) in bnx2_has_fast_work()
3402 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_has_work()
3408 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) in bnx2_has_work()
3412 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != in bnx2_has_work()
3413 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) in bnx2_has_work()
3422 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_chk_missed_msi()
3430 if (bnapi->last_status_idx == bp->idle_chk_status_idx) { in bnx2_chk_missed_msi()
3434 bnx2_msi(bp->irq_tbl[0].vector, bnapi); in bnx2_chk_missed_msi()
3438 bp->idle_chk_status_idx = bnapi->last_status_idx; in bnx2_chk_missed_msi()
3446 if (!bnapi->cnic_present) in bnx2_poll_cnic()
3450 c_ops = rcu_dereference(bp->cnic_ops); in bnx2_poll_cnic()
3452 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, in bnx2_poll_cnic()
3453 bnapi->status_blk.msi); in bnx2_poll_cnic()
3460 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_poll_link()
3461 u32 status_attn_bits = sblk->status_attn_bits; in bnx2_poll_link()
3462 u32 status_attn_bits_ack = sblk->status_attn_bits_ack; in bnx2_poll_link()
3473 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); in bnx2_poll_link()
3481 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_poll_work()
3482 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_poll_work()
3484 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) in bnx2_poll_work()
3487 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) in bnx2_poll_work()
3488 work_done += bnx2_rx_int(bp, bnapi, budget - work_done); in bnx2_poll_work()
3496 struct bnx2 *bp = bnapi->bp; in bnx2_poll_msix()
3498 struct status_block_msix *sblk = bnapi->status_blk.msix; in bnx2_poll_msix()
3505 bnapi->last_status_idx = sblk->status_idx; in bnx2_poll_msix()
3511 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_poll_msix()
3513 bnapi->last_status_idx); in bnx2_poll_msix()
3523 struct bnx2 *bp = bnapi->bp; in bnx2_poll()
3525 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_poll()
3536 /* bnapi->last_status_idx is used below to tell the hw how in bnx2_poll()
3540 bnapi->last_status_idx = sblk->status_idx; in bnx2_poll()
3548 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { in bnx2_poll()
3551 bnapi->last_status_idx); in bnx2_poll()
3557 bnapi->last_status_idx); in bnx2_poll()
3561 bnapi->last_status_idx); in bnx2_poll()
3583 spin_lock_bh(&bp->phy_lock); in bnx2_set_rx_mode()
3585 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | in bnx2_set_rx_mode()
3588 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) && in bnx2_set_rx_mode()
3589 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) in bnx2_set_rx_mode()
3591 if (dev->flags & IFF_PROMISC) { in bnx2_set_rx_mode()
3597 else if (dev->flags & IFF_ALLMULTI) { in bnx2_set_rx_mode()
3614 crc = ether_crc_le(ETH_ALEN, ha->addr); in bnx2_set_rx_mode()
3633 } else if (!(dev->flags & IFF_PROMISC)) { in bnx2_set_rx_mode()
3637 bnx2_set_mac_addr(bp, ha->addr, in bnx2_set_rx_mode()
3646 if (rx_mode != bp->rx_mode) { in bnx2_set_rx_mode()
3647 bp->rx_mode = rx_mode; in bnx2_set_rx_mode()
3655 spin_unlock_bh(&bp->phy_lock); in bnx2_set_rx_mode()
3663 u32 offset = be32_to_cpu(section->offset); in check_fw_section()
3664 u32 len = be32_to_cpu(section->len); in check_fw_section()
3666 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) in check_fw_section()
3667 return -EINVAL; in check_fw_section()
3668 if ((non_empty && len == 0) || len > fw->size - offset || in check_fw_section()
3669 len & (alignment - 1)) in check_fw_section()
3670 return -EINVAL; in check_fw_section()
3678 if (check_fw_section(fw, &entry->text, 4, true) || in check_mips_fw_entry()
3679 check_fw_section(fw, &entry->data, 4, false) || in check_mips_fw_entry()
3680 check_fw_section(fw, &entry->rodata, 4, false)) in check_mips_fw_entry()
3681 return -EINVAL; in check_mips_fw_entry()
3687 if (bp->rv2p_firmware) { in bnx2_release_firmware()
3688 release_firmware(bp->mips_firmware); in bnx2_release_firmware()
3689 release_firmware(bp->rv2p_firmware); in bnx2_release_firmware()
3690 bp->rv2p_firmware = NULL; in bnx2_release_firmware()
3713 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); in bnx2_request_uncached_firmware()
3719 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); in bnx2_request_uncached_firmware()
3724 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; in bnx2_request_uncached_firmware()
3725 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; in bnx2_request_uncached_firmware()
3726 if (bp->mips_firmware->size < sizeof(*mips_fw) || in bnx2_request_uncached_firmware()
3727 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || in bnx2_request_uncached_firmware()
3728 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || in bnx2_request_uncached_firmware()
3729 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || in bnx2_request_uncached_firmware()
3730 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || in bnx2_request_uncached_firmware()
3731 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { in bnx2_request_uncached_firmware()
3733 rc = -EINVAL; in bnx2_request_uncached_firmware()
3736 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || in bnx2_request_uncached_firmware()
3737 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || in bnx2_request_uncached_firmware()
3738 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { in bnx2_request_uncached_firmware()
3740 rc = -EINVAL; in bnx2_request_uncached_firmware()
3747 release_firmware(bp->rv2p_firmware); in bnx2_request_uncached_firmware()
3748 bp->rv2p_firmware = NULL; in bnx2_request_uncached_firmware()
3750 release_firmware(bp->mips_firmware); in bnx2_request_uncached_firmware()
3756 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); in bnx2_request_firmware()
3780 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); in load_rv2p_fw()
3781 file_offset = be32_to_cpu(fw_entry->rv2p.offset); in load_rv2p_fw()
3783 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); in load_rv2p_fw()
3803 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); in load_rv2p_fw()
3807 loc = be32_to_cpu(fw_entry->fixup[i]); in load_rv2p_fw()
3809 code = be32_to_cpu(*(rv2p_code + loc - 1)); in load_rv2p_fw()
3820 /* Reset the processor, un-stall is done later. */ in load_rv2p_fw()
3841 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); in load_cpu_fw()
3842 val |= cpu_reg->mode_value_halt; in load_cpu_fw()
3843 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); in load_cpu_fw()
3844 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
3847 addr = be32_to_cpu(fw_entry->text.addr); in load_cpu_fw()
3848 len = be32_to_cpu(fw_entry->text.len); in load_cpu_fw()
3849 file_offset = be32_to_cpu(fw_entry->text.offset); in load_cpu_fw()
3850 data = (__be32 *)(bp->mips_firmware->data + file_offset); in load_cpu_fw()
3852 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3861 addr = be32_to_cpu(fw_entry->data.addr); in load_cpu_fw()
3862 len = be32_to_cpu(fw_entry->data.len); in load_cpu_fw()
3863 file_offset = be32_to_cpu(fw_entry->data.offset); in load_cpu_fw()
3864 data = (__be32 *)(bp->mips_firmware->data + file_offset); in load_cpu_fw()
3866 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3874 /* Load the Read-Only area. */ in load_cpu_fw()
3875 addr = be32_to_cpu(fw_entry->rodata.addr); in load_cpu_fw()
3876 len = be32_to_cpu(fw_entry->rodata.len); in load_cpu_fw()
3877 file_offset = be32_to_cpu(fw_entry->rodata.offset); in load_cpu_fw()
3878 data = (__be32 *)(bp->mips_firmware->data + file_offset); in load_cpu_fw()
3880 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3888 /* Clear the pre-fetch instruction. */ in load_cpu_fw()
3889 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); in load_cpu_fw()
3891 val = be32_to_cpu(fw_entry->start_addr); in load_cpu_fw()
3892 bnx2_reg_wr_ind(bp, cpu_reg->pc, val); in load_cpu_fw()
3895 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); in load_cpu_fw()
3896 val &= ~cpu_reg->mode_value_halt; in load_cpu_fw()
3897 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
3898 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); in load_cpu_fw()
3905 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; in bnx2_init_cpus()
3907 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; in bnx2_init_cpus()
3910 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); in bnx2_init_cpus()
3911 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); in bnx2_init_cpus()
3914 load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); in bnx2_init_cpus()
3917 load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); in bnx2_init_cpus()
3919 /* Initialize the TX Patch-up Processor. */ in bnx2_init_cpus()
3920 load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); in bnx2_init_cpus()
3923 load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); in bnx2_init_cpus()
3926 load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); in bnx2_init_cpus()
3935 if (bp->wol) { in bnx2_setup_wol()
3939 autoneg = bp->autoneg; in bnx2_setup_wol()
3940 advertising = bp->advertising; in bnx2_setup_wol()
3942 if (bp->phy_port == PORT_TP) { in bnx2_setup_wol()
3943 bp->autoneg = AUTONEG_SPEED; in bnx2_setup_wol()
3944 bp->advertising = ADVERTISED_10baseT_Half | in bnx2_setup_wol()
3951 spin_lock_bh(&bp->phy_lock); in bnx2_setup_wol()
3952 bnx2_setup_phy(bp, bp->phy_port); in bnx2_setup_wol()
3953 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_wol()
3955 bp->autoneg = autoneg; in bnx2_setup_wol()
3956 bp->advertising = advertising; in bnx2_setup_wol()
3958 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_setup_wol()
3967 if (bp->phy_port == PORT_TP) { in bnx2_setup_wol()
3971 if (bp->line_speed == SPEED_2500) in bnx2_setup_wol()
4004 if (!(bp->flags & BNX2_FLAG_NO_WOL)) { in bnx2_setup_wol()
4008 if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) { in bnx2_setup_wol()
4031 pci_enable_wake(bp->pdev, PCI_D0, false); in bnx2_set_power_state()
4032 pci_set_power_state(bp->pdev, PCI_D0); in bnx2_set_power_state()
4046 pci_wake_from_d3(bp->pdev, bp->wol); in bnx2_set_power_state()
4050 if (bp->wol) in bnx2_set_power_state()
4051 pci_set_power_state(bp->pdev, PCI_D3hot); in bnx2_set_power_state()
4055 if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) { in bnx2_set_power_state()
4067 pci_set_power_state(bp->pdev, PCI_D3hot); in bnx2_set_power_state()
4075 return -EINVAL; in bnx2_set_power_state()
4097 return -EBUSY; in bnx2_acquire_nvram_lock()
4120 return -EBUSY; in bnx2_release_nvram_lock()
4134 if (bp->flash_info->flags & BNX2_NV_WREN) { in bnx2_enable_nvram_write()
4150 return -EBUSY; in bnx2_enable_nvram_write()
4194 if (bp->flash_info->flags & BNX2_NV_BUFFERED) in bnx2_nvram_erase_page()
4223 return -EBUSY; in bnx2_nvram_erase_page()
4238 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { in bnx2_nvram_read_dword()
4239 offset = ((offset / bp->flash_info->page_size) << in bnx2_nvram_read_dword()
4240 bp->flash_info->page_bits) + in bnx2_nvram_read_dword()
4241 (offset % bp->flash_info->page_size); in bnx2_nvram_read_dword()
4267 return -EBUSY; in bnx2_nvram_read_dword()
4284 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { in bnx2_nvram_write_dword()
4285 offset = ((offset / bp->flash_info->page_size) << in bnx2_nvram_write_dword()
4286 bp->flash_info->page_bits) + in bnx2_nvram_write_dword()
4287 (offset % bp->flash_info->page_size); in bnx2_nvram_write_dword()
4312 return -EBUSY; in bnx2_nvram_write_dword()
4325 bp->flash_info = &flash_5709; in bnx2_init_nvram()
4340 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { in bnx2_init_nvram()
4341 bp->flash_info = flash; in bnx2_init_nvram()
4358 if ((val & mask) == (flash->strapping & mask)) { in bnx2_init_nvram()
4359 bp->flash_info = flash; in bnx2_init_nvram()
4369 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1); in bnx2_init_nvram()
4370 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2); in bnx2_init_nvram()
4371 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3); in bnx2_init_nvram()
4372 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1); in bnx2_init_nvram()
4384 bp->flash_info = NULL; in bnx2_init_nvram()
4386 return -ENODEV; in bnx2_init_nvram()
4393 bp->flash_size = val; in bnx2_init_nvram()
4395 bp->flash_size = bp->flash_info->total_size; in bnx2_init_nvram()
4405 u32 cmd_flags, offset32, len32, extra; in bnx2_nvram_read() local
4419 extra = 0; in bnx2_nvram_read()
4428 pre_len = 4 - (offset & 3); in bnx2_nvram_read()
4448 len32 -= pre_len; in bnx2_nvram_read()
4451 extra = 4 - (len32 & 3); in bnx2_nvram_read()
4466 memcpy(ret_buf, buf, 4 - extra); in bnx2_nvram_read()
4482 len32 -= 4; in bnx2_nvram_read()
4490 len32 -= 4; in bnx2_nvram_read()
4499 memcpy(ret_buf, buf, 4 - extra); in bnx2_nvram_read()
4534 align_end = 4 - (len32 & 3); in bnx2_nvram_write()
4536 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) in bnx2_nvram_write()
4543 return -ENOMEM; in bnx2_nvram_write()
4548 memcpy(align_buf + len32 - 4, end, 4); in bnx2_nvram_write()
4554 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4557 rc = -ENOMEM; in bnx2_nvram_write()
4570 page_start -= (page_start % bp->flash_info->page_size); in bnx2_nvram_write()
4572 page_end = page_start + bp->flash_info->page_size; in bnx2_nvram_write()
4587 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4591 * (non-buffer flash only) */ in bnx2_nvram_write()
4592 for (j = 0; j < bp->flash_info->page_size; j += 4) { in bnx2_nvram_write()
4593 if (j == (bp->flash_info->page_size - 4)) { in bnx2_nvram_write()
4608 /* Enable writes to flash interface (unlock write-protect) */ in bnx2_nvram_write()
4615 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4620 /* Re-enable the write again for the actual write */ in bnx2_nvram_write()
4638 if ((addr == page_end - 4) || in bnx2_nvram_write()
4639 ((bp->flash_info->flags & BNX2_NV_BUFFERED) && in bnx2_nvram_write()
4640 (addr == data_end - 4))) { in bnx2_nvram_write()
4656 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4660 if (addr == page_end-4) { in bnx2_nvram_write()
4673 /* Disable writes to flash interface (lock write-protect) */ in bnx2_nvram_write()
4681 written += data_end - data_start; in bnx2_nvram_write()
4695 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; in bnx2_init_fw_cap()
4696 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; in bnx2_init_fw_cap()
4698 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) in bnx2_init_fw_cap()
4699 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; in bnx2_init_fw_cap()
4706 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; in bnx2_init_fw_cap()
4710 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_init_fw_cap()
4714 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; in bnx2_init_fw_cap()
4718 bp->phy_port = PORT_FIBRE; in bnx2_init_fw_cap()
4720 bp->phy_port = PORT_TP; in bnx2_init_fw_cap()
4726 if (netif_running(bp->dev) && sig) in bnx2_init_fw_cap()
4837 return -EBUSY; in bnx2_reset_chip()
4845 return -ENODEV; in bnx2_reset_chip()
4853 spin_lock_bh(&bp->phy_lock); in bnx2_reset_chip()
4854 old_port = bp->phy_port; in bnx2_reset_chip()
4856 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && in bnx2_reset_chip()
4857 old_port != bp->phy_port) in bnx2_reset_chip()
4859 spin_unlock_bh(&bp->phy_lock); in bnx2_reset_chip()
4870 if (bp->flags & BNX2_FLAG_USING_MSIX) { in bnx2_reset_chip()
4900 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) in bnx2_init_chip()
4905 !(bp->flags & BNX2_FLAG_PCIX)) in bnx2_init_chip()
4916 if (bp->flags & BNX2_FLAG_PCIX) { in bnx2_init_chip()
4919 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, in bnx2_init_chip()
4921 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, in bnx2_init_chip()
4943 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_init_chip()
4960 val = (BNX2_PAGE_BITS - 8) << 24; in bnx2_init_chip()
4966 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; in bnx2_init_chip()
4969 val = bp->mac_addr[0] + in bnx2_init_chip()
4970 (bp->mac_addr[1] << 8) + in bnx2_init_chip()
4971 (bp->mac_addr[2] << 16) + in bnx2_init_chip()
4972 bp->mac_addr[3] + in bnx2_init_chip()
4973 (bp->mac_addr[4] << 8) + in bnx2_init_chip()
4974 (bp->mac_addr[5] << 16); in bnx2_init_chip()
4978 mtu = bp->dev->mtu; in bnx2_init_chip()
4991 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); in bnx2_init_chip()
4993 bp->bnx2_napi[i].last_status_idx = 0; in bnx2_init_chip()
4995 bp->idle_chk_status_idx = 0xffff; in bnx2_init_chip()
5001 (u64) bp->status_blk_mapping & 0xffffffff); in bnx2_init_chip()
5002 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); in bnx2_init_chip()
5005 (u64) bp->stats_blk_mapping & 0xffffffff); in bnx2_init_chip()
5007 (u64) bp->stats_blk_mapping >> 32); in bnx2_init_chip()
5010 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); in bnx2_init_chip()
5013 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); in bnx2_init_chip()
5016 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); in bnx2_init_chip()
5018 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); in bnx2_init_chip()
5020 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); in bnx2_init_chip()
5023 (bp->com_ticks_int << 16) | bp->com_ticks); in bnx2_init_chip()
5026 (bp->cmd_ticks_int << 16) | bp->cmd_ticks); in bnx2_init_chip()
5028 if (bp->flags & BNX2_FLAG_BROKEN_STATS) in bnx2_init_chip()
5031 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); in bnx2_init_chip()
5041 if (bp->flags & BNX2_FLAG_USING_MSIX) { in bnx2_init_chip()
5048 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) in bnx2_init_chip()
5053 if (bp->rx_ticks < 25) in bnx2_init_chip()
5058 for (i = 1; i < bp->irq_nvecs; i++) { in bnx2_init_chip()
5059 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + in bnx2_init_chip()
5068 (bp->tx_quick_cons_trip_int << 16) | in bnx2_init_chip()
5069 bp->tx_quick_cons_trip); in bnx2_init_chip()
5072 (bp->tx_ticks_int << 16) | bp->tx_ticks); in bnx2_init_chip()
5075 (bp->rx_quick_cons_trip_int << 16) | in bnx2_init_chip()
5076 bp->rx_quick_cons_trip); in bnx2_init_chip()
5079 (bp->rx_ticks_int << 16) | bp->rx_ticks); in bnx2_init_chip()
5088 bnx2_set_rx_mode(bp->dev); in bnx2_init_chip()
5103 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); in bnx2_init_chip()
5117 bnapi = &bp->bnx2_napi[i]; in bnx2_clear_ring_states()
5118 txr = &bnapi->tx_ring; in bnx2_clear_ring_states()
5119 rxr = &bnapi->rx_ring; in bnx2_clear_ring_states()
5121 txr->tx_cons = 0; in bnx2_clear_ring_states()
5122 txr->hw_tx_cons = 0; in bnx2_clear_ring_states()
5123 rxr->rx_prod_bseq = 0; in bnx2_clear_ring_states()
5124 rxr->rx_prod = 0; in bnx2_clear_ring_states()
5125 rxr->rx_cons = 0; in bnx2_clear_ring_states()
5126 rxr->rx_pg_prod = 0; in bnx2_clear_ring_states()
5127 rxr->rx_pg_cons = 0; in bnx2_clear_ring_states()
5154 val = (u64) txr->tx_desc_mapping >> 32; in bnx2_init_tx_context()
5157 val = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_context()
5169 bnapi = &bp->bnx2_napi[ring_num]; in bnx2_init_tx_ring()
5170 txr = &bnapi->tx_ring; in bnx2_init_tx_ring()
5175 cid = TX_TSS_CID + ring_num - 1; in bnx2_init_tx_ring()
5177 bp->tx_wake_thresh = bp->tx_ring_size / 2; in bnx2_init_tx_ring()
5179 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT]; in bnx2_init_tx_ring()
5181 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; in bnx2_init_tx_ring()
5182 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_ring()
5184 txr->tx_prod = 0; in bnx2_init_tx_ring()
5185 txr->tx_prod_bseq = 0; in bnx2_init_tx_ring()
5187 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; in bnx2_init_tx_ring()
5188 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; in bnx2_init_tx_ring()
5205 rxbd->rx_bd_len = buf_size; in bnx2_init_rxbd_rings()
5206 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; in bnx2_init_rxbd_rings()
5208 if (i == (num_rings - 1)) in bnx2_init_rxbd_rings()
5212 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; in bnx2_init_rxbd_rings()
5213 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; in bnx2_init_rxbd_rings()
5223 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; in bnx2_init_rx_ring()
5224 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_init_rx_ring()
5229 cid = RX_RSS_CID + ring_num - 1; in bnx2_init_rx_ring()
5233 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, in bnx2_init_rx_ring()
5234 bp->rx_buf_use_size, bp->rx_max_ring); in bnx2_init_rx_ring()
5244 if (bp->rx_pg_ring_size) { in bnx2_init_rx_ring()
5245 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, in bnx2_init_rx_ring()
5246 rxr->rx_pg_desc_mapping, in bnx2_init_rx_ring()
5247 PAGE_SIZE, bp->rx_max_pg_ring); in bnx2_init_rx_ring()
5248 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; in bnx2_init_rx_ring()
5251 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); in bnx2_init_rx_ring()
5253 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5256 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5263 val = (u64) rxr->rx_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5266 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5269 ring_prod = prod = rxr->rx_pg_prod; in bnx2_init_rx_ring()
5270 for (i = 0; i < bp->rx_pg_ring_size; i++) { in bnx2_init_rx_ring()
5272 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n", in bnx2_init_rx_ring()
5273 ring_num, i, bp->rx_pg_ring_size); in bnx2_init_rx_ring()
5279 rxr->rx_pg_prod = prod; in bnx2_init_rx_ring()
5281 ring_prod = prod = rxr->rx_prod; in bnx2_init_rx_ring()
5282 for (i = 0; i < bp->rx_ring_size; i++) { in bnx2_init_rx_ring()
5284 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n", in bnx2_init_rx_ring()
5285 ring_num, i, bp->rx_ring_size); in bnx2_init_rx_ring()
5291 rxr->rx_prod = prod; in bnx2_init_rx_ring()
5293 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; in bnx2_init_rx_ring()
5294 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; in bnx2_init_rx_ring()
5295 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; in bnx2_init_rx_ring()
5297 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); in bnx2_init_rx_ring()
5298 BNX2_WR16(bp, rxr->rx_bidx_addr, prod); in bnx2_init_rx_ring()
5300 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); in bnx2_init_rx_ring()
5312 for (i = 0; i < bp->num_tx_rings; i++) in bnx2_init_all_rings()
5315 if (bp->num_tx_rings > 1) in bnx2_init_all_rings()
5316 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | in bnx2_init_all_rings()
5322 for (i = 0; i < bp->num_rx_rings; i++) in bnx2_init_all_rings()
5325 if (bp->num_rx_rings > 1) { in bnx2_init_all_rings()
5331 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; in bnx2_init_all_rings()
5355 ring_size -= BNX2_MAX_RX_DESC_CNT; in bnx2_find_max_ring()
5375 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; in bnx2_set_rx_ring_size()
5380 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; in bnx2_set_rx_ring_size()
5381 bp->rx_pg_ring_size = 0; in bnx2_set_rx_ring_size()
5382 bp->rx_max_pg_ring = 0; in bnx2_set_rx_ring_size()
5383 bp->rx_max_pg_ring_idx = 0; in bnx2_set_rx_ring_size()
5384 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { in bnx2_set_rx_ring_size()
5385 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; in bnx2_set_rx_ring_size()
5391 bp->rx_pg_ring_size = jumbo_size; in bnx2_set_rx_ring_size()
5392 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, in bnx2_set_rx_ring_size()
5394 bp->rx_max_pg_ring_idx = in bnx2_set_rx_ring_size()
5395 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1; in bnx2_set_rx_ring_size()
5397 bp->rx_copy_thresh = 0; in bnx2_set_rx_ring_size()
5400 bp->rx_buf_use_size = rx_size; in bnx2_set_rx_ring_size()
5402 bp->rx_buf_size = kmalloc_size_roundup( in bnx2_set_rx_ring_size()
5403 SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) + in bnx2_set_rx_ring_size()
5405 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; in bnx2_set_rx_ring_size()
5406 bp->rx_ring_size = size; in bnx2_set_rx_ring_size()
5407 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS); in bnx2_set_rx_ring_size()
5408 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1; in bnx2_set_rx_ring_size()
5416 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_skbs()
5417 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_tx_skbs()
5418 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_free_tx_skbs()
5421 if (!txr->tx_buf_ring) in bnx2_free_tx_skbs()
5425 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; in bnx2_free_tx_skbs()
5426 struct sk_buff *skb = tx_buf->skb; in bnx2_free_tx_skbs()
5434 dma_unmap_single(&bp->pdev->dev, in bnx2_free_tx_skbs()
5439 tx_buf->skb = NULL; in bnx2_free_tx_skbs()
5441 last = tx_buf->nr_frags; in bnx2_free_tx_skbs()
5444 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)]; in bnx2_free_tx_skbs()
5445 dma_unmap_page(&bp->pdev->dev, in bnx2_free_tx_skbs()
5447 skb_frag_size(&skb_shinfo(skb)->frags[k]), in bnx2_free_tx_skbs()
5452 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); in bnx2_free_tx_skbs()
5461 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_skbs()
5462 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_rx_skbs()
5463 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_free_rx_skbs()
5466 if (!rxr->rx_buf_ring) in bnx2_free_rx_skbs()
5469 for (j = 0; j < bp->rx_max_ring_idx; j++) { in bnx2_free_rx_skbs()
5470 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j]; in bnx2_free_rx_skbs()
5471 u8 *data = rx_buf->data; in bnx2_free_rx_skbs()
5476 dma_unmap_single(&bp->pdev->dev, in bnx2_free_rx_skbs()
5478 bp->rx_buf_use_size, in bnx2_free_rx_skbs()
5481 rx_buf->data = NULL; in bnx2_free_rx_skbs()
5485 for (j = 0; j < bp->rx_max_pg_ring_idx; j++) in bnx2_free_rx_skbs()
5522 spin_lock_bh(&bp->phy_lock); in bnx2_init_nic()
5525 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_init_nic()
5527 spin_unlock_bh(&bp->phy_lock); in bnx2_init_nic()
5536 if (bp->flags & BNX2_FLAG_NO_WOL) in bnx2_shutdown_chip()
5538 else if (bp->wol) in bnx2_shutdown_chip()
5682 save_val = readl(bp->regview + offset); in bnx2_test_registers()
5684 writel(0, bp->regview + offset); in bnx2_test_registers()
5686 val = readl(bp->regview + offset); in bnx2_test_registers()
5695 writel(0xffffffff, bp->regview + offset); in bnx2_test_registers()
5697 val = readl(bp->regview + offset); in bnx2_test_registers()
5706 writel(save_val, bp->regview + offset); in bnx2_test_registers()
5710 writel(save_val, bp->regview + offset); in bnx2_test_registers()
5711 ret = -ENODEV; in bnx2_test_registers()
5733 return -ENODEV; in bnx2_do_mem_test()
5797 int ret = -ENODEV; in bnx2_run_loopback()
5798 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; in bnx2_run_loopback()
5804 txr = &tx_napi->tx_ring; in bnx2_run_loopback()
5805 rxr = &bnapi->rx_ring; in bnx2_run_loopback()
5807 bp->loopback = MAC_LOOPBACK; in bnx2_run_loopback()
5811 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_run_loopback()
5814 bp->loopback = PHY_LOOPBACK; in bnx2_run_loopback()
5818 return -EINVAL; in bnx2_run_loopback()
5820 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); in bnx2_run_loopback()
5821 skb = netdev_alloc_skb(bp->dev, pkt_size); in bnx2_run_loopback()
5823 return -ENOMEM; in bnx2_run_loopback()
5825 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); in bnx2_run_loopback()
5830 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, in bnx2_run_loopback()
5832 if (dma_mapping_error(&bp->pdev->dev, map)) { in bnx2_run_loopback()
5834 return -EIO; in bnx2_run_loopback()
5838 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); in bnx2_run_loopback()
5847 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)]; in bnx2_run_loopback()
5849 txbd->tx_bd_haddr_hi = (u64) map >> 32; in bnx2_run_loopback()
5850 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; in bnx2_run_loopback()
5851 txbd->tx_bd_mss_nbytes = pkt_size; in bnx2_run_loopback()
5852 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; in bnx2_run_loopback()
5855 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod); in bnx2_run_loopback()
5856 txr->tx_prod_bseq += pkt_size; in bnx2_run_loopback()
5858 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); in bnx2_run_loopback()
5859 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); in bnx2_run_loopback()
5864 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); in bnx2_run_loopback()
5870 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); in bnx2_run_loopback()
5873 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) in bnx2_run_loopback()
5881 rx_buf = &rxr->rx_buf_ring[rx_start_idx]; in bnx2_run_loopback()
5882 data = rx_buf->data; in bnx2_run_loopback()
5887 dma_sync_single_for_cpu(&bp->pdev->dev, in bnx2_run_loopback()
5889 bp->rx_buf_use_size, DMA_FROM_DEVICE); in bnx2_run_loopback()
5891 if (rx_hdr->l2_fhdr_status & in bnx2_run_loopback()
5901 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { in bnx2_run_loopback()
5914 bp->loopback = 0; in bnx2_run_loopback()
5928 if (!netif_running(bp->dev)) in bnx2_test_loopback()
5932 spin_lock_bh(&bp->phy_lock); in bnx2_test_loopback()
5934 spin_unlock_bh(&bp->phy_lock); in bnx2_test_loopback()
5958 rc = -ENODEV; in bnx2_test_nvram()
5967 rc = -ENODEV; in bnx2_test_nvram()
5973 rc = -ENODEV; in bnx2_test_nvram()
5985 if (!netif_running(bp->dev)) in bnx2_test_link()
5986 return -ENODEV; in bnx2_test_link()
5988 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_test_link()
5989 if (bp->link_up) in bnx2_test_link()
5991 return -ENODEV; in bnx2_test_link()
5993 spin_lock_bh(&bp->phy_lock); in bnx2_test_link()
5995 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_test_link()
5996 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_test_link()
5998 spin_unlock_bh(&bp->phy_lock); in bnx2_test_link()
6003 return -ENODEV; in bnx2_test_link()
6012 if (!netif_running(bp->dev)) in bnx2_test_intr()
6013 return -ENODEV; in bnx2_test_intr()
6017 /* This register is not touched during run-time. */ in bnx2_test_intr()
6018 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); in bnx2_test_intr()
6033 return -ENODEV; in bnx2_test_intr()
6042 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) in bnx2_5706_serdes_has_link()
6073 spin_lock(&bp->phy_lock); in bnx2_5706_serdes_timer()
6074 if (bp->serdes_an_pending) { in bnx2_5706_serdes_timer()
6075 bp->serdes_an_pending--; in bnx2_5706_serdes_timer()
6077 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5706_serdes_timer()
6080 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5706_serdes_timer()
6082 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5706_serdes_timer()
6088 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6089 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_5706_serdes_timer()
6093 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && in bnx2_5706_serdes_timer()
6094 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { in bnx2_5706_serdes_timer()
6102 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5706_serdes_timer()
6104 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6106 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_5706_serdes_timer()
6109 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5706_serdes_timer()
6118 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { in bnx2_5706_serdes_timer()
6119 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { in bnx2_5706_serdes_timer()
6121 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; in bnx2_5706_serdes_timer()
6124 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) in bnx2_5706_serdes_timer()
6127 spin_unlock(&bp->phy_lock); in bnx2_5706_serdes_timer()
6133 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_5708_serdes_timer()
6136 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { in bnx2_5708_serdes_timer()
6137 bp->serdes_an_pending = 0; in bnx2_5708_serdes_timer()
6141 spin_lock(&bp->phy_lock); in bnx2_5708_serdes_timer()
6142 if (bp->serdes_an_pending) in bnx2_5708_serdes_timer()
6143 bp->serdes_an_pending--; in bnx2_5708_serdes_timer()
6144 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5708_serdes_timer()
6147 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5708_serdes_timer()
6150 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; in bnx2_5708_serdes_timer()
6153 bp->serdes_an_pending = 2; in bnx2_5708_serdes_timer()
6154 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5708_serdes_timer()
6158 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5708_serdes_timer()
6160 spin_unlock(&bp->phy_lock); in bnx2_5708_serdes_timer()
6168 if (!netif_running(bp->dev)) in bnx2_timer()
6171 if (atomic_read(&bp->intr_sem) != 0) in bnx2_timer()
6174 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == in bnx2_timer()
6180 bp->stats_blk->stat_FwRxDrop = in bnx2_timer()
6184 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) in bnx2_timer()
6185 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | in bnx2_timer()
6188 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_timer()
6196 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_timer()
6206 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) in bnx2_request_irq()
6211 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_request_irq()
6212 irq = &bp->irq_tbl[i]; in bnx2_request_irq()
6213 rc = request_irq(irq->vector, irq->handler, flags, irq->name, in bnx2_request_irq()
6214 &bp->bnx2_napi[i]); in bnx2_request_irq()
6217 irq->requested = 1; in bnx2_request_irq()
6228 for (i = 0; i < bp->irq_nvecs; i++) { in __bnx2_free_irq()
6229 irq = &bp->irq_tbl[i]; in __bnx2_free_irq()
6230 if (irq->requested) in __bnx2_free_irq()
6231 free_irq(irq->vector, &bp->bnx2_napi[i]); in __bnx2_free_irq()
6232 irq->requested = 0; in __bnx2_free_irq()
6241 if (bp->flags & BNX2_FLAG_USING_MSI) in bnx2_free_irq()
6242 pci_disable_msi(bp->pdev); in bnx2_free_irq()
6243 else if (bp->flags & BNX2_FLAG_USING_MSIX) in bnx2_free_irq()
6244 pci_disable_msix(bp->pdev); in bnx2_free_irq()
6246 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); in bnx2_free_irq()
6254 struct net_device *dev = bp->dev; in bnx2_enable_msix()
6255 const int len = sizeof(bp->irq_tbl[0].name); in bnx2_enable_msix()
6258 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); in bnx2_enable_msix()
6262 /* Need to flush the previous three writes to ensure MSI-X in bnx2_enable_msix()
6275 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, in bnx2_enable_msix()
6282 msix_vecs--; in bnx2_enable_msix()
6284 bp->irq_nvecs = msix_vecs; in bnx2_enable_msix()
6285 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; in bnx2_enable_msix()
6287 bp->irq_tbl[i].vector = msix_ent[i].vector; in bnx2_enable_msix()
6288 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); in bnx2_enable_msix()
6289 bp->irq_tbl[i].handler = bnx2_msi_1shot; in bnx2_enable_msix()
6299 if (!bp->num_req_rx_rings) in bnx2_setup_int_mode()
6300 msix_vecs = max(cpus + 1, bp->num_req_tx_rings); in bnx2_setup_int_mode()
6301 else if (!bp->num_req_tx_rings) in bnx2_setup_int_mode()
6302 msix_vecs = max(cpus, bp->num_req_rx_rings); in bnx2_setup_int_mode()
6304 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings); in bnx2_setup_int_mode()
6308 bp->irq_tbl[0].handler = bnx2_interrupt; in bnx2_setup_int_mode()
6309 strcpy(bp->irq_tbl[0].name, bp->dev->name); in bnx2_setup_int_mode()
6310 bp->irq_nvecs = 1; in bnx2_setup_int_mode()
6311 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6313 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) in bnx2_setup_int_mode()
6316 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && in bnx2_setup_int_mode()
6317 !(bp->flags & BNX2_FLAG_USING_MSIX)) { in bnx2_setup_int_mode()
6318 if (pci_enable_msi(bp->pdev) == 0) { in bnx2_setup_int_mode()
6319 bp->flags |= BNX2_FLAG_USING_MSI; in bnx2_setup_int_mode()
6321 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; in bnx2_setup_int_mode()
6322 bp->irq_tbl[0].handler = bnx2_msi_1shot; in bnx2_setup_int_mode()
6324 bp->irq_tbl[0].handler = bnx2_msi; in bnx2_setup_int_mode()
6326 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6330 if (!bp->num_req_tx_rings) in bnx2_setup_int_mode()
6331 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); in bnx2_setup_int_mode()
6333 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings); in bnx2_setup_int_mode()
6335 if (!bp->num_req_rx_rings) in bnx2_setup_int_mode()
6336 bp->num_rx_rings = bp->irq_nvecs; in bnx2_setup_int_mode()
6338 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings); in bnx2_setup_int_mode()
6340 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings); in bnx2_setup_int_mode()
6342 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings); in bnx2_setup_int_mode()
6377 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_open()
6379 atomic_set(&bp->intr_sem, 0); in bnx2_open()
6381 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); in bnx2_open()
6385 if (bp->flags & BNX2_FLAG_USING_MSI) { in bnx2_open()
6390 …netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report … in bnx2_open()
6403 del_timer_sync(&bp->timer); in bnx2_open()
6409 if (bp->flags & BNX2_FLAG_USING_MSI) in bnx2_open()
6411 else if (bp->flags & BNX2_FLAG_USING_MSIX) in bnx2_open()
6436 if (!netif_running(bp->dev)) { in bnx2_reset_task()
6443 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd); in bnx2_reset_task()
6446 pci_restore_state(bp->pdev); in bnx2_reset_task()
6447 pci_save_state(bp->pdev); in bnx2_reset_task()
6451 netdev_err(bp->dev, "failed to reset NIC, closing\n"); in bnx2_reset_task()
6453 dev_close(bp->dev); in bnx2_reset_task()
6458 atomic_set(&bp->intr_sem, 1); in bnx2_reset_task()
6470 struct net_device *dev = bp->dev; in bnx2_dump_ftq()
6491 netdev_err(dev, "<--- start FTQ dump --->\n"); in bnx2_dump_ftq()
6506 netdev_err(dev, "<--- end FTQ dump --->\n"); in bnx2_dump_ftq()
6507 netdev_err(dev, "<--- start TBDC dump --->\n"); in bnx2_dump_ftq()
6529 netdev_err(dev, "<--- end TBDC dump --->\n"); in bnx2_dump_ftq()
6535 struct net_device *dev = bp->dev; in bnx2_dump_state()
6538 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1); in bnx2_dump_state()
6540 atomic_read(&bp->intr_sem), val1); in bnx2_dump_state()
6541 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1); in bnx2_dump_state()
6542 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); in bnx2_dump_state()
6551 if (bp->flags & BNX2_FLAG_USING_MSIX) in bnx2_dump_state()
6566 schedule_work(&bp->reset_task); in bnx2_tx_timeout()
6589 bnapi = &bp->bnx2_napi[i]; in bnx2_start_xmit()
6590 txr = &bnapi->tx_ring; in bnx2_start_xmit()
6594 (skb_shinfo(skb)->nr_frags + 1))) { in bnx2_start_xmit()
6601 prod = txr->tx_prod; in bnx2_start_xmit()
6605 if (skb->ip_summed == CHECKSUM_PARTIAL) { in bnx2_start_xmit()
6614 if ((mss = skb_shinfo(skb)->gso_size)) { in bnx2_start_xmit()
6622 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { in bnx2_start_xmit()
6623 u32 tcp_off = skb_transport_offset(skb) - in bnx2_start_xmit()
6624 sizeof(struct ipv6hdr) - ETH_HLEN; in bnx2_start_xmit()
6640 if (tcp_opt_len || (iph->ihl > 5)) { in bnx2_start_xmit()
6641 vlan_tag_flags |= ((iph->ihl - 5) + in bnx2_start_xmit()
6648 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, in bnx2_start_xmit()
6650 if (dma_mapping_error(&bp->pdev->dev, mapping)) { in bnx2_start_xmit()
6655 tx_buf = &txr->tx_buf_ring[ring_prod]; in bnx2_start_xmit()
6656 tx_buf->skb = skb; in bnx2_start_xmit()
6659 txbd = &txr->tx_desc_ring[ring_prod]; in bnx2_start_xmit()
6661 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_start_xmit()
6662 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6663 txbd->tx_bd_mss_nbytes = len | (mss << 16); in bnx2_start_xmit()
6664 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; in bnx2_start_xmit()
6666 last_frag = skb_shinfo(skb)->nr_frags; in bnx2_start_xmit()
6667 tx_buf->nr_frags = last_frag; in bnx2_start_xmit()
6668 tx_buf->is_gso = skb_is_gso(skb); in bnx2_start_xmit()
6671 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in bnx2_start_xmit()
6675 txbd = &txr->tx_desc_ring[ring_prod]; in bnx2_start_xmit()
6678 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, in bnx2_start_xmit()
6680 if (dma_mapping_error(&bp->pdev->dev, mapping)) in bnx2_start_xmit()
6682 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, in bnx2_start_xmit()
6685 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_start_xmit()
6686 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6687 txbd->tx_bd_mss_nbytes = len | (mss << 16); in bnx2_start_xmit()
6688 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; in bnx2_start_xmit()
6691 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; in bnx2_start_xmit()
6696 netdev_tx_sent_queue(txq, skb->len); in bnx2_start_xmit()
6699 txr->tx_prod_bseq += skb->len; in bnx2_start_xmit()
6701 BNX2_WR16(bp, txr->tx_bidx_addr, prod); in bnx2_start_xmit()
6702 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); in bnx2_start_xmit()
6704 txr->tx_prod = prod; in bnx2_start_xmit()
6715 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) in bnx2_start_xmit()
6725 prod = txr->tx_prod; in bnx2_start_xmit()
6727 tx_buf = &txr->tx_buf_ring[ring_prod]; in bnx2_start_xmit()
6728 tx_buf->skb = NULL; in bnx2_start_xmit()
6729 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), in bnx2_start_xmit()
6736 tx_buf = &txr->tx_buf_ring[ring_prod]; in bnx2_start_xmit()
6737 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), in bnx2_start_xmit()
6738 skb_frag_size(&skb_shinfo(skb)->frags[i]), in bnx2_start_xmit()
6755 del_timer_sync(&bp->timer); in bnx2_close()
6761 bp->link_up = 0; in bnx2_close()
6762 netif_carrier_off(bp->dev); in bnx2_close()
6769 u32 *hw_stats = (u32 *) bp->stats_blk; in bnx2_save_stats()
6770 u32 *temp_stats = (u32 *) bp->temp_stats_blk; in bnx2_save_stats()
6773 /* The 1st 10 counters are 64-bit counters */ in bnx2_save_stats()
6794 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6795 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6798 (unsigned long) (bp->stats_blk->ctr + \
6799 bp->temp_stats_blk->ctr)
6806 if (!bp->stats_blk) in bnx2_get_stats64()
6809 net_stats->rx_packets = in bnx2_get_stats64()
6814 net_stats->tx_packets = in bnx2_get_stats64()
6819 net_stats->rx_bytes = in bnx2_get_stats64()
6822 net_stats->tx_bytes = in bnx2_get_stats64()
6825 net_stats->multicast = in bnx2_get_stats64()
6828 net_stats->collisions = in bnx2_get_stats64()
6831 net_stats->rx_length_errors = in bnx2_get_stats64()
6835 net_stats->rx_over_errors = in bnx2_get_stats64()
6839 net_stats->rx_frame_errors = in bnx2_get_stats64()
6842 net_stats->rx_crc_errors = in bnx2_get_stats64()
6845 net_stats->rx_errors = net_stats->rx_length_errors + in bnx2_get_stats64()
6846 net_stats->rx_over_errors + net_stats->rx_frame_errors + in bnx2_get_stats64()
6847 net_stats->rx_crc_errors; in bnx2_get_stats64()
6849 net_stats->tx_aborted_errors = in bnx2_get_stats64()
6855 net_stats->tx_carrier_errors = 0; in bnx2_get_stats64()
6857 net_stats->tx_carrier_errors = in bnx2_get_stats64()
6861 net_stats->tx_errors = in bnx2_get_stats64()
6863 net_stats->tx_aborted_errors + in bnx2_get_stats64()
6864 net_stats->tx_carrier_errors; in bnx2_get_stats64()
6866 net_stats->rx_missed_errors = in bnx2_get_stats64()
6884 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_get_link_ksettings()
6887 } else if (bp->phy_port == PORT_FIBRE) in bnx2_get_link_ksettings()
6895 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) in bnx2_get_link_ksettings()
6907 spin_lock_bh(&bp->phy_lock); in bnx2_get_link_ksettings()
6908 cmd->base.port = bp->phy_port; in bnx2_get_link_ksettings()
6909 advertising = bp->advertising; in bnx2_get_link_ksettings()
6911 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_get_link_ksettings()
6912 cmd->base.autoneg = AUTONEG_ENABLE; in bnx2_get_link_ksettings()
6914 cmd->base.autoneg = AUTONEG_DISABLE; in bnx2_get_link_ksettings()
6918 cmd->base.speed = bp->line_speed; in bnx2_get_link_ksettings()
6919 cmd->base.duplex = bp->duplex; in bnx2_get_link_ksettings()
6920 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) { in bnx2_get_link_ksettings()
6921 if (bp->phy_flags & BNX2_PHY_FLAG_MDIX) in bnx2_get_link_ksettings()
6922 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in bnx2_get_link_ksettings()
6924 cmd->base.eth_tp_mdix = ETH_TP_MDI; in bnx2_get_link_ksettings()
6928 cmd->base.speed = SPEED_UNKNOWN; in bnx2_get_link_ksettings()
6929 cmd->base.duplex = DUPLEX_UNKNOWN; in bnx2_get_link_ksettings()
6931 spin_unlock_bh(&bp->phy_lock); in bnx2_get_link_ksettings()
6933 cmd->base.phy_address = bp->phy_addr; in bnx2_get_link_ksettings()
6935 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in bnx2_get_link_ksettings()
6937 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in bnx2_get_link_ksettings()
6948 u8 autoneg = bp->autoneg; in bnx2_set_link_ksettings()
6949 u8 req_duplex = bp->req_duplex; in bnx2_set_link_ksettings()
6950 u16 req_line_speed = bp->req_line_speed; in bnx2_set_link_ksettings()
6951 u32 advertising = bp->advertising; in bnx2_set_link_ksettings()
6952 int err = -EINVAL; in bnx2_set_link_ksettings()
6954 spin_lock_bh(&bp->phy_lock); in bnx2_set_link_ksettings()
6956 if (cmd->base.port != PORT_TP && cmd->base.port != PORT_FIBRE) in bnx2_set_link_ksettings()
6959 if (cmd->base.port != bp->phy_port && in bnx2_set_link_ksettings()
6960 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) in bnx2_set_link_ksettings()
6966 if (!netif_running(dev) && cmd->base.port != bp->phy_port) in bnx2_set_link_ksettings()
6969 if (cmd->base.autoneg == AUTONEG_ENABLE) { in bnx2_set_link_ksettings()
6973 &advertising, cmd->link_modes.advertising); in bnx2_set_link_ksettings()
6975 if (cmd->base.port == PORT_TP) { in bnx2_set_link_ksettings()
6987 u32 speed = cmd->base.speed; in bnx2_set_link_ksettings()
6989 if (cmd->base.port == PORT_FIBRE) { in bnx2_set_link_ksettings()
6992 (cmd->base.duplex != DUPLEX_FULL)) in bnx2_set_link_ksettings()
6996 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_set_link_ksettings()
7003 req_duplex = cmd->base.duplex; in bnx2_set_link_ksettings()
7007 bp->autoneg = autoneg; in bnx2_set_link_ksettings()
7008 bp->advertising = advertising; in bnx2_set_link_ksettings()
7009 bp->req_line_speed = req_line_speed; in bnx2_set_link_ksettings()
7010 bp->req_duplex = req_duplex; in bnx2_set_link_ksettings()
7017 err = bnx2_setup_phy(bp, cmd->base.port); in bnx2_set_link_ksettings()
7020 spin_unlock_bh(&bp->phy_lock); in bnx2_set_link_ksettings()
7030 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in bnx2_get_drvinfo()
7031 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); in bnx2_get_drvinfo()
7032 strscpy(info->fw_version, bp->fw_version, sizeof(info->fw_version)); in bnx2_get_drvinfo()
7074 regs->version = 0; in bnx2_get_regs()
7078 if (!netif_running(bp->dev)) in bnx2_get_regs()
7100 if (bp->flags & BNX2_FLAG_NO_WOL) { in bnx2_get_wol()
7101 wol->supported = 0; in bnx2_get_wol()
7102 wol->wolopts = 0; in bnx2_get_wol()
7105 wol->supported = WAKE_MAGIC; in bnx2_get_wol()
7106 if (bp->wol) in bnx2_get_wol()
7107 wol->wolopts = WAKE_MAGIC; in bnx2_get_wol()
7109 wol->wolopts = 0; in bnx2_get_wol()
7111 memset(&wol->sopass, 0, sizeof(wol->sopass)); in bnx2_get_wol()
7119 if (wol->wolopts & ~WAKE_MAGIC) in bnx2_set_wol()
7120 return -EINVAL; in bnx2_set_wol()
7122 if (wol->wolopts & WAKE_MAGIC) { in bnx2_set_wol()
7123 if (bp->flags & BNX2_FLAG_NO_WOL) in bnx2_set_wol()
7124 return -EINVAL; in bnx2_set_wol()
7126 bp->wol = 1; in bnx2_set_wol()
7129 bp->wol = 0; in bnx2_set_wol()
7132 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); in bnx2_set_wol()
7144 return -EAGAIN; in bnx2_nway_reset()
7146 if (!(bp->autoneg & AUTONEG_SPEED)) { in bnx2_nway_reset()
7147 return -EINVAL; in bnx2_nway_reset()
7150 spin_lock_bh(&bp->phy_lock); in bnx2_nway_reset()
7152 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_nway_reset()
7155 rc = bnx2_setup_remote_phy(bp, bp->phy_port); in bnx2_nway_reset()
7156 spin_unlock_bh(&bp->phy_lock); in bnx2_nway_reset()
7161 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_nway_reset()
7162 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_nway_reset()
7163 spin_unlock_bh(&bp->phy_lock); in bnx2_nway_reset()
7167 spin_lock_bh(&bp->phy_lock); in bnx2_nway_reset()
7169 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; in bnx2_nway_reset()
7170 bp->serdes_an_pending = 1; in bnx2_nway_reset()
7171 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_nway_reset()
7174 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_nway_reset()
7176 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); in bnx2_nway_reset()
7178 spin_unlock_bh(&bp->phy_lock); in bnx2_nway_reset()
7188 return bp->link_up; in bnx2_get_link()
7196 if (!bp->flash_info) in bnx2_get_eeprom_len()
7199 return (int) bp->flash_size; in bnx2_get_eeprom_len()
7211 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); in bnx2_get_eeprom()
7225 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); in bnx2_set_eeprom()
7239 coal->rx_coalesce_usecs = bp->rx_ticks; in bnx2_get_coalesce()
7240 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; in bnx2_get_coalesce()
7241 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; in bnx2_get_coalesce()
7242 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; in bnx2_get_coalesce()
7244 coal->tx_coalesce_usecs = bp->tx_ticks; in bnx2_get_coalesce()
7245 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; in bnx2_get_coalesce()
7246 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; in bnx2_get_coalesce()
7247 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; in bnx2_get_coalesce()
7249 coal->stats_block_coalesce_usecs = bp->stats_ticks; in bnx2_get_coalesce()
7261 bp->rx_ticks = (u16) coal->rx_coalesce_usecs; in bnx2_set_coalesce()
7262 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; in bnx2_set_coalesce()
7264 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; in bnx2_set_coalesce()
7265 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7267 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; in bnx2_set_coalesce()
7268 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7270 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; in bnx2_set_coalesce()
7271 if (bp->rx_quick_cons_trip_int > 0xff) in bnx2_set_coalesce()
7272 bp->rx_quick_cons_trip_int = 0xff; in bnx2_set_coalesce()
7274 bp->tx_ticks = (u16) coal->tx_coalesce_usecs; in bnx2_set_coalesce()
7275 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; in bnx2_set_coalesce()
7277 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; in bnx2_set_coalesce()
7278 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7280 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; in bnx2_set_coalesce()
7281 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7283 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; in bnx2_set_coalesce()
7284 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = in bnx2_set_coalesce()
7287 bp->stats_ticks = coal->stats_block_coalesce_usecs; in bnx2_set_coalesce()
7288 if (bp->flags & BNX2_FLAG_BROKEN_STATS) { in bnx2_set_coalesce()
7289 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) in bnx2_set_coalesce()
7290 bp->stats_ticks = USEC_PER_SEC; in bnx2_set_coalesce()
7292 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) in bnx2_set_coalesce()
7293 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; in bnx2_set_coalesce()
7294 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; in bnx2_set_coalesce()
7296 if (netif_running(bp->dev)) { in bnx2_set_coalesce()
7312 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT; in bnx2_get_ringparam()
7313 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; in bnx2_get_ringparam()
7315 ering->rx_pending = bp->rx_ring_size; in bnx2_get_ringparam()
7316 ering->rx_jumbo_pending = bp->rx_pg_ring_size; in bnx2_get_ringparam()
7318 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT; in bnx2_get_ringparam()
7319 ering->tx_pending = bp->tx_ring_size; in bnx2_get_ringparam()
7325 if (netif_running(bp->dev)) { in bnx2_change_ring_size()
7342 bp->tx_ring_size = tx; in bnx2_change_ring_size()
7344 if (netif_running(bp->dev)) { in bnx2_change_ring_size()
7363 dev_close(bp->dev); in bnx2_change_ring_size()
7367 mutex_lock(&bp->cnic_lock); in bnx2_change_ring_size()
7369 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) in bnx2_change_ring_size()
7371 mutex_unlock(&bp->cnic_lock); in bnx2_change_ring_size()
7386 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) || in bnx2_set_ringparam()
7387 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) || in bnx2_set_ringparam()
7388 (ering->tx_pending <= MAX_SKB_FRAGS)) { in bnx2_set_ringparam()
7390 return -EINVAL; in bnx2_set_ringparam()
7392 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending, in bnx2_set_ringparam()
7402 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); in bnx2_get_pauseparam()
7403 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); in bnx2_get_pauseparam()
7404 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); in bnx2_get_pauseparam()
7412 bp->req_flow_ctrl = 0; in bnx2_set_pauseparam()
7413 if (epause->rx_pause) in bnx2_set_pauseparam()
7414 bp->req_flow_ctrl |= FLOW_CTRL_RX; in bnx2_set_pauseparam()
7415 if (epause->tx_pause) in bnx2_set_pauseparam()
7416 bp->req_flow_ctrl |= FLOW_CTRL_TX; in bnx2_set_pauseparam()
7418 if (epause->autoneg) { in bnx2_set_pauseparam()
7419 bp->autoneg |= AUTONEG_FLOW_CTRL; in bnx2_set_pauseparam()
7422 bp->autoneg &= ~AUTONEG_FLOW_CTRL; in bnx2_set_pauseparam()
7426 spin_lock_bh(&bp->phy_lock); in bnx2_set_pauseparam()
7427 bnx2_setup_phy(bp, bp->phy_port); in bnx2_set_pauseparam()
7428 spin_unlock_bh(&bp->phy_lock); in bnx2_set_pauseparam()
7581 return -EOPNOTSUPP; in bnx2_get_sset_count()
7591 if (etest->flags & ETH_TEST_FL_OFFLINE) { in bnx2_self_test()
7600 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7604 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7607 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7609 if (!netif_running(bp->dev)) in bnx2_self_test()
7618 if (bp->link_up) in bnx2_self_test()
7626 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7630 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7635 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7661 u32 *hw_stats = (u32 *) bp->stats_blk; in bnx2_get_ethtool_stats()
7662 u32 *temp_stats = (u32 *) bp->temp_stats_blk; in bnx2_get_ethtool_stats()
7689 /* 4-byte counter */ in bnx2_get_ethtool_stats()
7694 /* 8-byte counter */ in bnx2_get_ethtool_stats()
7709 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); in bnx2_set_phys_id()
7728 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save); in bnx2_set_phys_id()
7742 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); in bnx2_set_features()
7744 dev->vlan_features &= ~NETIF_F_ALL_TSO; in bnx2_set_features()
7747 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && in bnx2_set_features()
7750 dev->features = features; in bnx2_set_features()
7767 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { in bnx2_get_channels()
7772 channels->max_rx = max_rx_rings; in bnx2_get_channels()
7773 channels->max_tx = max_tx_rings; in bnx2_get_channels()
7774 channels->max_other = 0; in bnx2_get_channels()
7775 channels->max_combined = 0; in bnx2_get_channels()
7776 channels->rx_count = bp->num_rx_rings; in bnx2_get_channels()
7777 channels->tx_count = bp->num_tx_rings; in bnx2_get_channels()
7778 channels->other_count = 0; in bnx2_get_channels()
7779 channels->combined_count = 0; in bnx2_get_channels()
7790 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { in bnx2_set_channels()
7794 if (channels->rx_count > max_rx_rings || in bnx2_set_channels()
7795 channels->tx_count > max_tx_rings) in bnx2_set_channels()
7796 return -EINVAL; in bnx2_set_channels()
7798 bp->num_req_rx_rings = channels->rx_count; in bnx2_set_channels()
7799 bp->num_req_tx_rings = channels->tx_count; in bnx2_set_channels()
7802 rc = bnx2_change_ring_size(bp, bp->rx_ring_size, in bnx2_set_channels()
7803 bp->tx_ring_size, true); in bnx2_set_channels()
7851 data->phy_id = bp->phy_addr; in bnx2_ioctl()
7857 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_ioctl()
7858 return -EOPNOTSUPP; in bnx2_ioctl()
7861 return -EAGAIN; in bnx2_ioctl()
7863 spin_lock_bh(&bp->phy_lock); in bnx2_ioctl()
7864 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); in bnx2_ioctl()
7865 spin_unlock_bh(&bp->phy_lock); in bnx2_ioctl()
7867 data->val_out = mii_regval; in bnx2_ioctl()
7873 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_ioctl()
7874 return -EOPNOTSUPP; in bnx2_ioctl()
7877 return -EAGAIN; in bnx2_ioctl()
7879 spin_lock_bh(&bp->phy_lock); in bnx2_ioctl()
7880 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()
7881 spin_unlock_bh(&bp->phy_lock); in bnx2_ioctl()
7889 return -EOPNOTSUPP; in bnx2_ioctl()
7899 if (!is_valid_ether_addr(addr->sa_data)) in bnx2_change_mac_addr()
7900 return -EADDRNOTAVAIL; in bnx2_change_mac_addr()
7902 eth_hw_addr_set(dev, addr->sa_data); in bnx2_change_mac_addr()
7904 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_change_mac_addr()
7915 WRITE_ONCE(dev->mtu, new_mtu); in bnx2_change_mtu()
7916 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size, in bnx2_change_mtu()
7927 for (i = 0; i < bp->irq_nvecs; i++) { in poll_bnx2()
7928 struct bnx2_irq *irq = &bp->irq_tbl[i]; in poll_bnx2()
7930 disable_irq(irq->vector); in poll_bnx2()
7931 irq->handler(irq->vector, &bp->bnx2_napi[i]); in poll_bnx2()
7932 enable_irq(irq->vector); in poll_bnx2()
7947 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_get_5709_media()
7956 if (bp->func == 0) { in bnx2_get_5709_media()
7961 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_get_5709_media()
7969 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_get_5709_media()
7984 bp->flags |= BNX2_FLAG_PCIX; in bnx2_get_pci_speed()
7991 bp->bus_speed_mhz = 133; in bnx2_get_pci_speed()
7995 bp->bus_speed_mhz = 100; in bnx2_get_pci_speed()
8000 bp->bus_speed_mhz = 66; in bnx2_get_pci_speed()
8005 bp->bus_speed_mhz = 50; in bnx2_get_pci_speed()
8011 bp->bus_speed_mhz = 33; in bnx2_get_pci_speed()
8017 bp->bus_speed_mhz = 66; in bnx2_get_pci_speed()
8019 bp->bus_speed_mhz = 33; in bnx2_get_pci_speed()
8023 bp->flags |= BNX2_FLAG_PCI_32BIT; in bnx2_get_pci_speed()
8066 memcpy(bp->fw_version, &data[j], len); in bnx2_read_vpd_fw_ver()
8067 bp->fw_version[len] = ' '; in bnx2_read_vpd_fw_ver()
8081 SET_NETDEV_DEV(dev, &pdev->dev); in bnx2_init_board()
8084 bp->flags = 0; in bnx2_init_board()
8085 bp->phy_flags = 0; in bnx2_init_board()
8087 bp->temp_stats_blk = in bnx2_init_board()
8090 if (!bp->temp_stats_blk) { in bnx2_init_board()
8091 rc = -ENOMEM; in bnx2_init_board()
8095 /* enable device (incl. PCI PM wakeup), and bus-mastering */ in bnx2_init_board()
8098 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in bnx2_init_board()
8103 dev_err(&pdev->dev, in bnx2_init_board()
8105 rc = -ENODEV; in bnx2_init_board()
8111 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in bnx2_init_board()
8117 bp->pm_cap = pdev->pm_cap; in bnx2_init_board()
8118 if (bp->pm_cap == 0) { in bnx2_init_board()
8119 dev_err(&pdev->dev, in bnx2_init_board()
8121 rc = -EIO; in bnx2_init_board()
8125 bp->dev = dev; in bnx2_init_board()
8126 bp->pdev = pdev; in bnx2_init_board()
8128 spin_lock_init(&bp->phy_lock); in bnx2_init_board()
8129 spin_lock_init(&bp->indirect_lock); in bnx2_init_board()
8131 mutex_init(&bp->cnic_lock); in bnx2_init_board()
8133 INIT_WORK(&bp->reset_task, bnx2_reset_task); in bnx2_init_board()
8135 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + in bnx2_init_board()
8137 if (!bp->regview) { in bnx2_init_board()
8138 dev_err(&pdev->dev, "Cannot map register space, aborting\n"); in bnx2_init_board()
8139 rc = -ENOMEM; in bnx2_init_board()
8151 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); in bnx2_init_board()
8155 dev_err(&pdev->dev, "Not PCIE, aborting\n"); in bnx2_init_board()
8156 rc = -EIO; in bnx2_init_board()
8159 bp->flags |= BNX2_FLAG_PCIE; in bnx2_init_board()
8161 bp->flags |= BNX2_FLAG_JUMBO_BROKEN; in bnx2_init_board()
8163 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); in bnx2_init_board()
8164 if (bp->pcix_cap == 0) { in bnx2_init_board()
8165 dev_err(&pdev->dev, in bnx2_init_board()
8167 rc = -EIO; in bnx2_init_board()
8170 bp->flags |= BNX2_FLAG_BROKEN_STATS; in bnx2_init_board()
8175 if (pdev->msix_cap) in bnx2_init_board()
8176 bp->flags |= BNX2_FLAG_MSIX_CAP; in bnx2_init_board()
8181 if (pdev->msi_cap) in bnx2_init_board()
8182 bp->flags |= BNX2_FLAG_MSI_CAP; in bnx2_init_board()
8185 /* 5708 cannot support DMA addresses > 40-bit. */ in bnx2_init_board()
8192 if (dma_set_mask(&pdev->dev, dma_mask) == 0) { in bnx2_init_board()
8193 dev->features |= NETIF_F_HIGHDMA; in bnx2_init_board()
8194 rc = dma_set_coherent_mask(&pdev->dev, persist_dma_mask); in bnx2_init_board()
8196 dev_err(&pdev->dev, in bnx2_init_board()
8200 } else if ((rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) != 0) { in bnx2_init_board()
8201 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); in bnx2_init_board()
8205 if (!(bp->flags & BNX2_FLAG_PCIE)) in bnx2_init_board()
8214 !(bp->flags & BNX2_FLAG_PCIX)) { in bnx2_init_board()
8215 dev_err(&pdev->dev, in bnx2_init_board()
8217 rc = -EPERM; in bnx2_init_board()
8226 bp->func = 1; in bnx2_init_board()
8230 u32 off = bp->func << 2; in bnx2_init_board()
8232 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); in bnx2_init_board()
8234 bp->shmem_base = HOST_VIEW_SHMEM_BASE; in bnx2_init_board()
8243 dev_err(&pdev->dev, "Firmware not running, aborting\n"); in bnx2_init_board()
8244 rc = -ENODEV; in bnx2_init_board()
8250 j = strlen(bp->fw_version); in bnx2_init_board()
8256 bp->fw_version[j++] = 'b'; in bnx2_init_board()
8257 bp->fw_version[j++] = 'c'; in bnx2_init_board()
8258 bp->fw_version[j++] = ' '; in bnx2_init_board()
8260 num = (u8) (reg >> (24 - (i * 8))); in bnx2_init_board()
8263 bp->fw_version[j++] = (num / k) + '0'; in bnx2_init_board()
8268 bp->fw_version[j++] = '.'; in bnx2_init_board()
8272 bp->wol = 1; in bnx2_init_board()
8275 bp->flags |= BNX2_FLAG_ASF_ENABLE; in bnx2_init_board()
8291 bp->fw_version[j++] = ' '; in bnx2_init_board()
8295 memcpy(&bp->fw_version[j], ®, 4); in bnx2_init_board()
8301 bp->mac_addr[0] = (u8) (reg >> 8); in bnx2_init_board()
8302 bp->mac_addr[1] = (u8) reg; in bnx2_init_board()
8305 bp->mac_addr[2] = (u8) (reg >> 24); in bnx2_init_board()
8306 bp->mac_addr[3] = (u8) (reg >> 16); in bnx2_init_board()
8307 bp->mac_addr[4] = (u8) (reg >> 8); in bnx2_init_board()
8308 bp->mac_addr[5] = (u8) reg; in bnx2_init_board()
8310 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT; in bnx2_init_board()
8313 bp->tx_quick_cons_trip_int = 2; in bnx2_init_board()
8314 bp->tx_quick_cons_trip = 20; in bnx2_init_board()
8315 bp->tx_ticks_int = 18; in bnx2_init_board()
8316 bp->tx_ticks = 80; in bnx2_init_board()
8318 bp->rx_quick_cons_trip_int = 2; in bnx2_init_board()
8319 bp->rx_quick_cons_trip = 12; in bnx2_init_board()
8320 bp->rx_ticks_int = 18; in bnx2_init_board()
8321 bp->rx_ticks = 18; in bnx2_init_board()
8323 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; in bnx2_init_board()
8325 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_init_board()
8327 bp->phy_addr = 1; in bnx2_init_board()
8338 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_init_board()
8340 bp->phy_port = PORT_TP; in bnx2_init_board()
8341 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_init_board()
8342 bp->phy_port = PORT_FIBRE; in bnx2_init_board()
8345 bp->flags |= BNX2_FLAG_NO_WOL; in bnx2_init_board()
8346 bp->wol = 0; in bnx2_init_board()
8353 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && in bnx2_init_board()
8354 pdev->subsystem_device == 0x310c) in bnx2_init_board()
8355 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; in bnx2_init_board()
8357 bp->phy_addr = 2; in bnx2_init_board()
8359 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; in bnx2_init_board()
8363 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; in bnx2_init_board()
8367 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; in bnx2_init_board()
8375 bp->flags |= BNX2_FLAG_NO_WOL; in bnx2_init_board()
8376 bp->wol = 0; in bnx2_init_board()
8379 if (bp->flags & BNX2_FLAG_NO_WOL) in bnx2_init_board()
8380 device_set_wakeup_capable(&bp->pdev->dev, false); in bnx2_init_board()
8382 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); in bnx2_init_board()
8385 bp->tx_quick_cons_trip_int = in bnx2_init_board()
8386 bp->tx_quick_cons_trip; in bnx2_init_board()
8387 bp->tx_ticks_int = bp->tx_ticks; in bnx2_init_board()
8388 bp->rx_quick_cons_trip_int = in bnx2_init_board()
8389 bp->rx_quick_cons_trip; in bnx2_init_board()
8390 bp->rx_ticks_int = bp->rx_ticks; in bnx2_init_board()
8391 bp->comp_prod_trip_int = bp->comp_prod_trip; in bnx2_init_board()
8392 bp->com_ticks_int = bp->com_ticks; in bnx2_init_board()
8393 bp->cmd_ticks_int = bp->cmd_ticks; in bnx2_init_board()
8398 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes in bnx2_init_board()
8399 * with byte enables disabled on the unused 32-bit word. This is legal in bnx2_init_board()
8413 if (amd_8132->revision >= 0x10 && in bnx2_init_board()
8414 amd_8132->revision <= 0x13) { in bnx2_init_board()
8423 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in bnx2_init_board()
8425 timer_setup(&bp->timer, bnx2_timer, 0); in bnx2_init_board()
8426 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); in bnx2_init_board()
8430 bp->cnic_eth_dev.max_iscsi_conn = in bnx2_init_board()
8433 bp->cnic_probe = bnx2_cnic_probe; in bnx2_init_board()
8440 pci_iounmap(pdev, bp->regview); in bnx2_init_board()
8441 bp->regview = NULL; in bnx2_init_board()
8450 kfree(bp->temp_stats_blk); in bnx2_init_board()
8460 if (bp->flags & BNX2_FLAG_PCIE) { in bnx2_bus_string()
8464 if (bp->flags & BNX2_FLAG_PCIX) in bnx2_bus_string()
8465 s += sprintf(s, "-X"); in bnx2_bus_string()
8466 if (bp->flags & BNX2_FLAG_PCI_32BIT) in bnx2_bus_string()
8467 s += sprintf(s, " 32-bit"); in bnx2_bus_string()
8469 s += sprintf(s, " 64-bit"); in bnx2_bus_string()
8470 s += sprintf(s, " %dMHz", bp->bus_speed_mhz); in bnx2_bus_string()
8480 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_del_napi()
8481 netif_napi_del(&bp->bnx2_napi[i].napi); in bnx2_del_napi()
8489 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_init_napi()
8490 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_init_napi()
8498 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll); in bnx2_init_napi()
8499 bnapi->bp = bp; in bnx2_init_napi()
8531 return -ENOMEM; in bnx2_init_one()
8537 dev->netdev_ops = &bnx2_netdev_ops; in bnx2_init_one()
8538 dev->watchdog_timeo = TX_TIMEOUT; in bnx2_init_one()
8539 dev->ethtool_ops = &bnx2_ethtool_ops; in bnx2_init_one()
8546 * In-flight DMA from 1st kernel could continue going in kdump kernel. in bnx2_init_one()
8547 * New io-page table has been created before bnx2 does reset at open stage. in bnx2_init_one()
8548 * We have to wait for the in-flight DMA to complete to avoid it look up in bnx2_init_one()
8549 * into the newly created io-page table. in bnx2_init_one()
8554 eth_hw_addr_set(dev, bp->mac_addr); in bnx2_init_one()
8556 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | in bnx2_init_one()
8561 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; in bnx2_init_one()
8563 dev->vlan_features = dev->hw_features; in bnx2_init_one()
8564 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; in bnx2_init_one()
8565 dev->features |= dev->hw_features; in bnx2_init_one()
8566 dev->priv_flags |= IFF_UNICAST_FLT; in bnx2_init_one()
8567 dev->min_mtu = MIN_ETHERNET_PACKET_SIZE; in bnx2_init_one()
8568 dev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE; in bnx2_init_one()
8570 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) in bnx2_init_one()
8571 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; in bnx2_init_one()
8574 dev_err(&pdev->dev, "Cannot register net device\n"); in bnx2_init_one()
8579 "node addr %pM\n", board_info[ent->driver_data].name, in bnx2_init_one()
8583 pdev->irq, dev->dev_addr); in bnx2_init_one()
8588 pci_iounmap(pdev, bp->regview); in bnx2_init_one()
8605 del_timer_sync(&bp->timer); in bnx2_remove_one()
8606 cancel_work_sync(&bp->reset_task); in bnx2_remove_one()
8608 pci_iounmap(bp->pdev, bp->regview); in bnx2_remove_one()
8611 kfree(bp->temp_stats_blk); in bnx2_remove_one()
8629 cancel_work_sync(&bp->reset_task); in bnx2_suspend()
8632 del_timer_sync(&bp->timer); in bnx2_suspend()
8667 * bnx2_io_error_detected - called when PCI error is detected
8690 del_timer_sync(&bp->timer); in bnx2_io_error_detected()
8702 * bnx2_io_slot_reset - called after the pci bus has been reset.
8705 * Restart the card from scratch, as if from a cold-boot.
8716 dev_err(&pdev->dev, in bnx2_io_slot_reset()
8717 "Cannot re-enable PCI device after reset\n"); in bnx2_io_slot_reset()
8740 * bnx2_io_resume - called when traffic can start flowing again.
8773 dev_close(bp->dev); in bnx2_shutdown()