Lines Matching +full:0 +full:x33000000
81 static int disable_msi = 0;
87 BCM5706 = 0,
119 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
121 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
127 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
136 { PCI_VENDOR_ID_BROADCOM, 0x163b,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
138 { PCI_VENDOR_ID_BROADCOM, 0x163c,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
140 { 0, }
148 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
153 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
155 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
165 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
170 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
172 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
175 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
180 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
186 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
191 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
196 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
198 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
211 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
216 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
223 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
226 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
255 diff &= 0xffff; in bnx2_tx_avail()
311 for (i = 0; i < 5; i++) { in bnx2_ctx_wr()
313 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) in bnx2_ctx_wr()
344 return 0; in bnx2_drv_ctl()
350 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_setup_cnic_irq_info()
355 bnapi->cnic_present = 0; in bnx2_setup_cnic_irq_info()
357 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
362 sb_id = 0; in bnx2_setup_cnic_irq_info()
363 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
366 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; in bnx2_setup_cnic_irq_info()
367 cp->irq_arr[0].status_blk = (void *) in bnx2_setup_cnic_irq_info()
370 cp->irq_arr[0].status_blk_map = bp->status_blk_mapping; in bnx2_setup_cnic_irq_info()
371 cp->irq_arr[0].status_blk_num = sb_id; in bnx2_setup_cnic_irq_info()
393 cp->num_irq = 0; in bnx2_register_cnic()
398 return 0; in bnx2_register_cnic()
404 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_unregister_cnic()
408 cp->drv_state = 0; in bnx2_unregister_cnic()
409 bnapi->cnic_present = 0; in bnx2_unregister_cnic()
413 return 0; in bnx2_unregister_cnic()
462 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_cnic_start()
507 for (i = 0; i < 50; i++) { in bnx2_read_phy()
522 *val = 0x0; in bnx2_read_phy()
527 ret = 0; in bnx2_read_phy()
564 for (i = 0; i < 50; i++) { in bnx2_write_phy()
577 ret = 0; in bnx2_write_phy()
598 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_disable_int()
612 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_enable_int()
637 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_disable_int_sync()
646 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_disable()
655 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_enable()
695 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_mem()
715 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_mem()
720 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_free_rx_mem()
730 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_free_rx_mem()
747 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_alloc_tx_mem()
761 return 0; in bnx2_alloc_tx_mem()
769 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_alloc_rx_mem()
779 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_alloc_rx_mem()
799 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_alloc_rx_mem()
810 return 0; in bnx2_alloc_rx_mem()
850 return 0; in bnx2_alloc_stats_blk()
857 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_free_mem()
862 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_free_mem()
881 bnapi = &bp->bnx2_napi[0]; in bnx2_alloc_mem()
904 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; in bnx2_alloc_mem()
905 if (bp->ctx_pages == 0) in bnx2_alloc_mem()
907 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_alloc_mem()
925 return 0; in bnx2_alloc_mem()
935 u32 fw_link_status = 0; in bnx2_report_fw_link()
1035 bp->flow_ctrl = 0; in bnx2_resolve_flow_ctrl()
1065 u32 new_local_adv = 0; in bnx2_resolve_flow_ctrl()
1066 u32 new_remote_adv = 0; in bnx2_resolve_flow_ctrl()
1117 if ((bp->autoneg & AUTONEG_SPEED) == 0) { in bnx2_5709s_linkup()
1120 return 0; in bnx2_5709s_linkup()
1142 return 0; in bnx2_5709s_linkup()
1171 return 0; in bnx2_5708s_linkup()
1191 return 0; in bnx2_5706s_linkup()
1208 return 0; in bnx2_5706s_linkup()
1256 bp->line_speed = 0; in bnx2_copper_linkup()
1257 bp->link_up = 0; in bnx2_copper_linkup()
1284 return 0; in bnx2_copper_linkup()
1294 val |= 0x02 << 8; in bnx2_init_rx_context()
1308 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { in bnx2_init_all_rx_contexts()
1320 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); in bnx2_set_mac_link()
1323 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); in bnx2_set_mac_link()
1407 return 0; in bnx2_test_and_enable_2g5()
1419 ret = 0; in bnx2_test_and_enable_2g5()
1433 int ret = 0; in bnx2_test_and_disable_2g5()
1436 return 0; in bnx2_test_and_disable_2g5()
1546 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); in bnx2_5706s_force_link_dn()
1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); in bnx2_5706s_force_link_dn()
1559 return 0; in bnx2_set_link()
1563 return 0; in bnx2_set_link()
1577 bnx2_5706s_force_link_dn(bp, 0); in bnx2_set_link()
1623 bp->link_up = 0; in bnx2_set_link()
1632 return 0; in bnx2_set_link()
1644 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { in bnx2_reset_phy()
1656 return 0; in bnx2_reset_phy()
1662 u32 adv = 0; in bnx2_phy_get_pause_adv()
1700 u32 speed_arg = 0, pause_adv; in bnx2_setup_remote_phy()
1748 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); in bnx2_setup_remote_phy()
1751 return 0; in bnx2_setup_remote_phy()
1760 u32 new_adv = 0; in bnx2_setup_serdes_phy()
1767 int force_link_down = 0; in bnx2_setup_serdes_phy()
1788 new_bmcr &= ~0x2000; in bnx2_setup_serdes_phy()
1815 bp->link_up = 0; in bnx2_setup_serdes_phy()
1826 return 0; in bnx2_setup_serdes_phy()
1839 bp->serdes_an_pending = 0; in bnx2_setup_serdes_phy()
1840 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { in bnx2_setup_serdes_phy()
1868 return 0; in bnx2_setup_serdes_phy()
1897 bp->req_line_speed = 0; in bnx2_set_default_remote_link()
1913 bp->autoneg = 0; in bnx2_set_default_remote_link()
1914 bp->advertising = 0; in bnx2_set_default_remote_link()
1942 bp->req_line_speed = 0; in bnx2_set_default_link()
1951 bp->autoneg = 0; in bnx2_set_default_link()
1988 bp->link_up = 0; in bnx2_remote_phy_event()
2022 bp->line_speed = 0; in bnx2_remote_phy_event()
2026 bp->flow_ctrl = 0; in bnx2_remote_phy_event()
2069 return 0; in bnx2_set_remote_link()
2077 u32 bmcr, adv_reg, new_adv = 0; in bnx2_setup_copper_phy()
2090 u32 new_adv1000 = 0; in bnx2_setup_copper_phy()
2100 ((bmcr & BMCR_ANENABLE) == 0)) { in bnx2_setup_copper_phy()
2114 return 0; in bnx2_setup_copper_phy()
2121 new_bmcr = 0; in bnx2_setup_copper_phy()
2161 return 0; in bnx2_setup_copper_phy()
2170 return 0; in bnx2_setup_phy()
2185 bp->mii_bmcr = MII_BMCR + 0x10; in bnx2_init_5709s_phy()
2186 bp->mii_bmsr = MII_BMSR + 0x10; in bnx2_init_5709s_phy()
2188 bp->mii_adv = MII_ADVERTISE + 0x10; in bnx2_init_5709s_phy()
2189 bp->mii_lpa = MII_LPA + 0x10; in bnx2_init_5709s_phy()
2227 return 0; in bnx2_init_5709s_phy()
2285 return 0; in bnx2_init_5708s_phy()
2297 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); in bnx2_init_5706s_phy()
2303 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2304 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_5706s_phy()
2305 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); in bnx2_init_5706s_phy()
2307 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2308 bnx2_read_phy(bp, 0x1c, &val); in bnx2_init_5706s_phy()
2309 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); in bnx2_init_5706s_phy()
2314 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2315 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_5706s_phy()
2316 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_5706s_phy()
2318 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2319 bnx2_read_phy(bp, 0x1c, &val); in bnx2_init_5706s_phy()
2320 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); in bnx2_init_5706s_phy()
2323 return 0; in bnx2_init_5706s_phy()
2335 bnx2_write_phy(bp, 0x18, 0x0c00); in bnx2_init_copper_phy()
2336 bnx2_write_phy(bp, 0x17, 0x000a); in bnx2_init_copper_phy()
2337 bnx2_write_phy(bp, 0x15, 0x310b); in bnx2_init_copper_phy()
2338 bnx2_write_phy(bp, 0x17, 0x201f); in bnx2_init_copper_phy()
2339 bnx2_write_phy(bp, 0x15, 0x9506); in bnx2_init_copper_phy()
2340 bnx2_write_phy(bp, 0x17, 0x401f); in bnx2_init_copper_phy()
2341 bnx2_write_phy(bp, 0x15, 0x14e2); in bnx2_init_copper_phy()
2342 bnx2_write_phy(bp, 0x18, 0x0400); in bnx2_init_copper_phy()
2347 MII_BNX2_DSP_EXPAND_REG | 0x8); in bnx2_init_copper_phy()
2355 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2356 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_copper_phy()
2357 bnx2_write_phy(bp, 0x18, val | 0x4000); in bnx2_init_copper_phy()
2359 bnx2_read_phy(bp, 0x10, &val); in bnx2_init_copper_phy()
2360 bnx2_write_phy(bp, 0x10, val | 0x1); in bnx2_init_copper_phy()
2363 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2364 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_copper_phy()
2365 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_copper_phy()
2367 bnx2_read_phy(bp, 0x10, &val); in bnx2_init_copper_phy()
2368 bnx2_write_phy(bp, 0x10, val & ~0x1); in bnx2_init_copper_phy()
2381 return 0; in bnx2_init_copper_phy()
2391 int rc = 0; in bnx2_init_phy()
2410 bp->phy_id |= val & 0xffff; in bnx2_init_phy()
2441 return 0; in bnx2_set_mac_loopback()
2459 for (i = 0; i < 10; i++) { in bnx2_set_phy_loopback()
2460 if (bnx2_test_link(bp) == 0) in bnx2_set_phy_loopback()
2473 return 0; in bnx2_set_phy_loopback()
2512 DP_SHMEM_LINE(bp, 0x3cc); in bnx2_dump_mcp_state()
2513 DP_SHMEM_LINE(bp, 0x3dc); in bnx2_dump_mcp_state()
2514 DP_SHMEM_LINE(bp, 0x3ec); in bnx2_dump_mcp_state()
2515 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc)); in bnx2_dump_mcp_state()
2532 return 0; in bnx2_fw_sync()
2535 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { in bnx2_fw_sync()
2544 return 0; in bnx2_fw_sync()
2563 return 0; in bnx2_fw_sync()
2569 int i, ret = 0; in bnx2_init_5709_context()
2575 for (i = 0; i < 10; i++) { in bnx2_init_5709_context()
2584 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_init_5709_context()
2588 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); in bnx2_init_5709_context()
2593 (bp->ctx_blk_mapping[i] & 0xffffffff) | in bnx2_init_5709_context()
2599 for (j = 0; j < 10; j++) { in bnx2_init_5709_context()
2630 if (vcid & 0x8) { in bnx2_init_context()
2631 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); in bnx2_init_context()
2643 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { in bnx2_init_context()
2651 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) in bnx2_init_context()
2652 bnx2_ctx_wr(bp, vcid_addr, offset, 0); in bnx2_init_context()
2671 good_mbuf_cnt = 0; in bnx2_alloc_bad_rbuf()
2703 return 0; in bnx2_alloc_bad_rbuf()
2711 val = (mac_addr[0] << 8) | mac_addr[1]; in bnx2_set_mac_addr()
2732 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, in bnx2_alloc_rx_page()
2742 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_page()
2743 return 0; in bnx2_alloc_rx_page()
2788 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_data()
2792 return 0; in bnx2_alloc_rx_data()
2810 is_set = 0; in bnx2_phy_event_is_set()
2846 int tx_pkt = 0, index; in bnx2_tx_int()
2847 unsigned int tx_bytes = 0; in bnx2_tx_int()
2878 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { in bnx2_tx_int()
2889 for (i = 0; i < last; i++) { in bnx2_tx_int()
2966 for (i = 0; i < count; i++) { in bnx2_reuse_rx_skb_pages()
3029 u16 prod = ring_idx & 0xffff; in bnx2_rx_skb()
3053 if (hdr_len == 0) { in bnx2_rx_skb()
3066 for (i = 0; i < pages; i++) { in bnx2_rx_skb()
3078 if (i == 0) { in bnx2_rx_skb()
3097 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); in bnx2_rx_skb()
3146 int rx_pkt = 0, pg_ring_used = 0; in bnx2_rx_int()
3148 if (budget <= 0) in bnx2_rx_int()
3191 hdr_len = 0; in bnx2_rx_int()
3251 skb->protocol != htons(0x8100) && in bnx2_rx_int()
3265 L2_FHDR_ERRORS_UDP_XSUM)) == 0)) in bnx2_rx_int()
3274 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); in bnx2_rx_int()
3320 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi()
3337 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi_1shot()
3373 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_interrupt()
3393 return 0; in bnx2_has_fast_work()
3416 return 0; in bnx2_has_work()
3422 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_chk_missed_msi()
3434 bnx2_msi(bp->irq_tbl[0].vector, bnapi); in bnx2_chk_missed_msi()
3485 bnx2_tx_int(bp, bnapi, 0); in bnx2_poll_work()
3497 int work_done = 0; in bnx2_poll_msix()
3524 int work_done = 0; in bnx2_poll()
3598 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { in bnx2_set_rx_mode()
3600 0xffffffff); in bnx2_set_rx_mode()
3611 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); in bnx2_set_rx_mode()
3615 bit = crc & 0xff; in bnx2_set_rx_mode()
3616 regidx = (bit & 0xe0) >> 5; in bnx2_set_rx_mode()
3617 bit &= 0x1f; in bnx2_set_rx_mode()
3621 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { in bnx2_set_rx_mode()
3635 i = 0; in bnx2_set_rx_mode()
3651 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); in bnx2_set_rx_mode()
3666 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) in check_fw_section()
3668 if ((non_empty && len == 0) || len > fw->size - offset || in check_fw_section()
3671 return 0; in check_fw_section()
3682 return 0; in check_mips_fw_entry()
3756 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); in bnx2_request_firmware()
3793 for (i = 0; i < rv2p_code_len; i += 8) { in load_rv2p_fw()
3804 for (i = 0; i < 8; i++) { in load_rv2p_fw()
3828 return 0; in load_rv2p_fw()
3856 for (j = 0; j < (len / 4); j++, offset += 4) in load_cpu_fw()
3870 for (j = 0; j < (len / 4); j++, offset += 4) in load_cpu_fw()
3884 for (j = 0; j < (len / 4); j++, offset += 4) in load_cpu_fw()
3889 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); in load_cpu_fw()
3958 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_setup_wol()
3978 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { in bnx2_setup_wol()
3980 0xffffffff); in bnx2_setup_wol()
3985 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); in bnx2_setup_wol()
4009 bnx2_fw_sync(bp, wol_msg, 1, 0); in bnx2_setup_wol()
4018 bnx2_fw_sync(bp, wol_msg, 1, 0); in bnx2_setup_wol()
4077 return 0; in bnx2_set_power_state()
4088 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_acquire_nvram_lock()
4099 return 0; in bnx2_acquire_nvram_lock()
4111 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_release_nvram_lock()
4122 return 0; in bnx2_release_nvram_lock()
4141 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_enable_nvram_write()
4152 return 0; in bnx2_enable_nvram_write()
4196 return 0; in bnx2_nvram_erase_page()
4212 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_nvram_erase_page()
4225 return 0; in bnx2_nvram_erase_page()
4254 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_nvram_read_dword()
4269 return 0; in bnx2_nvram_read_dword()
4305 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_nvram_write_dword()
4314 return 0; in bnx2_nvram_write_dword()
4321 int j, entry_count, rc = 0; in bnx2_init_nvram()
4334 if (val & 0x40000000) { in bnx2_init_nvram()
4337 for (j = 0, flash = &flash_table[0]; j < entry_count; in bnx2_init_nvram()
4355 for (j = 0, flash = &flash_table[0]; j < entry_count; in bnx2_init_nvram()
4362 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) in bnx2_init_nvram()
4381 } /* if (val & 0x40000000) */ in bnx2_init_nvram()
4404 int rc = 0; in bnx2_nvram_read()
4407 if (buf_size == 0) in bnx2_nvram_read()
4408 return 0; in bnx2_nvram_read()
4411 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) in bnx2_nvram_read()
4419 extra = 0; in bnx2_nvram_read()
4421 cmd_flags = 0; in bnx2_nvram_read()
4468 else if (len32 > 0) { in bnx2_nvram_read()
4473 cmd_flags = 0; in bnx2_nvram_read()
4484 while (len32 > 4 && rc == 0) { in bnx2_nvram_read()
4485 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); in bnx2_nvram_read()
4516 int rc = 0; in bnx2_nvram_write()
4522 align_start = align_end = 0; in bnx2_nvram_write()
4562 written = 0; in bnx2_nvram_write()
4563 while ((written < len32) && (rc == 0)) { in bnx2_nvram_write()
4574 data_start = (written == 0) ? offset32 : page_start; in bnx2_nvram_write()
4580 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) in bnx2_nvram_write()
4592 for (j = 0; j < bp->flash_info->page_size; j += 4) { in bnx2_nvram_write()
4604 cmd_flags = 0; in bnx2_nvram_write()
4609 if ((rc = bnx2_enable_nvram_write(bp)) != 0) in bnx2_nvram_write()
4614 i = 0; in bnx2_nvram_write()
4617 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) in bnx2_nvram_write()
4629 if (rc != 0) in bnx2_nvram_write()
4632 cmd_flags = 0; in bnx2_nvram_write()
4647 if (rc != 0) in bnx2_nvram_write()
4650 cmd_flags = 0; in bnx2_nvram_write()
4666 if (rc != 0) in bnx2_nvram_write()
4669 cmd_flags = 0; in bnx2_nvram_write()
4693 u32 val, sig = 0; in bnx2_init_fw_cap()
4764 for (i = 0; i < 100; i++) { in bnx2_wait_dma_complete()
4780 int i, rc = 0; in bnx2_reset_chip()
4826 for (i = 0; i < 10; i++) { in bnx2_reset_chip()
4829 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) in bnx2_reset_chip()
4843 if (val != 0x01020304) { in bnx2_reset_chip()
4849 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); in bnx2_reset_chip()
4863 * of this register is 0x0000000e. */ in bnx2_reset_chip()
4864 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); in bnx2_reset_chip()
4898 val |= (0x2 << 20) | (1 << 11); in bnx2_init_chip()
4943 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_init_chip()
4956 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); in bnx2_init_chip()
4966 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; in bnx2_init_chip()
4969 val = bp->mac_addr[0] + in bnx2_init_chip()
4991 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); in bnx2_init_chip()
4992 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) in bnx2_init_chip()
4993 bp->bnx2_napi[i].last_status_idx = 0; in bnx2_init_chip()
4995 bp->idle_chk_status_idx = 0xffff; in bnx2_init_chip()
5001 (u64) bp->status_blk_mapping & 0xffffffff); in bnx2_init_chip()
5005 (u64) bp->stats_blk_mapping & 0xffffffff); in bnx2_init_chip()
5029 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0); in bnx2_init_chip()
5032 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ in bnx2_init_chip()
5056 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0); in bnx2_init_chip()
5096 1, 0); in bnx2_init_chip()
5116 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { in bnx2_clear_ring_states()
5121 txr->tx_cons = 0; in bnx2_clear_ring_states()
5122 txr->hw_tx_cons = 0; in bnx2_clear_ring_states()
5123 rxr->rx_prod_bseq = 0; in bnx2_clear_ring_states()
5124 rxr->rx_prod = 0; in bnx2_clear_ring_states()
5125 rxr->rx_cons = 0; in bnx2_clear_ring_states()
5126 rxr->rx_pg_prod = 0; in bnx2_clear_ring_states()
5127 rxr->rx_pg_cons = 0; in bnx2_clear_ring_states()
5157 val = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_context()
5172 if (ring_num == 0) in bnx2_init_tx_ring()
5182 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_ring()
5184 txr->tx_prod = 0; in bnx2_init_tx_ring()
5185 txr->tx_prod_bseq = 0; in bnx2_init_tx_ring()
5200 for (i = 0; i < num_rings; i++) { in bnx2_init_rxbd_rings()
5203 rxbd = &rx_ring[i][0]; in bnx2_init_rxbd_rings()
5204 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) { in bnx2_init_rxbd_rings()
5209 j = 0; in bnx2_init_rxbd_rings()
5213 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; in bnx2_init_rxbd_rings()
5226 if (ring_num == 0) in bnx2_init_rx_ring()
5243 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); in bnx2_init_rx_ring()
5253 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5256 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5263 val = (u64) rxr->rx_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5266 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5270 for (i = 0; i < bp->rx_pg_ring_size; i++) { in bnx2_init_rx_ring()
5271 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) { in bnx2_init_rx_ring()
5282 for (i = 0; i < bp->rx_ring_size; i++) { in bnx2_init_rx_ring()
5283 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) { in bnx2_init_rx_ring()
5311 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0); in bnx2_init_all_rings()
5312 for (i = 0; i < bp->num_tx_rings; i++) in bnx2_init_all_rings()
5319 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); in bnx2_init_all_rings()
5320 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); in bnx2_init_all_rings()
5322 for (i = 0; i < bp->num_rx_rings; i++) in bnx2_init_all_rings()
5326 u32 tbl_32 = 0; in bnx2_init_all_rings()
5328 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { in bnx2_init_all_rings()
5338 tbl_32 = 0; in bnx2_init_all_rings()
5360 while ((max & num_rings) == 0) in bnx2_find_max_ring()
5381 bp->rx_pg_ring_size = 0; in bnx2_set_rx_ring_size()
5382 bp->rx_max_pg_ring = 0; in bnx2_set_rx_ring_size()
5383 bp->rx_max_pg_ring_idx = 0; in bnx2_set_rx_ring_size()
5397 bp->rx_copy_thresh = 0; in bnx2_set_rx_ring_size()
5416 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_skbs()
5424 for (j = 0; j < BNX2_TX_DESC_CNT; ) { in bnx2_free_tx_skbs()
5443 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { in bnx2_free_tx_skbs()
5461 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_skbs()
5469 for (j = 0; j < bp->rx_max_ring_idx; j++) { in bnx2_free_rx_skbs()
5485 for (j = 0; j < bp->rx_max_pg_ring_idx; j++) in bnx2_free_rx_skbs()
5507 if ((rc = bnx2_init_chip(bp)) != 0) in bnx2_reset_nic()
5511 return 0; in bnx2_reset_nic()
5519 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) in bnx2_init_nic()
5528 return 0; in bnx2_init_nic()
5558 { 0x006c, 0, 0x00000000, 0x0000003f }, in bnx2_test_registers()
5559 { 0x0090, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5560 { 0x0094, 0, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5562 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, in bnx2_test_registers()
5563 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5564 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5565 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, in bnx2_test_registers()
5566 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5567 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5568 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, in bnx2_test_registers()
5569 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5570 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5572 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5573 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5574 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5575 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5576 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5577 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5579 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5580 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, in bnx2_test_registers()
5581 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, in bnx2_test_registers()
5583 { 0x1000, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5584 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, in bnx2_test_registers()
5586 { 0x1408, 0, 0x01c00800, 0x00000000 }, in bnx2_test_registers()
5587 { 0x149c, 0, 0x8000ffff, 0x00000000 }, in bnx2_test_registers()
5588 { 0x14a8, 0, 0x00000000, 0x000001ff }, in bnx2_test_registers()
5589 { 0x14ac, 0, 0x0fffffff, 0x10000000 }, in bnx2_test_registers()
5590 { 0x14b0, 0, 0x00000002, 0x00000001 }, in bnx2_test_registers()
5591 { 0x14b8, 0, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5592 { 0x14c0, 0, 0x00000000, 0x00000009 }, in bnx2_test_registers()
5593 { 0x14c4, 0, 0x00003fff, 0x00000000 }, in bnx2_test_registers()
5594 { 0x14cc, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5595 { 0x14d0, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5597 { 0x1800, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5598 { 0x1804, 0, 0x00000000, 0x00000003 }, in bnx2_test_registers()
5600 { 0x2800, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5601 { 0x2804, 0, 0x00000000, 0x00003f01 }, in bnx2_test_registers()
5602 { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, in bnx2_test_registers()
5603 { 0x2810, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5604 { 0x2814, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5605 { 0x2818, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5606 { 0x281c, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5607 { 0x2834, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5608 { 0x2840, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5609 { 0x2844, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5610 { 0x2848, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5611 { 0x284c, 0, 0xf800f800, 0x07ff07ff }, in bnx2_test_registers()
5613 { 0x2c00, 0, 0x00000000, 0x00000011 }, in bnx2_test_registers()
5614 { 0x2c04, 0, 0x00000000, 0x00030007 }, in bnx2_test_registers()
5616 { 0x3c00, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5617 { 0x3c04, 0, 0x00000000, 0x00070000 }, in bnx2_test_registers()
5618 { 0x3c08, 0, 0x00007f71, 0x07f00000 }, in bnx2_test_registers()
5619 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, in bnx2_test_registers()
5620 { 0x3c10, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5621 { 0x3c14, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5622 { 0x3c18, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5623 { 0x3c1c, 0, 0xfffff000, 0x00000000 }, in bnx2_test_registers()
5624 { 0x3c20, 0, 0xffffff00, 0x00000000 }, in bnx2_test_registers()
5626 { 0x5004, 0, 0x00000000, 0x0000007f }, in bnx2_test_registers()
5627 { 0x5008, 0, 0x0f0007ff, 0x00000000 }, in bnx2_test_registers()
5629 { 0x5c00, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5630 { 0x5c04, 0, 0x00000000, 0x0003000f }, in bnx2_test_registers()
5631 { 0x5c08, 0, 0x00000003, 0x00000000 }, in bnx2_test_registers()
5632 { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, in bnx2_test_registers()
5633 { 0x5c10, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5634 { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, in bnx2_test_registers()
5635 { 0x5c84, 0, 0x00000000, 0x0000f333 }, in bnx2_test_registers()
5636 { 0x5c88, 0, 0x00000000, 0x00077373 }, in bnx2_test_registers()
5637 { 0x5c8c, 0, 0x00000000, 0x0007f737 }, in bnx2_test_registers()
5639 { 0x6808, 0, 0x0000ff7f, 0x00000000 }, in bnx2_test_registers()
5640 { 0x680c, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5641 { 0x6810, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5642 { 0x6814, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5643 { 0x6818, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5644 { 0x681c, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5645 { 0x6820, 0, 0x00ff00ff, 0x00000000 }, in bnx2_test_registers()
5646 { 0x6824, 0, 0x00ff00ff, 0x00000000 }, in bnx2_test_registers()
5647 { 0x6828, 0, 0x00ff00ff, 0x00000000 }, in bnx2_test_registers()
5648 { 0x682c, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5649 { 0x6830, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5650 { 0x6834, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5651 { 0x6838, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5652 { 0x683c, 0, 0x0000ffff, 0x00000000 }, in bnx2_test_registers()
5653 { 0x6840, 0, 0x00000ff0, 0x00000000 }, in bnx2_test_registers()
5654 { 0x6844, 0, 0x00ffff00, 0x00000000 }, in bnx2_test_registers()
5655 { 0x684c, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5656 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5657 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5658 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5659 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5660 { 0x6908, 0, 0x00000000, 0x0001ff0f }, in bnx2_test_registers()
5661 { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, in bnx2_test_registers()
5663 { 0xffff, 0, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5666 ret = 0; in bnx2_test_registers()
5667 is_5709 = 0; in bnx2_test_registers()
5671 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in bnx2_test_registers()
5684 writel(0, bp->regview + offset); in bnx2_test_registers()
5687 if ((val & rw_mask) != 0) { in bnx2_test_registers()
5695 writel(0xffffffff, bp->regview + offset); in bnx2_test_registers()
5720 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, in bnx2_do_mem_test()
5721 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; in bnx2_do_mem_test()
5724 for (i = 0; i < sizeof(test_pattern) / 4; i++) { in bnx2_do_mem_test()
5727 for (offset = 0; offset < size; offset += 4) { in bnx2_do_mem_test()
5737 return 0; in bnx2_do_mem_test()
5743 int ret = 0; in bnx2_test_memory()
5749 { 0x60000, 0x4000 }, in bnx2_test_memory()
5750 { 0xa0000, 0x3000 }, in bnx2_test_memory()
5751 { 0xe0000, 0x4000 }, in bnx2_test_memory()
5752 { 0x120000, 0x4000 }, in bnx2_test_memory()
5753 { 0x1a0000, 0x4000 }, in bnx2_test_memory()
5754 { 0x160000, 0x4000 }, in bnx2_test_memory()
5755 { 0xffffffff, 0 }, in bnx2_test_memory()
5758 { 0x60000, 0x4000 }, in bnx2_test_memory()
5759 { 0xa0000, 0x3000 }, in bnx2_test_memory()
5760 { 0xe0000, 0x4000 }, in bnx2_test_memory()
5761 { 0x120000, 0x4000 }, in bnx2_test_memory()
5762 { 0x1a0000, 0x4000 }, in bnx2_test_memory()
5763 { 0xffffffff, 0 }, in bnx2_test_memory()
5772 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { in bnx2_test_memory()
5774 mem_tbl[i].len)) != 0) { in bnx2_test_memory()
5782 #define BNX2_MAC_LOOPBACK 0
5798 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; in bnx2_run_loopback()
5812 return 0; in bnx2_run_loopback()
5826 memset(packet + ETH_ALEN, 0x0, 8); in bnx2_run_loopback()
5828 packet[i] = (unsigned char) (i & 0xff); in bnx2_run_loopback()
5845 num_pkts = 0; in bnx2_run_loopback()
5850 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; in bnx2_run_loopback()
5906 if (*(data + i) != (unsigned char) (i & 0xff)) { in bnx2_run_loopback()
5911 ret = 0; in bnx2_run_loopback()
5914 bp->loopback = 0; in bnx2_run_loopback()
5926 int rc = 0; in bnx2_test_loopback()
5942 #define NVRAM_SIZE 0x200
5943 #define CRC32_RESIDUAL 0xdebb20e3
5950 int rc = 0; in bnx2_test_nvram()
5953 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) in bnx2_test_nvram()
5956 magic = be32_to_cpu(buf[0]); in bnx2_test_nvram()
5957 if (magic != 0x669955aa) { in bnx2_test_nvram()
5962 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) in bnx2_test_nvram()
5965 csum = ether_crc_le(0x100, data); in bnx2_test_nvram()
5971 csum = ether_crc_le(0x100, data + 0x100); in bnx2_test_nvram()
5990 return 0; in bnx2_test_link()
6001 return 0; in bnx2_test_link()
6015 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; in bnx2_test_intr()
6021 for (i = 0; i < 10; i++) { in bnx2_test_intr()
6022 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != in bnx2_test_intr()
6031 return 0; in bnx2_test_intr()
6043 return 0; in bnx2_5706_serdes_has_link()
6049 return 0; in bnx2_5706_serdes_has_link()
6056 return 0; in bnx2_5706_serdes_has_link()
6063 return 0; in bnx2_5706_serdes_has_link()
6076 check_link = 0; in bnx2_5706_serdes_timer()
6077 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5706_serdes_timer()
6097 bnx2_write_phy(bp, 0x17, 0x0f01); in bnx2_5706_serdes_timer()
6098 bnx2_read_phy(bp, 0x15, &phy2); in bnx2_5706_serdes_timer()
6099 if (phy2 & 0x20) { in bnx2_5706_serdes_timer()
6136 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { in bnx2_5708_serdes_timer()
6137 bp->serdes_an_pending = 0; in bnx2_5708_serdes_timer()
6144 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5708_serdes_timer()
6171 if (atomic_read(&bp->intr_sem) != 0) in bnx2_timer()
6204 int rc = 0, i; in bnx2_request_irq()
6207 flags = 0; in bnx2_request_irq()
6211 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_request_irq()
6228 for (i = 0; i < bp->irq_nvecs; i++) { in __bnx2_free_irq()
6232 irq->requested = 0; in __bnx2_free_irq()
6255 const int len = sizeof(bp->irq_tbl[0].name); in bnx2_enable_msix()
6266 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { in bnx2_enable_msix()
6268 msix_ent[i].vector = 0; in bnx2_enable_msix()
6277 if (total_vecs < 0) in bnx2_enable_msix()
6286 for (i = 0; i < total_vecs; i++) { in bnx2_enable_msix()
6308 bp->irq_tbl[0].handler = bnx2_interrupt; in bnx2_setup_int_mode()
6309 strcpy(bp->irq_tbl[0].name, bp->dev->name); in bnx2_setup_int_mode()
6311 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6318 if (pci_enable_msi(bp->pdev) == 0) { in bnx2_setup_int_mode()
6322 bp->irq_tbl[0].handler = bnx2_msi_1shot; in bnx2_setup_int_mode()
6324 bp->irq_tbl[0].handler = bnx2_msi; in bnx2_setup_int_mode()
6326 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6353 if (rc < 0) in bnx2_open()
6379 atomic_set(&bp->intr_sem, 0); in bnx2_open()
6381 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); in bnx2_open()
6389 if (bnx2_test_intr(bp) != 0) { in bnx2_open()
6397 rc = bnx2_init_nic(bp, 0); in bnx2_open()
6492 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++) in bnx2_dump_ftq()
6497 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000) in bnx2_dump_ftq()
6502 bnx2_reg_rd_ind(bp, reg + 0x1c), in bnx2_dump_ftq()
6503 bnx2_reg_rd_ind(bp, reg + 0x1c), in bnx2_dump_ftq()
6504 bnx2_reg_rd_ind(bp, reg + 0x20)); in bnx2_dump_ftq()
6511 for (i = 0; i < 0x20; i++) { in bnx2_dump_ftq()
6512 int j = 0; in bnx2_dump_ftq()
6527 bdidx >> 24, (valid >> 8) & 0x0ff); in bnx2_dump_ftq()
6604 vlan_tag_flags = 0; in bnx2_start_xmit()
6628 if (likely(tcp_off == 0)) in bnx2_start_xmit()
6632 vlan_tag_flags |= ((tcp_off & 0x3) << in bnx2_start_xmit()
6634 ((tcp_off & 0x10) << in bnx2_start_xmit()
6636 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; in bnx2_start_xmit()
6646 mss = 0; in bnx2_start_xmit()
6662 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6670 for (i = 0; i < last_frag; i++) { in bnx2_start_xmit()
6678 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, in bnx2_start_xmit()
6686 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6733 for (i = 0; i < last_frag; i++) { in bnx2_start_xmit()
6761 bp->link_up = 0; in bnx2_close()
6763 return 0; in bnx2_close()
6774 for (i = 0; i < 20; i += 2) { in bnx2_save_stats()
6780 if (lo > 0xffffffff) in bnx2_save_stats()
6783 temp_stats[i + 1] = lo & 0xffffffff; in bnx2_save_stats()
6855 net_stats->tx_carrier_errors = 0; in bnx2_get_stats64()
6880 int support_serdes = 0, support_copper = 0; in bnx2_get_link_ksettings()
6940 return 0; in bnx2_get_link_ksettings()
7004 advertising = 0; in bnx2_set_link_ksettings()
7012 err = 0; in bnx2_set_link_ksettings()
7050 0x0000, 0x0098, 0x0400, 0x045c, in bnx2_get_regs()
7051 0x0800, 0x0880, 0x0c00, 0x0c10, in bnx2_get_regs()
7052 0x0c30, 0x0d08, 0x1000, 0x101c, in bnx2_get_regs()
7053 0x1040, 0x1048, 0x1080, 0x10a4, in bnx2_get_regs()
7054 0x1400, 0x1490, 0x1498, 0x14f0, in bnx2_get_regs()
7055 0x1500, 0x155c, 0x1580, 0x15dc, in bnx2_get_regs()
7056 0x1600, 0x1658, 0x1680, 0x16d8, in bnx2_get_regs()
7057 0x1800, 0x1820, 0x1840, 0x1854, in bnx2_get_regs()
7058 0x1880, 0x1894, 0x1900, 0x1984, in bnx2_get_regs()
7059 0x1c00, 0x1c0c, 0x1c40, 0x1c54, in bnx2_get_regs()
7060 0x1c80, 0x1c94, 0x1d00, 0x1d84, in bnx2_get_regs()
7061 0x2000, 0x2030, 0x23c0, 0x2400, in bnx2_get_regs()
7062 0x2800, 0x2820, 0x2830, 0x2850, in bnx2_get_regs()
7063 0x2b40, 0x2c10, 0x2fc0, 0x3058, in bnx2_get_regs()
7064 0x3c00, 0x3c94, 0x4000, 0x4010, in bnx2_get_regs()
7065 0x4080, 0x4090, 0x43c0, 0x4458, in bnx2_get_regs()
7066 0x4c00, 0x4c18, 0x4c40, 0x4c54, in bnx2_get_regs()
7067 0x4fc0, 0x5010, 0x53c0, 0x5444, in bnx2_get_regs()
7068 0x5c00, 0x5c18, 0x5c80, 0x5c90, in bnx2_get_regs()
7069 0x5fc0, 0x6000, 0x6400, 0x6428, in bnx2_get_regs()
7070 0x6800, 0x6848, 0x684c, 0x6860, in bnx2_get_regs()
7071 0x6888, 0x6910, 0x8000 in bnx2_get_regs()
7074 regs->version = 0; in bnx2_get_regs()
7076 memset(p, 0, BNX2_REGDUMP_LEN); in bnx2_get_regs()
7081 i = 0; in bnx2_get_regs()
7082 offset = reg_boundaries[0]; in bnx2_get_regs()
7101 wol->supported = 0; in bnx2_get_wol()
7102 wol->wolopts = 0; in bnx2_get_wol()
7109 wol->wolopts = 0; in bnx2_get_wol()
7111 memset(&wol->sopass, 0, sizeof(wol->sopass)); in bnx2_get_wol()
7129 bp->wol = 0; in bnx2_set_wol()
7134 return 0; in bnx2_set_wol()
7180 return 0; in bnx2_nway_reset()
7197 return 0; in bnx2_get_eeprom_len()
7237 memset(coal, 0, sizeof(struct ethtool_coalesce)); in bnx2_get_coalesce()
7251 return 0; in bnx2_get_coalesce()
7262 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; in bnx2_set_coalesce()
7265 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7268 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7271 if (bp->rx_quick_cons_trip_int > 0xff) in bnx2_set_coalesce()
7272 bp->rx_quick_cons_trip_int = 0xff; in bnx2_set_coalesce()
7275 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; in bnx2_set_coalesce()
7278 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7281 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7284 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = in bnx2_set_coalesce()
7285 0xff; in bnx2_set_coalesce()
7289 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) in bnx2_set_coalesce()
7298 bnx2_init_nic(bp, 0); in bnx2_set_coalesce()
7302 return 0; in bnx2_set_coalesce()
7345 int rc = 0; in bnx2_change_ring_size()
7359 rc = bnx2_init_nic(bp, 0); in bnx2_change_ring_size()
7375 return 0; in bnx2_change_ring_size()
7402 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); in bnx2_get_pauseparam()
7403 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); in bnx2_get_pauseparam()
7404 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); in bnx2_get_pauseparam()
7412 bp->req_flow_ctrl = 0; in bnx2_set_pauseparam()
7431 return 0; in bnx2_set_pauseparam()
7544 8,0,8,8,8,8,8,8,8,8,
7545 4,0,4,4,4,4,4,4,4,4,
7552 8,0,8,8,8,8,8,8,8,8,
7590 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); in bnx2_self_test()
7598 if (bnx2_test_registers(bp) != 0) { in bnx2_self_test()
7599 buf[0] = 1; in bnx2_self_test()
7602 if (bnx2_test_memory(bp) != 0) { in bnx2_self_test()
7606 if ((buf[2] = bnx2_test_loopback(bp)) != 0) in bnx2_self_test()
7617 for (i = 0; i < 7; i++) { in bnx2_self_test()
7624 if (bnx2_test_nvram(bp) != 0) { in bnx2_self_test()
7628 if (bnx2_test_intr(bp) != 0) { in bnx2_self_test()
7633 if (bnx2_test_link(bp) != 0) { in bnx2_self_test()
7666 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); in bnx2_get_ethtool_stats()
7678 for (i = 0; i < BNX2_NUM_STATS; i++) { in bnx2_get_ethtool_stats()
7681 if (stats_len_arr[i] == 0) { in bnx2_get_ethtool_stats()
7683 buf[i] = 0; in bnx2_get_ethtool_stats()
7727 BNX2_WR(bp, BNX2_EMAC_LED, 0); in bnx2_set_phys_id()
7732 return 0; in bnx2_set_phys_id()
7752 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); in bnx2_set_features()
7757 return 0; in bnx2_set_features()
7774 channels->max_other = 0; in bnx2_get_channels()
7775 channels->max_combined = 0; in bnx2_get_channels()
7778 channels->other_count = 0; in bnx2_get_channels()
7779 channels->combined_count = 0; in bnx2_get_channels()
7788 int rc = 0; in bnx2_set_channels()
7864 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); in bnx2_ioctl()
7880 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()
7904 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_change_mac_addr()
7906 return 0; in bnx2_change_mac_addr()
7927 for (i = 0; i < bp->irq_nvecs; i++) { in poll_bnx2()
7956 if (bp->func == 0) { in bnx2_get_5709_media()
7958 case 0x4: in bnx2_get_5709_media()
7959 case 0x5: in bnx2_get_5709_media()
7960 case 0x6: in bnx2_get_5709_media()
7966 case 0x1: in bnx2_get_5709_media()
7967 case 0x2: in bnx2_get_5709_media()
7968 case 0x4: in bnx2_get_5709_media()
8034 #define BNX2_VPD_NVRAM_OFFSET 0x300 in bnx2_read_vpd_fw_ver()
8046 for (i = 0; i < BNX2_VPD_LEN; i += 4) in bnx2_read_vpd_fw_ver()
8051 if (j < 0) in bnx2_read_vpd_fw_ver()
8060 if (j < 0) in bnx2_read_vpd_fw_ver()
8084 bp->flags = 0; in bnx2_init_board()
8085 bp->phy_flags = 0; in bnx2_init_board()
8102 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { in bnx2_init_board()
8118 if (bp->pm_cap == 0) { in bnx2_init_board()
8135 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + in bnx2_init_board()
8164 if (bp->pcix_cap == 0) { in bnx2_init_board()
8192 if (dma_set_mask(&pdev->dev, dma_mask) == 0) { in bnx2_init_board()
8200 } else if ((rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) != 0) { in bnx2_init_board()
8252 for (i = 0; i < 3 && j < 24; i++) { in bnx2_init_board()
8255 if (i == 0) { in bnx2_init_board()
8263 bp->fw_version[j++] = (num / k) + '0'; in bnx2_init_board()
8264 skip0 = 0; in bnx2_init_board()
8277 for (i = 0; i < 30; i++) { in bnx2_init_board()
8292 for (i = 0; i < 3 && j < 28; i++) { in bnx2_init_board()
8301 bp->mac_addr[0] = (u8) (reg >> 8); in bnx2_init_board()
8346 bp->wol = 0; in bnx2_init_board()
8354 pdev->subsystem_device == 0x310c) in bnx2_init_board()
8376 bp->wol = 0; in bnx2_init_board()
8406 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) { in bnx2_init_board()
8413 if (amd_8132->revision >= 0x10 && in bnx2_init_board()
8414 amd_8132->revision <= 0x13) { in bnx2_init_board()
8425 timer_setup(&bp->timer, bnx2_timer, 0); in bnx2_init_board()
8437 return 0; in bnx2_init_board()
8480 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_del_napi()
8489 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_init_napi()
8493 if (i == 0) in bnx2_init_napi()
8534 if (rc < 0) in bnx2_init_one()
8580 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A', in bnx2_init_one()
8581 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4), in bnx2_init_one()
8582 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0), in bnx2_init_one()
8585 return 0; in bnx2_init_one()
8638 return 0; in bnx2_suspend()
8648 return 0; in bnx2_resume()
8655 return 0; in bnx2_resume()
8712 int err = 0; in bnx2_io_slot_reset()