Lines Matching +full:bit0 +full:- +full:7
49 * bit(7:2): real revision
103 #define ALX_PMCTRL_L1_BUFSRX_EN BIT(7)
121 #define ALX_MASTER_SYSALVTIMER_EN BIT(7)
125 /* bit0: MAC & DMA reset */
142 #define ALX_PHY_CTRL_IDDQ BIT(7)
145 /* bit0: out of dsp RST state */
168 #define ALX_MDIO_CLK_SEL_25MD128 7
266 #define ALX_MAC_CTRL_PCRCE BIT(7)
327 #define ALX_TXQ0_LSO_8023_EN BIT(7)
338 #define ALX_TXQ1_JUMBO_TSO_TH (7*1024)
354 #define ALX_RXQ0_IPV6_PARSE_EN BIT(7)
374 /* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
375 * rx-packet(1522) + delay-of-link(64)
479 #define ALX_ISR_TX_Q3 BIT(7)
490 /* re-send assert msg if SW no response */
568 #define ALX_WOL_CTRL4_PT7_EN BIT(7)
735 /* bit0: 25M switch to intnl OSC */
838 /********* dev 7 **********/
839 #define ALX_MIIEXT_ANEG 7
849 /* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */