28  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
43 /* Transmit Packet Descriptor, contains 4 32-bit words.
46  *   +----------------+----------------+
47  *   |    vlan-tag    |   buf length   |
48  *   +----------------+----------------+
50  *   +----------------+----------------+
52  *   +----------------+----------------+
54  *   +----------------+----------------+
56  * Word 2 and 3 combine to form a 64-bit buffer address
59  * if bit8 =='1', the definition is just for custom checksum offload.
64  *     checksum or LSO(TSO) offload.
68  *   0-+                                  0-+
75  *   7-+                                  7-+
77  *   9      General IPv4 checksum         9      General IPv4 checksum
78  *   10     General TCP checksum          10     General TCP checksum
79  *   11     General UDP checksum          11     General UDP checksum
86  *   18-+                                 18-+
93  *   25-+                                 25 |
94  *   26-+                                 26 |
98  *   30-+                                 30-+
151 				 * declared in register --- every
156 /* Receive Return Descriptor, contains 4 32-bit words.
159  *   +----------------+----------------+
161  *   +----------------+----------------+
163  *   +----------------+----------------+
165  *   +----------------+----------------+
167  *   +----------------+----------------+
171  *   0--+                                 0--+
178  *   7  |    IP payload checksum          7  |     VLAN tag
186  *   15-+                                 15-+
187  *   16-+                                 16-+
190  *   19-+                                 19 |     Protocol ID
191  *   20-+                                 20 |      (23:16)
194  *   23 |                                 23-+
196  *   25 |     Start index of RFD-ring     25-+
197  *   26 |         (31:20)                 26 |     RSS Q-num (27:25)
198  *   27 |                                 27-+
199  *   28 |                                 28-+
202  *   31-+                                 31-+
206  *   0--+
219  *   13-+
220  *   14      L4 Header checksum error
221  *   15      IPv4 checksum error
223  *   17-+
225  *   19-+
231  *   25      Incomplete packet due to insufficient rx-desc
259 /* non-ip packet */
405 	u64 rx_sz_127B;		/* 65-127 byte RX packets */
406 	u64 rx_sz_255B;		/* 128-255 byte RX packets */
407 	u64 rx_sz_511B;		/* 256-511 byte RX packets */
408 	u64 rx_sz_1023B;	/* 512-1023 byte RX packets */
409 	u64 rx_sz_1518B;	/* 1024-1518 byte RX packets */
429 	u64 tx_sz_127B;		/* 65-127 byte TX packets */
430 	u64 tx_sz_255B;		/* 128-255 byte TX packets */
431 	u64 tx_sz_511B;		/* 256-511 byte TX packets */
432 	u64 tx_sz_1023B;	/* 512-1023 byte TX packets */
433 	u64 tx_sz_1518B;	/* 1024-1518 byte TX packets */
486 	/* auto-neg advertisement or force mode config */
501 static inline int alx_hw_revision(struct alx_hw *hw)  in alx_hw_revision()  argument
503 	return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;  in alx_hw_revision()
506 static inline bool alx_hw_with_cr(struct alx_hw *hw)  in alx_hw_with_cr()  argument
508 	return hw->pdev->revision & 1;  in alx_hw_with_cr()
511 static inline bool alx_hw_giga(struct alx_hw *hw)  in alx_hw_giga()  argument
513 	return hw->pdev->device & 1;  in alx_hw_giga()
516 static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)  in alx_write_mem8()  argument
518 	writeb(val, hw->hw_addr + reg);  in alx_write_mem8()
521 static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)  in alx_write_mem16()  argument
523 	writew(val, hw->hw_addr + reg);  in alx_write_mem16()
526 static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)  in alx_read_mem16()  argument
528 	return readw(hw->hw_addr + reg);  in alx_read_mem16()
531 static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)  in alx_write_mem32()  argument
533 	writel(val, hw->hw_addr + reg);  in alx_write_mem32()
536 static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)  in alx_read_mem32()  argument
538 	return readl(hw->hw_addr + reg);  in alx_read_mem32()
541 static inline void alx_post_write(struct alx_hw *hw)  in alx_post_write()  argument
543 	readl(hw->hw_addr);  in alx_post_write()
546 int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
547 void alx_reset_phy(struct alx_hw *hw);
548 void alx_reset_pcie(struct alx_hw *hw);
549 void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
550 int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
551 void alx_post_phy_link(struct alx_hw *hw);
552 int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
553 int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
554 int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
555 int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
556 int alx_read_phy_link(struct alx_hw *hw);
557 int alx_clear_phy_intr(struct alx_hw *hw);
558 void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
559 void alx_start_mac(struct alx_hw *hw);
560 int alx_reset_mac(struct alx_hw *hw);
561 void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
562 bool alx_phy_configured(struct alx_hw *hw);
563 void alx_configure_basic(struct alx_hw *hw);
564 void alx_mask_msix(struct alx_hw *hw, int index, bool mask);
565 void alx_disable_rss(struct alx_hw *hw);
566 bool alx_get_phy_info(struct alx_hw *hw);
567 void alx_update_hw_stats(struct alx_hw *hw);