Lines Matching +full:0 +full:xfff7
26 #define AX88796C_PHY_ID 0x10
34 #define TX_HDR_SOP_DICF 0x8000
35 #define TX_HDR_SOP_CPHI 0x4000
36 #define TX_HDR_SOP_INT 0x2000
37 #define TX_HDR_SOP_MDEQ 0x1000
38 #define TX_HDR_SOP_PKTLEN 0x07FF
39 #define TX_HDR_SOP_SEQNUM 0xF800
40 #define TX_HDR_SOP_PKTLENBAR 0x07FF
42 #define TX_HDR_SEG_FS 0x8000
43 #define TX_HDR_SEG_LS 0x4000
44 #define TX_HDR_SEG_SEGNUM 0x3800
45 #define TX_HDR_SEG_SEGLEN 0x0700
46 #define TX_HDR_SEG_EOFST 0xC000
47 #define TX_HDR_SEG_SOFST 0x3800
48 #define TX_HDR_SEG_SEGLENBAR 0x07FF
50 #define TX_HDR_EOP_SEQNUM 0xF800
51 #define TX_HDR_EOP_PKTLEN 0x07FF
52 #define TX_HDR_EOP_SEQNUMBAR 0xF800
53 #define TX_HDR_EOP_PKTLENBAR 0x07FF
56 #define RX_HDR1_MCBC 0x8000
57 #define RX_HDR1_STUFF_PKT 0x4000
58 #define RX_HDR1_MII_ERR 0x2000
59 #define RX_HDR1_CRC_ERR 0x1000
60 #define RX_HDR1_PKT_LEN 0x07FF
62 #define RX_HDR2_SEQ_NUM 0xF800
63 #define RX_HDR2_PKT_LEN_BAR 0x7FFF
65 #define RX_HDR3_PE 0x8000
66 #define RX_HDR3_L3_TYPE_IPV4V6 0x6000
67 #define RX_HDR3_L3_TYPE_IP 0x4000
68 #define RX_HDR3_L3_TYPE_IPV6 0x2000
69 #define RX_HDR3_L4_TYPE_ICMPV6 0x1400
70 #define RX_HDR3_L4_TYPE_TCP 0x1000
71 #define RX_HDR3_L4_TYPE_IGMP 0x0c00
72 #define RX_HDR3_L4_TYPE_ICMP 0x0800
73 #define RX_HDR3_L4_TYPE_UDP 0x0400
74 #define RX_HDR3_L3_ERR 0x0200
75 #define RX_HDR3_L4_ERR 0x0100
77 #define RX_HDR3_STRIP 0x0008
78 #define RX_HDR3_VLAN_ID 0x0007
120 #define AX_FC_NONE 0
121 #define AX_FC_RX BIT(0)
126 #define AX_CAP_COMP BIT(0)
130 #define EVENT_INTR 0
139 illegal = 0,
152 #define P0_PSR (0x00)
154 #define PSR_RESET (0 << 15)
156 #define P0_BOR (0x02)
157 #define P0_FER (0x04)
158 #define FER_IPALM BIT(0)
165 #define FER_INTLO (0 << 10)
169 #define P0_ISR (0x06)
170 #define ISR_RXPKT BIT(0)
176 #define P0_IMR (0x08)
177 #define IMR_RXPKT BIT(0)
183 #define IMR_MASKALL (0xFFFF)
185 #define P0_WFCR (0x0A)
186 #define WFCR_PMEIND BIT(0) /* PME indication */
202 #define P0_PSCR (0x0C)
203 #define PSCR_PS_MASK (0xFFF0)
204 #define PSCR_PS_D0 (0)
205 #define PSCR_PS_D1 BIT(0)
224 #define P0_MACCR (0x0E)
225 #define MACCR_RXEN BIT(0) /* Enable RX */
226 #define MACCR_DUPLEX_FULL BIT(1) /* 1: Full, 0: Half */
227 #define MACCR_SPEED_100 BIT(2) /* 1: 100Mbps, 0: 10Mbps */
229 #define MACCR_RXFC_MASK 0xFFF7
231 #define MACCR_TXFC_MASK 0xFFEF
236 #define MACCR_PMM_MASK (0x1F00)
249 #define P0_TFBFCR (0x10)
250 #define TFBFCR_SCHE_FREE_PAGE 0xE07F
251 #define TFBFCR_FREE_PAGE_BITS 0x07
253 #define TFBFCR_SET_FREE_PAGE(x) (((x) & 0x3F) << TFBFCR_FREE_PAGE_BITS)
256 #define TX_FREEBUF_MASK 0x003F
257 #define TX_DPTSTART 0x4000
259 #define P0_TSNR (0x12)
262 #define TSNR_PKT_CNT(x) (((x) & 0x3F) << 8)
265 #define P0_RTDPR (0x14)
266 #define P0_RXBCR1 (0x16)
269 #define P0_RXBCR2 (0x18)
270 #define RXBCR2_PKT_MASK (0xFF)
271 #define RXBCR2_RXPC_MASK (0x7F)
275 #define P0_RTWCR (0x1A)
276 #define RTWCR_RXWC_MASK (0x3FFF)
278 #define P0_RCPHR (0x1C)
281 #define P1_RPPER (0x22)
282 #define RPPER_RXEN BIT(0)
283 #define P1_MRCR (0x28)
284 #define P1_MDR (0x2A)
285 #define P1_RMPR (0x2C)
286 #define P1_TMPR (0x2E)
287 #define P1_RXBSPCR (0x30)
288 #define RXBSPCR_STUF_WORD_CNT(x) (((x) & 0x7000) >> 12)
290 #define P1_MCR (0x32)
296 #define P2_CIR (0x42)
297 #define P2_PCR (0x44)
298 #define PCR_POLL_EN BIT(0)
302 #define P2_PHYSR (0x46)
303 #define P2_MDIODR (0x48)
304 #define P2_MDIOCR (0x4A)
305 #define MDIOCR_RADDR(x) ((x) & 0x1F)
306 #define MDIOCR_FADDR(x) (((x) & 0x1F) << 8)
310 #define P2_LCR0 (0x4C)
311 #define LCR_LED0_EN BIT(0)
327 #define P2_LCR1 (0x4E)
328 #define LCR_LED2_MASK (0xFF00)
329 #define LCR_LED2_EN BIT(0)
337 #define P2_IPGCR (0x50)
338 #define P2_CRIR (0x52)
339 #define P2_FLHWCR (0x54)
340 #define P2_RXCR (0x56)
341 #define RXCR_PRO BIT(0)
348 #define P2_JLCR (0x58)
349 #define P2_MPLR (0x5C)
352 #define P3_MACASR0 (0x62)
354 #define MACASR_LOWBYTE_MASK 0x00FF
355 #define MACASR_HIGH_BITS 0x08
356 #define P3_MACASR1 (0x64)
357 #define P3_MACASR2 (0x66)
358 #define P3_MFAR01 (0x68)
359 #define P3_MFAR_BASE (0x68)
362 #define P3_MFAR23 (0x6A)
363 #define P3_MFAR45 (0x6C)
364 #define P3_MFAR67 (0x6E)
365 #define P3_VID0FR (0x70)
366 #define P3_VID1FR (0x72)
367 #define P3_EECSR (0x74)
368 #define P3_EEDR (0x76)
369 #define P3_EECR (0x78)
370 #define EECR_ADDR_MASK (0x00FF)
378 #define P3_TPCR (0x7A)
379 #define TPCR_PATT_MASK (0xFF)
382 #define P3_TPLR (0x7C)
384 #define P4_SPICR (0x8A)
385 #define SPICR_RCEN BIT(0)
392 #define P4_SPIISMR (0x8C)
394 #define P4_COERCR0 (0x92)
395 #define COERCR0_RXIPCE BIT(0)
413 #define P4_COERCR1 (0x94)
414 #define COERCR1_IPCEDP BIT(0)
433 #define P4_COETCR0 (0x96)
434 #define COETCR0_TXIP BIT(0)
449 #define P4_COETCR1 (0x98)
450 #define COETCR1_TX64TE BIT(0)
453 #define P4_COECEDR (0x9A)
454 #define P4_L2CECR (0x9C)
457 #define P5_WFTR (0xA2)
458 #define WFTR_2MS (0x01)
459 #define WFTR_4MS (0x02)
460 #define WFTR_8MS (0x03)
461 #define WFTR_16MS (0x04)
462 #define WFTR_32MS (0x05)
463 #define WFTR_64MS (0x06)
464 #define WFTR_128MS (0x07)
465 #define WFTR_256MS (0x08)
466 #define WFTR_512MS (0x09)
467 #define WFTR_1024MS (0x0A)
468 #define WFTR_2048MS (0x0B)
469 #define WFTR_4096MS (0x0C)
470 #define WFTR_8192MS (0x0D)
471 #define WFTR_16384MS (0x0E)
472 #define WFTR_32768MS (0x0F)
473 #define P5_WFCCR (0xA4)
474 #define P5_WFCR03 (0xA6)
475 #define WFCR03_F0_EN BIT(0)
479 #define P5_WFCR47 (0xA8)
480 #define WFCR47_F4_EN BIT(0)
484 #define P5_WF0BMR0 (0xAA)
485 #define P5_WF0BMR1 (0xAC)
486 #define P5_WF0CR (0xAE)
487 #define P5_WF0OBR (0xB0)
488 #define P5_WF1BMR0 (0xB2)
489 #define P5_WF1BMR1 (0xB4)
490 #define P5_WF1CR (0xB6)
491 #define P5_WF1OBR (0xB8)
492 #define P5_WF2BMR0 (0xBA)
493 #define P5_WF2BMR1 (0xBC)
496 #define P6_WF2CR (0xC2)
497 #define P6_WF2OBR (0xC4)
498 #define P6_WF3BMR0 (0xC6)
499 #define P6_WF3BMR1 (0xC8)
500 #define P6_WF3CR (0xCA)
501 #define P6_WF3OBR (0xCC)
502 #define P6_WF4BMR0 (0xCE)
503 #define P6_WF4BMR1 (0xD0)
504 #define P6_WF4CR (0xD2)
505 #define P6_WF4OBR (0xD4)
506 #define P6_WF5BMR0 (0xD6)
507 #define P6_WF5BMR1 (0xD8)
508 #define P6_WF5CR (0xDA)
509 #define P6_WF5OBR (0xDC)
512 #define P7_WF6BMR0 (0xE2)
513 #define P7_WF6BMR1 (0xE4)
514 #define P7_WF6CR (0xE6)
515 #define P7_WF6OBR (0xE8)
516 #define P7_WF7BMR0 (0xEA)
517 #define P7_WF7BMR1 (0xEC)
518 #define P7_WF7CR (0xEE)
519 #define P7_WF7OBR (0xF0)
520 #define P7_WFR01 (0xF2)
521 #define P7_WFR23 (0xF4)
522 #define P7_WFR45 (0xF6)
523 #define P7_WFR67 (0xF8)
524 #define P7_WFPC0 (0xFA)
525 #define P7_WFPC1 (0xFC)
529 /* bit 15-11: flags, bit 10-0: packet length */
531 /* bit 15-11: sequence number, bit 11-0: packet length bar */
537 /* bit 10-0: segment length */
540 /* bit 10-0: segment length bar */
545 /* bit 15-11: sequence number, bit 10-0: packet length */
547 /* bit 15-11: sequence number bar, bit 10-0: packet length bar */