50 		dev_dbg(pdata->dev, "multi %s interrupts enabled\n",  in xgbe_config_multi_msi()
81 		dev_dbg(pdata->dev, "single %s interrupt enabled\n",  in xgbe_config_irqs()
88 		dev_dbg(pdata->dev, " dev irq=%d\n", pdata->dev_irq);  in xgbe_config_irqs()
89 		dev_dbg(pdata->dev, " ecc irq=%d\n", pdata->ecc_irq);  in xgbe_config_irqs()
90 		dev_dbg(pdata->dev, " i2c irq=%d\n", pdata->i2c_irq);  in xgbe_config_irqs()
91 		dev_dbg(pdata->dev, "  an irq=%d\n", pdata->an_irq);  in xgbe_config_irqs()
93 			dev_dbg(pdata->dev, " dma%u irq=%d\n",  in xgbe_config_irqs()
153 		dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);  in xgbe_pci_probe()
154 		dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);  in xgbe_pci_probe()
155 		dev_dbg(dev, "xi2c_regs  = %p\n", pdata->xi2c_regs);  in xgbe_pci_probe()
165 		dev_dbg(dev, "xpcs_regs  = %p\n", pdata->xpcs_regs);  in xgbe_pci_probe()
223 		dev_dbg(dev, "xpcs window def  = %#010x\n",  in xgbe_pci_probe()
225 		dev_dbg(dev, "xpcs window sel  = %#010x\n",  in xgbe_pci_probe()
227 		dev_dbg(dev, "xpcs window      = %#010x\n",  in xgbe_pci_probe()
229 		dev_dbg(dev, "xpcs window size = %#010x\n",  in xgbe_pci_probe()
231 		dev_dbg(dev, "xpcs window mask = %#010x\n",  in xgbe_pci_probe()
273 		dev_dbg(dev, "port property 0 = %#010x\n", pdata->pp0);  in xgbe_pci_probe()
274 		dev_dbg(dev, "port property 1 = %#010x\n", pdata->pp1);  in xgbe_pci_probe()
275 		dev_dbg(dev, "port property 2 = %#010x\n", pdata->pp2);  in xgbe_pci_probe()
276 		dev_dbg(dev, "port property 3 = %#010x\n", pdata->pp3);  in xgbe_pci_probe()
277 		dev_dbg(dev, "port property 4 = %#010x\n", pdata->pp4);  in xgbe_pci_probe()
290 		dev_dbg(dev, "max tx/rx channel count = %u/%u\n",  in xgbe_pci_probe()
293 		dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n",  in xgbe_pci_probe()
312 		dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n",  in xgbe_pci_probe()