Lines Matching refs:pdata
20 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) in xgbe_get_max_frame() argument
22 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
25 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, in xgbe_usec_to_riwt() argument
33 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
48 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, in xgbe_riwt_to_usec() argument
56 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
71 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata) in xgbe_config_pbl_val() argument
77 pbl = pdata->pbl; in xgbe_config_pbl_val()
79 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
84 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
85 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
88 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
89 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
92 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
93 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
100 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) in xgbe_config_osp_mode() argument
104 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
105 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
108 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
109 pdata->tx_osp_mode); in xgbe_config_osp_mode()
115 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_rsf_mode() argument
119 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
120 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); in xgbe_config_rsf_mode()
125 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_tsf_mode() argument
129 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
130 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); in xgbe_config_tsf_mode()
135 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, in xgbe_config_rx_threshold() argument
140 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
141 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); in xgbe_config_rx_threshold()
146 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, in xgbe_config_tx_threshold() argument
151 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
152 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); in xgbe_config_tx_threshold()
157 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_rx_coalesce() argument
161 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
162 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
165 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
166 pdata->rx_riwt); in xgbe_config_rx_coalesce()
172 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_tx_coalesce() argument
177 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_buffer_size() argument
181 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
182 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
185 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
186 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
190 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) in xgbe_config_tso_mode() argument
194 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
195 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
198 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); in xgbe_config_tso_mode()
202 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) in xgbe_config_sph_mode() argument
206 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
207 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
210 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
213 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); in xgbe_config_sph_mode()
216 static void xgbe_disable_sph_mode(struct xgbe_prv_data *pdata) in xgbe_disable_sph_mode() argument
220 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_sph_mode()
221 if (!pdata->channel[i]->rx_ring) in xgbe_disable_sph_mode()
224 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0); in xgbe_disable_sph_mode()
228 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, in xgbe_write_rss_reg() argument
234 mutex_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
236 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { in xgbe_write_rss_reg()
241 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); in xgbe_write_rss_reg()
243 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); in xgbe_write_rss_reg()
244 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); in xgbe_write_rss_reg()
245 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); in xgbe_write_rss_reg()
246 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); in xgbe_write_rss_reg()
250 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) in xgbe_write_rss_reg()
259 mutex_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
264 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) in xgbe_write_rss_hash_key() argument
266 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); in xgbe_write_rss_hash_key()
267 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
271 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, in xgbe_write_rss_hash_key()
280 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) in xgbe_write_rss_lookup_table() argument
285 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
286 ret = xgbe_write_rss_reg(pdata, in xgbe_write_rss_lookup_table()
288 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
296 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) in xgbe_set_rss_hash_key() argument
298 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
300 return xgbe_write_rss_hash_key(pdata); in xgbe_set_rss_hash_key()
303 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, in xgbe_set_rss_lookup_table() argument
308 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
309 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
311 return xgbe_write_rss_lookup_table(pdata); in xgbe_set_rss_lookup_table()
314 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) in xgbe_enable_rss() argument
318 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
322 ret = xgbe_write_rss_hash_key(pdata); in xgbe_enable_rss()
327 ret = xgbe_write_rss_lookup_table(pdata); in xgbe_enable_rss()
332 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
335 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); in xgbe_enable_rss()
340 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) in xgbe_disable_rss() argument
342 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
345 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); in xgbe_disable_rss()
350 static void xgbe_config_rss(struct xgbe_prv_data *pdata) in xgbe_config_rss() argument
354 if (!pdata->hw_feat.rss) in xgbe_config_rss()
357 if (pdata->netdev->features & NETIF_F_RXHASH) in xgbe_config_rss()
358 ret = xgbe_enable_rss(pdata); in xgbe_config_rss()
360 ret = xgbe_disable_rss(pdata); in xgbe_config_rss()
363 netdev_err(pdata->netdev, in xgbe_config_rss()
367 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, in xgbe_is_pfc_queue() argument
374 if (pdata->prio2q_map[prio] != queue) in xgbe_is_pfc_queue()
378 tc = pdata->ets->prio_tc[prio]; in xgbe_is_pfc_queue()
381 if (pdata->pfc->pfc_en & (1 << tc)) in xgbe_is_pfc_queue()
388 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata) in xgbe_set_vxlan_id() argument
391 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); in xgbe_set_vxlan_id()
393 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", in xgbe_set_vxlan_id()
394 pdata->vxlan_port); in xgbe_set_vxlan_id()
397 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata) in xgbe_enable_vxlan() argument
399 if (!pdata->hw_feat.vxn) in xgbe_enable_vxlan()
403 xgbe_set_vxlan_id(pdata); in xgbe_enable_vxlan()
406 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1); in xgbe_enable_vxlan()
409 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0); in xgbe_enable_vxlan()
410 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1); in xgbe_enable_vxlan()
412 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); in xgbe_enable_vxlan()
415 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata) in xgbe_disable_vxlan() argument
417 if (!pdata->hw_feat.vxn) in xgbe_disable_vxlan()
421 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0); in xgbe_disable_vxlan()
424 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0); in xgbe_disable_vxlan()
427 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0); in xgbe_disable_vxlan()
429 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); in xgbe_disable_vxlan()
432 static unsigned int xgbe_get_fc_queue_count(struct xgbe_prv_data *pdata) in xgbe_get_fc_queue_count() argument
437 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30) in xgbe_get_fc_queue_count()
440 return min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_get_fc_queue_count()
443 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_tx_flow_control() argument
449 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
450 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); in xgbe_disable_tx_flow_control()
453 q_count = xgbe_get_fc_queue_count(pdata); in xgbe_disable_tx_flow_control()
456 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_disable_tx_flow_control()
458 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_disable_tx_flow_control()
466 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_tx_flow_control() argument
468 struct ieee_pfc *pfc = pdata->pfc; in xgbe_enable_tx_flow_control()
469 struct ieee_ets *ets = pdata->ets; in xgbe_enable_tx_flow_control()
474 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
477 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
480 if (xgbe_is_pfc_queue(pdata, i)) in xgbe_enable_tx_flow_control()
487 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); in xgbe_enable_tx_flow_control()
489 netif_dbg(pdata, drv, pdata->netdev, in xgbe_enable_tx_flow_control()
495 q_count = xgbe_get_fc_queue_count(pdata); in xgbe_enable_tx_flow_control()
498 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_enable_tx_flow_control()
505 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_enable_tx_flow_control()
513 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_rx_flow_control() argument
515 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); in xgbe_disable_rx_flow_control()
520 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_rx_flow_control() argument
522 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); in xgbe_enable_rx_flow_control()
527 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_tx_flow_control() argument
529 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_tx_flow_control()
531 if (pdata->tx_pause || (pfc && pfc->pfc_en)) in xgbe_config_tx_flow_control()
532 xgbe_enable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
534 xgbe_disable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
539 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_rx_flow_control() argument
541 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_rx_flow_control()
543 if (pdata->rx_pause || (pfc && pfc->pfc_en)) in xgbe_config_rx_flow_control()
544 xgbe_enable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
546 xgbe_disable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
551 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_flow_control() argument
553 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_flow_control()
555 xgbe_config_tx_flow_control(pdata); in xgbe_config_flow_control()
556 xgbe_config_rx_flow_control(pdata); in xgbe_config_flow_control()
558 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, in xgbe_config_flow_control()
562 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_dma_interrupts() argument
568 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
569 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, in xgbe_enable_dma_interrupts()
570 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
572 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
574 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
575 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
604 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
616 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
625 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mtl_interrupts() argument
630 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
633 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); in xgbe_enable_mtl_interrupts()
634 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); in xgbe_enable_mtl_interrupts()
637 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); in xgbe_enable_mtl_interrupts()
641 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mac_interrupts() argument
648 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); in xgbe_enable_mac_interrupts()
651 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
652 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
655 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); in xgbe_enable_mac_interrupts()
658 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_ecc_interrupts() argument
662 if (!pdata->vdata->ecc_support) in xgbe_enable_ecc_interrupts()
666 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); in xgbe_enable_ecc_interrupts()
667 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); in xgbe_enable_ecc_interrupts()
677 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_enable_ecc_interrupts()
680 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) in xgbe_disable_ecc_ded() argument
684 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); in xgbe_disable_ecc_ded()
691 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_disable_ecc_ded()
694 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, in xgbe_disable_ecc_sec() argument
699 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); in xgbe_disable_ecc_sec()
714 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_disable_ecc_sec()
717 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) in xgbe_set_speed() argument
738 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) in xgbe_set_speed()
739 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); in xgbe_set_speed()
744 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_stripping() argument
747 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); in xgbe_enable_rx_vlan_stripping()
750 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); in xgbe_enable_rx_vlan_stripping()
753 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); in xgbe_enable_rx_vlan_stripping()
756 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); in xgbe_enable_rx_vlan_stripping()
759 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); in xgbe_enable_rx_vlan_stripping()
764 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_stripping() argument
766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); in xgbe_disable_rx_vlan_stripping()
771 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_filtering() argument
774 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); in xgbe_enable_rx_vlan_filtering()
777 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); in xgbe_enable_rx_vlan_filtering()
780 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); in xgbe_enable_rx_vlan_filtering()
783 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); in xgbe_enable_rx_vlan_filtering()
791 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); in xgbe_enable_rx_vlan_filtering()
796 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_filtering() argument
799 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); in xgbe_disable_rx_vlan_filtering()
828 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) in xgbe_update_vlan_hash_table() argument
836 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { in xgbe_update_vlan_hash_table()
845 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); in xgbe_update_vlan_hash_table()
850 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, in xgbe_set_promiscuous_mode() argument
855 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) in xgbe_set_promiscuous_mode()
858 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", in xgbe_set_promiscuous_mode()
860 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); in xgbe_set_promiscuous_mode()
864 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
866 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_set_promiscuous_mode()
867 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
873 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, in xgbe_set_all_multicast_mode() argument
878 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) in xgbe_set_all_multicast_mode()
881 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", in xgbe_set_all_multicast_mode()
883 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); in xgbe_set_all_multicast_mode()
888 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, in xgbe_set_mac_reg() argument
907 netif_dbg(pdata, drv, pdata->netdev, in xgbe_set_mac_reg()
914 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); in xgbe_set_mac_reg()
916 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); in xgbe_set_mac_reg()
920 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) in xgbe_set_mac_addn_addrs() argument
922 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_addn_addrs()
928 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
931 xgbe_set_promiscuous_mode(pdata, 1); in xgbe_set_mac_addn_addrs()
934 xgbe_set_mac_reg(pdata, ha, &mac_reg); in xgbe_set_mac_addn_addrs()
939 xgbe_set_all_multicast_mode(pdata, 1); in xgbe_set_mac_addn_addrs()
942 xgbe_set_mac_reg(pdata, ha, &mac_reg); in xgbe_set_mac_addn_addrs()
950 xgbe_set_mac_reg(pdata, NULL, &mac_reg); in xgbe_set_mac_addn_addrs()
953 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) in xgbe_set_mac_hash_table() argument
955 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_hash_table()
963 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); in xgbe_set_mac_hash_table()
964 hash_table_count = pdata->hw_feat.hash_table_size / 32; in xgbe_set_mac_hash_table()
983 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); in xgbe_set_mac_hash_table()
988 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) in xgbe_add_mac_addresses() argument
990 if (pdata->hw_feat.hash_table_size) in xgbe_add_mac_addresses()
991 xgbe_set_mac_hash_table(pdata); in xgbe_add_mac_addresses()
993 xgbe_set_mac_addn_addrs(pdata); in xgbe_add_mac_addresses()
998 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, const u8 *addr) in xgbe_set_mac_address() argument
1006 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); in xgbe_set_mac_address()
1007 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); in xgbe_set_mac_address()
1012 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) in xgbe_config_rx_mode() argument
1014 struct net_device *netdev = pdata->netdev; in xgbe_config_rx_mode()
1020 xgbe_set_promiscuous_mode(pdata, pr_mode); in xgbe_config_rx_mode()
1021 xgbe_set_all_multicast_mode(pdata, am_mode); in xgbe_config_rx_mode()
1023 xgbe_add_mac_addresses(pdata); in xgbe_config_rx_mode()
1028 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_clr_gpio() argument
1035 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_clr_gpio()
1038 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_clr_gpio()
1043 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_set_gpio() argument
1050 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_set_gpio()
1053 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_set_gpio()
1058 static unsigned int xgbe_get_mmd_address(struct xgbe_prv_data *pdata, in xgbe_get_mmd_address() argument
1063 (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_get_mmd_address()
1066 static void xgbe_get_pcs_index_and_offset(struct xgbe_prv_data *pdata, in xgbe_get_pcs_index_and_offset() argument
1081 *index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_get_pcs_index_and_offset()
1082 *offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_get_pcs_index_and_offset()
1085 static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs_v3() argument
1093 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg); in xgbe_read_mmd_regs_v3()
1095 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); in xgbe_read_mmd_regs_v3()
1097 smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg; in xgbe_read_mmd_regs_v3()
1102 ret = amd_smn_read(0, pdata->smn_base + offset, &mmd_data); in xgbe_read_mmd_regs_v3()
1112 static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs_v3() argument
1121 dev = pdata->pcidev; in xgbe_write_mmd_regs_v3()
1122 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg); in xgbe_write_mmd_regs_v3()
1124 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); in xgbe_write_mmd_regs_v3()
1126 smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg; in xgbe_write_mmd_regs_v3()
1133 ret = amd_smn_read(0, pdata->smn_base + offset, &pci_mmd_data); in xgbe_write_mmd_regs_v3()
1156 ret = amd_smn_write(0, (pdata->smn_base + offset), pci_mmd_data); in xgbe_write_mmd_regs_v3()
1163 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs_v2() argument
1170 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg); in xgbe_read_mmd_regs_v2()
1172 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); in xgbe_read_mmd_regs_v2()
1174 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1175 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1176 mmd_data = XPCS16_IOREAD(pdata, offset); in xgbe_read_mmd_regs_v2()
1177 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1182 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs_v2() argument
1188 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg); in xgbe_write_mmd_regs_v2()
1190 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); in xgbe_write_mmd_regs_v2()
1192 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1193 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1194 XPCS16_IOWRITE(pdata, offset, mmd_data); in xgbe_write_mmd_regs_v2()
1195 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1198 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs_v1() argument
1205 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg); in xgbe_read_mmd_regs_v1()
1216 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1217 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_read_mmd_regs_v1()
1218 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); in xgbe_read_mmd_regs_v1()
1219 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1224 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs_v1() argument
1230 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg); in xgbe_write_mmd_regs_v1()
1241 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1242 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_write_mmd_regs_v1()
1243 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); in xgbe_write_mmd_regs_v1()
1244 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1247 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs() argument
1250 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1252 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); in xgbe_read_mmd_regs()
1256 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); in xgbe_read_mmd_regs()
1259 return xgbe_read_mmd_regs_v3(pdata, prtad, mmd_reg); in xgbe_read_mmd_regs()
1263 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs() argument
1266 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1268 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); in xgbe_write_mmd_regs()
1271 return xgbe_write_mmd_regs_v3(pdata, prtad, mmd_reg, mmd_data); in xgbe_write_mmd_regs()
1275 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); in xgbe_write_mmd_regs()
1302 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, in xgbe_write_ext_mii_regs() argument
1307 reinit_completion(&pdata->mdio_complete); in xgbe_write_ext_mii_regs()
1309 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_write_ext_mii_regs()
1315 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_write_ext_mii_regs()
1317 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_write_ext_mii_regs()
1318 netdev_err(pdata->netdev, "mdio write operation timed out\n"); in xgbe_write_ext_mii_regs()
1325 static int xgbe_write_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, in xgbe_write_ext_mii_regs_c22() argument
1332 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); in xgbe_write_ext_mii_regs_c22()
1335 static int xgbe_write_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, in xgbe_write_ext_mii_regs_c45() argument
1342 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); in xgbe_write_ext_mii_regs_c45()
1345 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, in xgbe_read_ext_mii_regs() argument
1350 reinit_completion(&pdata->mdio_complete); in xgbe_read_ext_mii_regs()
1352 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_read_ext_mii_regs()
1357 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_read_ext_mii_regs()
1359 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_read_ext_mii_regs()
1360 netdev_err(pdata->netdev, "mdio read operation timed out\n"); in xgbe_read_ext_mii_regs()
1364 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); in xgbe_read_ext_mii_regs()
1367 static int xgbe_read_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, in xgbe_read_ext_mii_regs_c22() argument
1374 return xgbe_read_ext_mii_regs(pdata, mdio_sca); in xgbe_read_ext_mii_regs_c22()
1377 static int xgbe_read_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, in xgbe_read_ext_mii_regs_c45() argument
1384 return xgbe_read_ext_mii_regs(pdata, mdio_sca); in xgbe_read_ext_mii_regs_c45()
1387 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, in xgbe_set_ext_mii_mode() argument
1390 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); in xgbe_set_ext_mii_mode()
1404 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); in xgbe_set_ext_mii_mode()
1414 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_disable_rx_csum() argument
1416 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); in xgbe_disable_rx_csum()
1421 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_enable_rx_csum() argument
1423 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); in xgbe_enable_rx_csum()
1477 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, in xgbe_rx_desc_reset() argument
1481 unsigned int rx_usecs = pdata->rx_usecs; in xgbe_rx_desc_reset()
1482 unsigned int rx_frames = pdata->rx_frames; in xgbe_rx_desc_reset()
1527 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_rx_desc_init() local
1540 xgbe_rx_desc_reset(pdata, rdata, i); in xgbe_rx_desc_init()
1564 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_tx_start_xmit() local
1577 if (pdata->tx_usecs && !channel->tx_timer_active) { in xgbe_tx_start_xmit()
1580 jiffies + usecs_to_jiffies(pdata->tx_usecs)); in xgbe_tx_start_xmit()
1588 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_xmit() local
1636 if (!pdata->tx_frames) in xgbe_dev_xmit()
1638 else if (tx_packets > pdata->tx_frames) in xgbe_dev_xmit()
1640 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) in xgbe_dev_xmit()
1651 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1671 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1730 pdata->ext_stats.tx_tso_packets += tx_packets; in xgbe_dev_xmit()
1749 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; in xgbe_dev_xmit()
1788 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; in xgbe_dev_xmit()
1789 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; in xgbe_dev_xmit()
1802 if (netif_msg_tx_queued(pdata)) in xgbe_dev_xmit()
1803 xgbe_dump_tx_desc(pdata, ring, start_index, in xgbe_dev_xmit()
1811 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, in xgbe_dev_xmit()
1826 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read() local
1831 struct net_device *netdev = pdata->netdev; in xgbe_dev_read()
1846 if (netif_msg_rx_status(pdata)) in xgbe_dev_read()
1847 xgbe_dump_rx_desc(pdata, ring, ring->cur); in xgbe_dev_read()
1875 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
1924 pdata->ext_stats.rx_vxlan_packets++; in xgbe_dev_read()
1939 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); in xgbe_dev_read()
1950 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", in xgbe_dev_read()
1962 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
1968 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
1975 pdata->ext_stats.rxq_packets[channel->queue_index]++; in xgbe_dev_read()
1976 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; in xgbe_dev_read()
2079 static int __xgbe_exit(struct xgbe_prv_data *pdata) in __xgbe_exit() argument
2086 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); in __xgbe_exit()
2090 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
2101 static int xgbe_exit(struct xgbe_prv_data *pdata) in xgbe_exit() argument
2108 ret = __xgbe_exit(pdata); in xgbe_exit()
2112 return __xgbe_exit(pdata); in xgbe_exit()
2115 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) in xgbe_flush_tx_queues() argument
2119 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
2122 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
2123 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); in xgbe_flush_tx_queues()
2126 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
2128 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
2139 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) in xgbe_config_dma_bus() argument
2143 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); in xgbe_config_dma_bus()
2150 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
2151 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
2152 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
2153 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
2155 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); in xgbe_config_dma_bus()
2158 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
2159 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, in xgbe_config_dma_bus()
2160 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
2162 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
2163 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, in xgbe_config_dma_bus()
2164 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
2167 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) in xgbe_config_dma_cache() argument
2169 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
2170 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
2171 if (pdata->awarcr) in xgbe_config_dma_cache()
2172 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
2175 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) in xgbe_config_mtl_mode() argument
2180 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); in xgbe_config_mtl_mode()
2183 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
2184 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_mtl_mode()
2186 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); in xgbe_config_mtl_mode()
2190 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); in xgbe_config_mtl_mode()
2193 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_queue_flow_control_threshold() argument
2200 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_queue_flow_control_threshold()
2202 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { in xgbe_queue_flow_control_threshold()
2204 rfa = pdata->pfc_rfa; in xgbe_queue_flow_control_threshold()
2218 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
2219 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
2225 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
2226 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
2232 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
2233 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
2254 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
2255 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
2258 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_calculate_flow_control_threshold() argument
2264 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
2267 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); in xgbe_calculate_flow_control_threshold()
2271 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) in xgbe_config_flow_control_threshold() argument
2275 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
2276 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, in xgbe_config_flow_control_threshold()
2277 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
2278 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, in xgbe_config_flow_control_threshold()
2279 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
2283 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_tx_fifo_size() argument
2286 return min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
2287 pdata->hw_feat.tx_fifo_size); in xgbe_get_tx_fifo_size()
2290 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_rx_fifo_size() argument
2293 return min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
2294 pdata->hw_feat.rx_fifo_size); in xgbe_get_rx_fifo_size()
2343 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) in xgbe_get_pfc_delay() argument
2348 if (pdata->pfc->delay) in xgbe_get_pfc_delay()
2349 return pdata->pfc->delay / 8; in xgbe_get_pfc_delay()
2352 delay = xgbe_get_max_frame(pdata); in xgbe_get_pfc_delay()
2367 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) in xgbe_get_pfc_queues() argument
2372 if (!pdata->pfc->pfc_en) in xgbe_get_pfc_queues()
2376 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_get_pfc_queues()
2378 if (!xgbe_is_pfc_queue(pdata, i)) in xgbe_get_pfc_queues()
2381 pdata->pfcq[i] = 1; in xgbe_get_pfc_queues()
2388 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, in xgbe_calculate_dcb_fifo() argument
2397 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_calculate_dcb_fifo()
2398 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_calculate_dcb_fifo()
2399 pfc_count = xgbe_get_pfc_queues(pdata); in xgbe_calculate_dcb_fifo()
2413 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); in xgbe_calculate_dcb_fifo()
2414 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); in xgbe_calculate_dcb_fifo()
2416 if (pdata->pfc_rfa > q_fifo_size) { in xgbe_calculate_dcb_fifo()
2417 addn_fifo = pdata->pfc_rfa - q_fifo_size; in xgbe_calculate_dcb_fifo()
2434 if (!pdata->pfcq[i] || !addn_fifo) in xgbe_calculate_dcb_fifo()
2438 netdev_warn(pdata->netdev, in xgbe_calculate_dcb_fifo()
2459 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_tx_fifo_size() argument
2465 fifo_size = xgbe_get_tx_fifo_size(pdata); in xgbe_config_tx_fifo_size()
2467 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
2469 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_fifo_size()
2470 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); in xgbe_config_tx_fifo_size()
2472 netif_info(pdata, drv, pdata->netdev, in xgbe_config_tx_fifo_size()
2474 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
2477 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_fifo_size() argument
2485 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); in xgbe_config_rx_fifo_size()
2486 pdata->pfc_rfa = 0; in xgbe_config_rx_fifo_size()
2488 fifo_size = xgbe_get_rx_fifo_size(pdata); in xgbe_config_rx_fifo_size()
2489 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2492 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
2494 if (pdata->pfc && pdata->ets) in xgbe_config_rx_fifo_size()
2495 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); in xgbe_config_rx_fifo_size()
2499 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2500 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); in xgbe_config_rx_fifo_size()
2502 xgbe_calculate_flow_control_threshold(pdata, fifo); in xgbe_config_rx_fifo_size()
2503 xgbe_config_flow_control_threshold(pdata); in xgbe_config_rx_fifo_size()
2505 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { in xgbe_config_rx_fifo_size()
2506 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2507 "%u Rx hardware queues\n", pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2508 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2509 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2513 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2515 pdata->rx_q_count, in xgbe_config_rx_fifo_size()
2520 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) in xgbe_config_queue_mapping() argument
2531 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2532 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2534 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
2536 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2538 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
2540 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2544 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2546 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
2548 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2553 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
2562 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2565 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2569 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2572 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2580 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2588 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2591 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2594 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2601 static void xgbe_config_tc(struct xgbe_prv_data *pdata) in xgbe_config_tc() argument
2606 netdev_reset_tc(pdata->netdev); in xgbe_config_tc()
2607 if (!pdata->num_tcs) in xgbe_config_tc()
2610 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); in xgbe_config_tc()
2612 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { in xgbe_config_tc()
2613 while ((queue < pdata->tx_q_count) && in xgbe_config_tc()
2614 (pdata->q2tc_map[queue] == i)) in xgbe_config_tc()
2617 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", in xgbe_config_tc()
2619 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); in xgbe_config_tc()
2623 if (!pdata->ets) in xgbe_config_tc()
2627 netdev_set_prio_tc_map(pdata->netdev, prio, in xgbe_config_tc()
2628 pdata->ets->prio_tc[prio]); in xgbe_config_tc()
2631 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) in xgbe_config_dcb_tc() argument
2633 struct ieee_ets *ets = pdata->ets; in xgbe_config_dcb_tc()
2644 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); in xgbe_config_dcb_tc()
2647 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; in xgbe_config_dcb_tc()
2652 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_dcb_tc()
2661 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", in xgbe_config_dcb_tc()
2664 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_config_dcb_tc()
2669 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_dcb_tc()
2674 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2676 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_dcb_tc()
2683 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2685 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_dcb_tc()
2687 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, in xgbe_config_dcb_tc()
2693 xgbe_config_tc(pdata); in xgbe_config_dcb_tc()
2696 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) in xgbe_config_dcb_pfc() argument
2698 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2700 netif_tx_stop_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2703 pdata->hw_if.disable_rx(pdata); in xgbe_config_dcb_pfc()
2706 xgbe_config_rx_fifo_size(pdata); in xgbe_config_dcb_pfc()
2707 xgbe_config_flow_control(pdata); in xgbe_config_dcb_pfc()
2709 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2711 pdata->hw_if.enable_rx(pdata); in xgbe_config_dcb_pfc()
2714 netif_tx_start_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2718 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) in xgbe_config_mac_address() argument
2720 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); in xgbe_config_mac_address()
2723 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2724 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); in xgbe_config_mac_address()
2725 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); in xgbe_config_mac_address()
2726 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); in xgbe_config_mac_address()
2730 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) in xgbe_config_jumbo_enable() argument
2734 if (pdata->netdev->mtu > XGMAC_JUMBO_PACKET_MTU) { in xgbe_config_jumbo_enable()
2735 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSL, in xgbe_config_jumbo_enable()
2737 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 1); in xgbe_config_jumbo_enable()
2738 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 1); in xgbe_config_jumbo_enable()
2739 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 1); in xgbe_config_jumbo_enable()
2741 val = pdata->netdev->mtu > XGMAC_STD_PACKET_MTU ? 1 : 0; in xgbe_config_jumbo_enable()
2742 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 0); in xgbe_config_jumbo_enable()
2743 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 0); in xgbe_config_jumbo_enable()
2744 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 0); in xgbe_config_jumbo_enable()
2745 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); in xgbe_config_jumbo_enable()
2749 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) in xgbe_config_mac_speed() argument
2751 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2754 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) in xgbe_config_checksum_offload() argument
2756 if (pdata->netdev->features & NETIF_F_RXCSUM) in xgbe_config_checksum_offload()
2757 xgbe_enable_rx_csum(pdata); in xgbe_config_checksum_offload()
2759 xgbe_disable_rx_csum(pdata); in xgbe_config_checksum_offload()
2762 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) in xgbe_config_vlan_support() argument
2765 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); in xgbe_config_vlan_support()
2766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); in xgbe_config_vlan_support()
2769 xgbe_update_vlan_hash_table(pdata); in xgbe_config_vlan_support()
2771 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_config_vlan_support()
2772 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2774 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2776 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) in xgbe_config_vlan_support()
2777 xgbe_enable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2779 xgbe_disable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2782 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) in xgbe_mmc_read() argument
2787 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2816 val = XGMAC_IOREAD(pdata, reg_lo); in xgbe_mmc_read()
2819 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); in xgbe_mmc_read()
2824 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_tx_mmc_int() argument
2826 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2827 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); in xgbe_tx_mmc_int()
2831 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_tx_mmc_int()
2835 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_tx_mmc_int()
2839 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2843 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2847 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_tx_mmc_int()
2851 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_tx_mmc_int()
2855 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_tx_mmc_int()
2859 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_tx_mmc_int()
2863 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_tx_mmc_int()
2867 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_tx_mmc_int()
2871 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2875 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2879 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2883 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_tx_mmc_int()
2887 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_tx_mmc_int()
2891 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_tx_mmc_int()
2895 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_tx_mmc_int()
2899 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_tx_mmc_int()
2902 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_rx_mmc_int() argument
2904 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
2905 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); in xgbe_rx_mmc_int()
2909 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_rx_mmc_int()
2913 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_rx_mmc_int()
2917 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_rx_mmc_int()
2921 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2925 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2929 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_rx_mmc_int()
2933 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_rx_mmc_int()
2937 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_rx_mmc_int()
2941 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_rx_mmc_int()
2945 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_rx_mmc_int()
2949 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_rx_mmc_int()
2953 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_rx_mmc_int()
2957 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_rx_mmc_int()
2961 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_rx_mmc_int()
2965 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_rx_mmc_int()
2969 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_rx_mmc_int()
2973 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2977 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_rx_mmc_int()
2981 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_rx_mmc_int()
2985 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_rx_mmc_int()
2989 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_rx_mmc_int()
2993 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_rx_mmc_int()
2997 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_rx_mmc_int()
3000 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) in xgbe_read_mmc_stats() argument
3002 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
3005 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); in xgbe_read_mmc_stats()
3008 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
3011 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
3014 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3017 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3020 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
3023 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
3026 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
3029 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
3032 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
3035 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
3038 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3041 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3044 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3047 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_read_mmc_stats()
3050 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
3053 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_read_mmc_stats()
3056 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
3059 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_read_mmc_stats()
3062 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
3065 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
3068 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
3071 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3074 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3077 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_read_mmc_stats()
3080 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_read_mmc_stats()
3083 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_read_mmc_stats()
3086 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_read_mmc_stats()
3089 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_read_mmc_stats()
3092 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
3095 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
3098 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
3101 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
3104 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
3107 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
3110 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3113 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_read_mmc_stats()
3116 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_read_mmc_stats()
3119 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
3122 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_read_mmc_stats()
3125 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_read_mmc_stats()
3128 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_read_mmc_stats()
3131 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); in xgbe_read_mmc_stats()
3134 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) in xgbe_config_mmc() argument
3137 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()
3140 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); in xgbe_config_mmc()
3143 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, in xgbe_txq_prepare_tx_stop() argument
3155 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); in xgbe_txq_prepare_tx_stop()
3164 netdev_info(pdata->netdev, in xgbe_txq_prepare_tx_stop()
3169 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, in xgbe_prepare_tx_stop() argument
3176 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
3177 return xgbe_txq_prepare_tx_stop(pdata, queue); in xgbe_prepare_tx_stop()
3197 tx_status = XGMAC_IOREAD(pdata, tx_dsr); in xgbe_prepare_tx_stop()
3207 netdev_info(pdata->netdev, in xgbe_prepare_tx_stop()
3212 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) in xgbe_enable_tx() argument
3217 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
3218 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
3221 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
3225 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
3226 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, in xgbe_enable_tx()
3230 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_enable_tx()
3233 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) in xgbe_disable_tx() argument
3238 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3239 xgbe_prepare_tx_stop(pdata, i); in xgbe_disable_tx()
3242 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_disable_tx()
3245 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3246 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); in xgbe_disable_tx()
3249 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
3250 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
3253 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
3257 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, in xgbe_prepare_rx_stop() argument
3269 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); in xgbe_prepare_rx_stop()
3278 netdev_info(pdata->netdev, in xgbe_prepare_rx_stop()
3283 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) in xgbe_enable_rx() argument
3288 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
3289 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
3292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
3297 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
3299 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); in xgbe_enable_rx()
3302 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); in xgbe_enable_rx()
3303 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); in xgbe_enable_rx()
3304 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); in xgbe_enable_rx()
3305 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); in xgbe_enable_rx()
3308 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) in xgbe_disable_rx() argument
3313 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); in xgbe_disable_rx()
3314 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); in xgbe_disable_rx()
3315 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); in xgbe_disable_rx()
3316 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); in xgbe_disable_rx()
3319 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
3320 xgbe_prepare_rx_stop(pdata, i); in xgbe_disable_rx()
3323 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); in xgbe_disable_rx()
3326 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
3327 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
3330 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
3334 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) in xgbe_powerup_tx() argument
3339 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
3340 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
3343 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
3347 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_powerup_tx()
3350 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) in xgbe_powerdown_tx() argument
3355 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
3356 xgbe_prepare_tx_stop(pdata, i); in xgbe_powerdown_tx()
3359 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_powerdown_tx()
3362 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
3363 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
3366 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
3370 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) in xgbe_powerup_rx() argument
3375 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
3376 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
3379 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
3383 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) in xgbe_powerdown_rx() argument
3388 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
3389 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
3392 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
3396 static int xgbe_init(struct xgbe_prv_data *pdata) in xgbe_init() argument
3398 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
3404 ret = xgbe_flush_tx_queues(pdata); in xgbe_init()
3406 netdev_err(pdata->netdev, "error flushing TX queues\n"); in xgbe_init()
3413 xgbe_config_dma_bus(pdata); in xgbe_init()
3414 xgbe_config_dma_cache(pdata); in xgbe_init()
3415 xgbe_config_osp_mode(pdata); in xgbe_init()
3416 xgbe_config_pbl_val(pdata); in xgbe_init()
3417 xgbe_config_rx_coalesce(pdata); in xgbe_init()
3418 xgbe_config_tx_coalesce(pdata); in xgbe_init()
3419 xgbe_config_rx_buffer_size(pdata); in xgbe_init()
3420 xgbe_config_tso_mode(pdata); in xgbe_init()
3422 if (pdata->netdev->features & NETIF_F_RXCSUM) { in xgbe_init()
3423 xgbe_config_sph_mode(pdata); in xgbe_init()
3424 xgbe_config_rss(pdata); in xgbe_init()
3427 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
3428 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
3429 xgbe_enable_dma_interrupts(pdata); in xgbe_init()
3434 xgbe_config_mtl_mode(pdata); in xgbe_init()
3435 xgbe_config_queue_mapping(pdata); in xgbe_init()
3436 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
3437 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
3438 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
3439 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
3440 xgbe_config_tx_fifo_size(pdata); in xgbe_init()
3441 xgbe_config_rx_fifo_size(pdata); in xgbe_init()
3445 xgbe_config_dcb_tc(pdata); in xgbe_init()
3446 xgbe_enable_mtl_interrupts(pdata); in xgbe_init()
3451 xgbe_config_mac_address(pdata); in xgbe_init()
3452 xgbe_config_rx_mode(pdata); in xgbe_init()
3453 xgbe_config_jumbo_enable(pdata); in xgbe_init()
3454 xgbe_config_flow_control(pdata); in xgbe_init()
3455 xgbe_config_mac_speed(pdata); in xgbe_init()
3456 xgbe_config_checksum_offload(pdata); in xgbe_init()
3457 xgbe_config_vlan_support(pdata); in xgbe_init()
3458 xgbe_config_mmc(pdata); in xgbe_init()
3459 xgbe_enable_mac_interrupts(pdata); in xgbe_init()
3464 xgbe_enable_ecc_interrupts(pdata); in xgbe_init()