Lines Matching +full:mtl +full:- +full:rx +full:- +full:config
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
17 #include "xgbe-common.h"
18 #include "xgbe-smn.h"
22 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
31 DBGPR("-->xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
33 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
43 DBGPR("<--xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
54 DBGPR("-->xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
56 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
66 DBGPR("<--xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
77 pbl = pdata->pbl; in xgbe_config_pbl_val()
79 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
84 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
85 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
88 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
89 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
92 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
93 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
104 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
105 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
108 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
109 pdata->tx_osp_mode); in xgbe_config_osp_mode()
119 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
129 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
140 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
151 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
161 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
162 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
165 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
166 pdata->rx_riwt); in xgbe_config_rx_coalesce()
181 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
182 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
185 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
186 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
194 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
195 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
198 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); in xgbe_config_tso_mode()
206 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
207 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
210 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
220 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_sph_mode()
221 if (!pdata->channel[i]->rx_ring) in xgbe_disable_sph_mode()
224 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0); in xgbe_disable_sph_mode()
234 mutex_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
237 ret = -EBUSY; in xgbe_write_rss_reg()
249 while (wait--) { in xgbe_write_rss_reg()
256 ret = -EBUSY; in xgbe_write_rss_reg()
259 mutex_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
266 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); in xgbe_write_rss_hash_key()
267 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
270 while (key_regs--) { in xgbe_write_rss_hash_key()
285 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
288 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
298 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
308 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
309 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
318 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
319 return -EOPNOTSUPP; in xgbe_enable_rss()
332 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
342 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
343 return -EOPNOTSUPP; in xgbe_disable_rss()
354 if (!pdata->hw_feat.rss) in xgbe_config_rss()
357 if (pdata->netdev->features & NETIF_F_RXHASH) in xgbe_config_rss()
363 netdev_err(pdata->netdev, in xgbe_config_rss()
374 if (pdata->prio2q_map[prio] != queue) in xgbe_is_pfc_queue()
378 tc = pdata->ets->prio_tc[prio]; in xgbe_is_pfc_queue()
381 if (pdata->pfc->pfc_en & (1 << tc)) in xgbe_is_pfc_queue()
391 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); in xgbe_set_vxlan_id()
393 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", in xgbe_set_vxlan_id()
394 pdata->vxlan_port); in xgbe_set_vxlan_id()
399 if (!pdata->hw_feat.vxn) in xgbe_enable_vxlan()
405 /* Allow for IPv6/UDP zero-checksum VXLAN packets */ in xgbe_enable_vxlan()
412 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); in xgbe_enable_vxlan()
417 if (!pdata->hw_feat.vxn) in xgbe_disable_vxlan()
423 /* Clear IPv6/UDP zero-checksum VXLAN packets setting */ in xgbe_disable_vxlan()
429 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); in xgbe_disable_vxlan()
437 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30) in xgbe_get_fc_queue_count()
440 return min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_get_fc_queue_count()
448 /* Clear MTL flow control */ in xgbe_disable_tx_flow_control()
449 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
468 struct ieee_pfc *pfc = pdata->pfc; in xgbe_enable_tx_flow_control()
469 struct ieee_ets *ets = pdata->ets; in xgbe_enable_tx_flow_control()
473 /* Set MTL flow control */ in xgbe_enable_tx_flow_control()
474 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
477 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
489 netif_dbg(pdata, drv, pdata->netdev, in xgbe_enable_tx_flow_control()
529 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_tx_flow_control()
531 if (pdata->tx_pause || (pfc && pfc->pfc_en)) in xgbe_config_tx_flow_control()
541 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_rx_flow_control()
543 if (pdata->rx_pause || (pfc && pfc->pfc_en)) in xgbe_config_rx_flow_control()
553 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_flow_control()
559 (pfc && pfc->pfc_en) ? 1 : 0); in xgbe_config_flow_control()
568 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
570 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
572 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
574 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
575 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
582 channel->curr_ier = 0; in xgbe_enable_dma_interrupts()
585 * NIE - Normal Interrupt Summary Enable in xgbe_enable_dma_interrupts()
586 * AIE - Abnormal Interrupt Summary Enable in xgbe_enable_dma_interrupts()
587 * FBEE - Fatal Bus Error Enable in xgbe_enable_dma_interrupts()
590 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); in xgbe_enable_dma_interrupts()
591 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); in xgbe_enable_dma_interrupts()
593 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); in xgbe_enable_dma_interrupts()
594 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); in xgbe_enable_dma_interrupts()
596 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); in xgbe_enable_dma_interrupts()
598 if (channel->tx_ring) { in xgbe_enable_dma_interrupts()
600 * TIE - Transmit Interrupt Enable (unless using in xgbe_enable_dma_interrupts()
604 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
605 XGMAC_SET_BITS(channel->curr_ier, in xgbe_enable_dma_interrupts()
608 if (channel->rx_ring) { in xgbe_enable_dma_interrupts()
609 /* Enable following Rx interrupts in xgbe_enable_dma_interrupts()
610 * RBUE - Receive Buffer Unavailable Enable in xgbe_enable_dma_interrupts()
611 * RIE - Receive Interrupt Enable (unless using in xgbe_enable_dma_interrupts()
615 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); in xgbe_enable_dma_interrupts()
616 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
617 XGMAC_SET_BITS(channel->curr_ier, in xgbe_enable_dma_interrupts()
621 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_enable_dma_interrupts()
630 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
636 /* No MTL interrupts to be enabled */ in xgbe_enable_mtl_interrupts()
662 if (!pdata->vdata->ecc_support) in xgbe_enable_ecc_interrupts()
735 return -EINVAL; in xgbe_set_speed()
746 /* Put the VLAN tag in the Rx descriptor */ in xgbe_enable_rx_vlan_stripping()
752 /* Check only C-TAG (0x8100) packets */ in xgbe_enable_rx_vlan_stripping()
755 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ in xgbe_enable_rx_vlan_stripping()
782 /* Only filter on the lower 12-bits of the VLAN tag */ in xgbe_enable_rx_vlan_filtering()
836 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { in xgbe_update_vlan_hash_table()
858 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", in xgbe_set_promiscuous_mode()
866 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_set_promiscuous_mode()
881 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", in xgbe_set_all_multicast_mode()
899 mac_addr[0] = ha->addr[0]; in xgbe_set_mac_reg()
900 mac_addr[1] = ha->addr[1]; in xgbe_set_mac_reg()
901 mac_addr[2] = ha->addr[2]; in xgbe_set_mac_reg()
902 mac_addr[3] = ha->addr[3]; in xgbe_set_mac_reg()
904 mac_addr[0] = ha->addr[4]; in xgbe_set_mac_reg()
905 mac_addr[1] = ha->addr[5]; in xgbe_set_mac_reg()
907 netif_dbg(pdata, drv, pdata->netdev, in xgbe_set_mac_reg()
909 ha->addr, *mac_reg); in xgbe_set_mac_reg()
922 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_addn_addrs()
928 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
935 addn_macs--; in xgbe_set_mac_addn_addrs()
943 addn_macs--; in xgbe_set_mac_addn_addrs()
949 while (addn_macs--) in xgbe_set_mac_addn_addrs()
955 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_hash_table()
963 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); in xgbe_set_mac_hash_table()
964 hash_table_count = pdata->hw_feat.hash_table_size / 32; in xgbe_set_mac_hash_table()
969 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); in xgbe_set_mac_hash_table()
975 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); in xgbe_set_mac_hash_table()
990 if (pdata->hw_feat.hash_table_size) in xgbe_add_mac_addresses()
1014 struct net_device *netdev = pdata->netdev; in xgbe_config_rx_mode()
1017 pr_mode = ((netdev->flags & IFF_PROMISC) != 0); in xgbe_config_rx_mode()
1018 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); in xgbe_config_rx_mode()
1033 return -EINVAL; in xgbe_clr_gpio()
1048 return -EINVAL; in xgbe_set_gpio()
1063 (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_get_mmd_address()
1076 * The mmio interface is based on 16-bit offsets and values. All in xgbe_get_pcs_index_and_offset()
1081 *index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_get_pcs_index_and_offset()
1082 *offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_get_pcs_index_and_offset()
1097 smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg; in xgbe_read_mmd_regs_v3()
1102 ret = amd_smn_read(0, pdata->smn_base + offset, &mmd_data); in xgbe_read_mmd_regs_v3()
1121 dev = pdata->pcidev; in xgbe_write_mmd_regs_v3()
1126 smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg; in xgbe_write_mmd_regs_v3()
1133 ret = amd_smn_read(0, pdata->smn_base + offset, &pci_mmd_data); in xgbe_write_mmd_regs_v3()
1156 ret = amd_smn_write(0, (pdata->smn_base + offset), pci_mmd_data); in xgbe_write_mmd_regs_v3()
1174 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1175 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1177 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1192 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1193 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1195 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1212 * The mmio interface is based on 32-bit offsets and values. All in xgbe_read_mmd_regs_v1()
1216 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1219 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1237 * The mmio interface is based on 32-bit offsets and values. All in xgbe_write_mmd_regs_v1()
1241 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1244 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1250 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1266 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1307 reinit_completion(&pdata->mdio_complete); in xgbe_write_ext_mii_regs()
1317 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_write_ext_mii_regs()
1318 netdev_err(pdata->netdev, "mdio write operation timed out\n"); in xgbe_write_ext_mii_regs()
1319 return -ETIMEDOUT; in xgbe_write_ext_mii_regs()
1350 reinit_completion(&pdata->mdio_complete); in xgbe_read_ext_mii_regs()
1359 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_read_ext_mii_regs()
1360 netdev_err(pdata->netdev, "mdio read operation timed out\n"); in xgbe_read_ext_mii_regs()
1361 return -ETIMEDOUT; in xgbe_read_ext_mii_regs()
1395 return -EINVAL; in xgbe_set_ext_mii_mode()
1401 return -EINVAL; in xgbe_set_ext_mii_mode()
1411 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); in xgbe_tx_complete()
1430 struct xgbe_ring_desc *rdesc = rdata->rdesc; in xgbe_tx_desc_reset()
1438 rdesc->desc0 = 0; in xgbe_tx_desc_reset()
1439 rdesc->desc1 = 0; in xgbe_tx_desc_reset()
1440 rdesc->desc2 = 0; in xgbe_tx_desc_reset()
1441 rdesc->desc3 = 0; in xgbe_tx_desc_reset()
1449 struct xgbe_ring *ring = channel->tx_ring; in xgbe_tx_desc_init()
1452 int start_index = ring->cur; in xgbe_tx_desc_init()
1454 DBGPR("-->tx_desc_init\n"); in xgbe_tx_desc_init()
1457 for (i = 0; i < ring->rdesc_count; i++) { in xgbe_tx_desc_init()
1465 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); in xgbe_tx_desc_init()
1470 upper_32_bits(rdata->rdesc_dma)); in xgbe_tx_desc_init()
1472 lower_32_bits(rdata->rdesc_dma)); in xgbe_tx_desc_init()
1474 DBGPR("<--tx_desc_init\n"); in xgbe_tx_desc_init()
1480 struct xgbe_ring_desc *rdesc = rdata->rdesc; in xgbe_rx_desc_reset()
1481 unsigned int rx_usecs = pdata->rx_usecs; in xgbe_rx_desc_reset()
1482 unsigned int rx_frames = pdata->rx_frames; in xgbe_rx_desc_reset()
1490 /* Set interrupt based on Rx frame coalescing setting */ in xgbe_rx_desc_reset()
1497 /* Reset the Rx descriptor in xgbe_rx_desc_reset()
1504 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; in xgbe_rx_desc_reset()
1505 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; in xgbe_rx_desc_reset()
1506 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); in xgbe_rx_desc_reset()
1507 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); in xgbe_rx_desc_reset()
1508 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); in xgbe_rx_desc_reset()
1509 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); in xgbe_rx_desc_reset()
1511 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); in xgbe_rx_desc_reset()
1513 /* Since the Rx DMA engine is likely running, make sure everything in xgbe_rx_desc_reset()
1519 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); in xgbe_rx_desc_reset()
1527 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_rx_desc_init()
1528 struct xgbe_ring *ring = channel->rx_ring; in xgbe_rx_desc_init()
1530 unsigned int start_index = ring->cur; in xgbe_rx_desc_init()
1533 DBGPR("-->rx_desc_init\n"); in xgbe_rx_desc_init()
1536 for (i = 0; i < ring->rdesc_count; i++) { in xgbe_rx_desc_init()
1539 /* Initialize Rx descriptor */ in xgbe_rx_desc_init()
1543 /* Update the total number of Rx descriptors */ in xgbe_rx_desc_init()
1544 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); in xgbe_rx_desc_init()
1549 upper_32_bits(rdata->rdesc_dma)); in xgbe_rx_desc_init()
1551 lower_32_bits(rdata->rdesc_dma)); in xgbe_rx_desc_init()
1553 /* Update the Rx Descriptor Tail Pointer */ in xgbe_rx_desc_init()
1554 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); in xgbe_rx_desc_init()
1556 lower_32_bits(rdata->rdesc_dma)); in xgbe_rx_desc_init()
1558 DBGPR("<--rx_desc_init\n"); in xgbe_rx_desc_init()
1564 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_tx_start_xmit()
1572 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); in xgbe_tx_start_xmit()
1574 lower_32_bits(rdata->rdesc_dma)); in xgbe_tx_start_xmit()
1577 if (pdata->tx_usecs && !channel->tx_timer_active) { in xgbe_tx_start_xmit()
1578 channel->tx_timer_active = 1; in xgbe_tx_start_xmit()
1579 mod_timer(&channel->tx_timer, in xgbe_tx_start_xmit()
1580 jiffies + usecs_to_jiffies(pdata->tx_usecs)); in xgbe_tx_start_xmit()
1583 ring->tx.xmit_more = 0; in xgbe_tx_start_xmit()
1588 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_xmit()
1589 struct xgbe_ring *ring = channel->tx_ring; in xgbe_dev_xmit()
1592 struct xgbe_packet_data *packet = &ring->packet_data; in xgbe_dev_xmit()
1597 int start_index = ring->cur; in xgbe_dev_xmit()
1598 int cur_index = ring->cur; in xgbe_dev_xmit()
1601 DBGPR("-->xgbe_dev_xmit\n"); in xgbe_dev_xmit()
1603 tx_packets = packet->tx_packets; in xgbe_dev_xmit()
1604 tx_bytes = packet->tx_bytes; in xgbe_dev_xmit()
1606 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1608 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1610 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1612 vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, in xgbe_dev_xmit()
1615 if (tso && (packet->mss != ring->tx.cur_mss)) in xgbe_dev_xmit()
1620 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) in xgbe_dev_xmit()
1627 * - Tx frame count exceeds the frame count setting in xgbe_dev_xmit()
1628 * - Addition of Tx frame count to the frame count since the in xgbe_dev_xmit()
1631 * - No frame count setting specified (ethtool -C ethX tx-frames 0) in xgbe_dev_xmit()
1632 * - Addition of Tx frame count to the frame count since the in xgbe_dev_xmit()
1635 ring->coalesce_count += tx_packets; in xgbe_dev_xmit()
1636 if (!pdata->tx_frames) in xgbe_dev_xmit()
1638 else if (tx_packets > pdata->tx_frames) in xgbe_dev_xmit()
1640 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) in xgbe_dev_xmit()
1646 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1651 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1653 packet->mss); in xgbe_dev_xmit()
1656 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, in xgbe_dev_xmit()
1657 MSS, packet->mss); in xgbe_dev_xmit()
1660 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1664 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1667 ring->tx.cur_mss = packet->mss; in xgbe_dev_xmit()
1671 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1673 packet->vlan_ctag); in xgbe_dev_xmit()
1676 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1680 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1681 VT, packet->vlan_ctag); in xgbe_dev_xmit()
1684 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, in xgbe_dev_xmit()
1687 ring->tx.cur_vlan_ctag = packet->vlan_ctag; in xgbe_dev_xmit()
1692 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1696 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1697 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1700 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, in xgbe_dev_xmit()
1701 rdata->skb_dma_len); in xgbe_dev_xmit()
1705 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, in xgbe_dev_xmit()
1709 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) in xgbe_dev_xmit()
1710 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); in xgbe_dev_xmit()
1713 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); in xgbe_dev_xmit()
1716 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); in xgbe_dev_xmit()
1720 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); in xgbe_dev_xmit()
1724 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); in xgbe_dev_xmit()
1725 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, in xgbe_dev_xmit()
1726 packet->tcp_payload_len); in xgbe_dev_xmit()
1727 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, in xgbe_dev_xmit()
1728 packet->tcp_header_len / 4); in xgbe_dev_xmit()
1730 pdata->ext_stats.tx_tso_packets += tx_packets; in xgbe_dev_xmit()
1733 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); in xgbe_dev_xmit()
1737 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, in xgbe_dev_xmit()
1741 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, in xgbe_dev_xmit()
1742 packet->length); in xgbe_dev_xmit()
1746 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP, in xgbe_dev_xmit()
1749 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; in xgbe_dev_xmit()
1752 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { in xgbe_dev_xmit()
1755 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1758 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1759 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); in xgbe_dev_xmit()
1762 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, in xgbe_dev_xmit()
1763 rdata->skb_dma_len); in xgbe_dev_xmit()
1766 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); in xgbe_dev_xmit()
1769 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); in xgbe_dev_xmit()
1773 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, in xgbe_dev_xmit()
1778 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); in xgbe_dev_xmit()
1782 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); in xgbe_dev_xmit()
1785 rdata->tx.packets = tx_packets; in xgbe_dev_xmit()
1786 rdata->tx.bytes = tx_bytes; in xgbe_dev_xmit()
1788 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; in xgbe_dev_xmit()
1789 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; in xgbe_dev_xmit()
1799 rdesc = rdata->rdesc; in xgbe_dev_xmit()
1800 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); in xgbe_dev_xmit()
1804 packet->rdesc_count, 1); in xgbe_dev_xmit()
1809 ring->cur = cur_index + 1; in xgbe_dev_xmit()
1811 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, in xgbe_dev_xmit()
1812 channel->queue_index))) in xgbe_dev_xmit()
1815 ring->tx.xmit_more = 1; in xgbe_dev_xmit()
1818 channel->name, start_index & (ring->rdesc_count - 1), in xgbe_dev_xmit()
1819 (ring->cur - 1) & (ring->rdesc_count - 1)); in xgbe_dev_xmit()
1821 DBGPR("<--xgbe_dev_xmit\n"); in xgbe_dev_xmit()
1826 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read()
1827 struct xgbe_ring *ring = channel->rx_ring; in xgbe_dev_read()
1830 struct xgbe_packet_data *packet = &ring->packet_data; in xgbe_dev_read()
1831 struct net_device *netdev = pdata->netdev; in xgbe_dev_read()
1834 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); in xgbe_dev_read()
1836 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); in xgbe_dev_read()
1837 rdesc = rdata->rdesc; in xgbe_dev_read()
1840 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) in xgbe_dev_read()
1847 xgbe_dump_rx_desc(pdata, ring, ring->cur); in xgbe_dev_read()
1849 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { in xgbe_dev_read()
1853 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1855 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1861 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); in xgbe_dev_read()
1864 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) in xgbe_dev_read()
1865 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1869 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { in xgbe_dev_read()
1870 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1872 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, in xgbe_dev_read()
1874 if (rdata->rx.hdr_len) in xgbe_dev_read()
1875 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
1877 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1882 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { in xgbe_dev_read()
1883 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1886 packet->rss_hash = le32_to_cpu(rdesc->desc1); in xgbe_dev_read()
1888 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); in xgbe_dev_read()
1894 packet->rss_hash_type = PKT_HASH_TYPE_L4; in xgbe_dev_read()
1897 packet->rss_hash_type = PKT_HASH_TYPE_L3; in xgbe_dev_read()
1902 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) in xgbe_dev_read()
1906 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1910 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); in xgbe_dev_read()
1913 if (netdev->features & NETIF_F_RXCSUM) { in xgbe_dev_read()
1914 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1916 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1921 if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) { in xgbe_dev_read()
1922 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1924 pdata->ext_stats.rx_vxlan_packets++; in xgbe_dev_read()
1926 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); in xgbe_dev_read()
1930 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1937 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); in xgbe_dev_read()
1938 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); in xgbe_dev_read()
1944 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { in xgbe_dev_read()
1945 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1947 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, in xgbe_dev_read()
1950 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", in xgbe_dev_read()
1951 packet->vlan_ctag); in xgbe_dev_read()
1954 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, in xgbe_dev_read()
1958 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1960 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1962 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
1964 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1966 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1968 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
1970 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, in xgbe_dev_read()
1975 pdata->ext_stats.rxq_packets[channel->queue_index]++; in xgbe_dev_read()
1976 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; in xgbe_dev_read()
1978 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, in xgbe_dev_read()
1979 ring->cur & (ring->rdesc_count - 1), ring->cur); in xgbe_dev_read()
1986 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ in xgbe_is_context_desc()
1987 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); in xgbe_is_context_desc()
1992 /* Rx and Tx share LD bit, so check TDES3.LD bit */ in xgbe_is_last_desc()
1993 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); in xgbe_is_last_desc()
2001 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); in xgbe_enable_int()
2004 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); in xgbe_enable_int()
2007 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); in xgbe_enable_int()
2010 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); in xgbe_enable_int()
2013 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); in xgbe_enable_int()
2016 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); in xgbe_enable_int()
2019 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); in xgbe_enable_int()
2020 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); in xgbe_enable_int()
2023 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); in xgbe_enable_int()
2026 channel->curr_ier |= channel->saved_ier; in xgbe_enable_int()
2029 return -1; in xgbe_enable_int()
2032 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_enable_int()
2042 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); in xgbe_disable_int()
2045 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); in xgbe_disable_int()
2048 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); in xgbe_disable_int()
2051 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); in xgbe_disable_int()
2054 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); in xgbe_disable_int()
2057 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); in xgbe_disable_int()
2060 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); in xgbe_disable_int()
2061 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); in xgbe_disable_int()
2064 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); in xgbe_disable_int()
2067 channel->saved_ier = channel->curr_ier; in xgbe_disable_int()
2068 channel->curr_ier = 0; in xgbe_disable_int()
2071 return -1; in xgbe_disable_int()
2074 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_disable_int()
2083 DBGPR("-->xgbe_exit\n"); in __xgbe_exit()
2090 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
2094 return -EBUSY; in __xgbe_exit()
2096 DBGPR("<--xgbe_exit\n"); in __xgbe_exit()
2119 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
2122 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
2126 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
2128 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
2133 return -EBUSY; in xgbe_flush_tx_queues()
2150 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
2151 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
2152 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
2153 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
2158 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
2160 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
2162 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
2164 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
2169 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
2170 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
2171 if (pdata->awarcr) in xgbe_config_dma_cache()
2172 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
2183 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
2189 /* Set Rx to strict priority algorithm */ in xgbe_config_mtl_mode()
2202 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { in xgbe_queue_flow_control_threshold()
2204 rfa = pdata->pfc_rfa; in xgbe_queue_flow_control_threshold()
2209 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT; in xgbe_queue_flow_control_threshold()
2218 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
2219 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
2225 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
2226 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
2231 /* Between 4096 and max-frame */ in xgbe_queue_flow_control_threshold()
2232 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
2233 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
2238 /* Between max-frame and 3 max-frames, in xgbe_queue_flow_control_threshold()
2242 rfa = q_fifo_size - frame_fifo_size; in xgbe_queue_flow_control_threshold()
2245 /* Above 3 max-frames - trigger when just over in xgbe_queue_flow_control_threshold()
2254 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
2255 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
2264 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
2275 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
2277 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
2279 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
2286 return min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
2287 pdata->hw_feat.tx_fifo_size); in xgbe_get_tx_fifo_size()
2293 return min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
2294 pdata->hw_feat.rx_fifo_size); in xgbe_get_rx_fifo_size()
2313 p_fifo--; in xgbe_calculate_equal_fifo()
2331 /* Rx queues 9 and up are for specialized packets, in xgbe_set_nonprio_fifos()
2336 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; in xgbe_set_nonprio_fifos()
2337 fifo_size -= XGMAC_FIFO_MIN_ALLOC; in xgbe_set_nonprio_fifos()
2348 if (pdata->pfc->delay) in xgbe_get_pfc_delay()
2349 return pdata->pfc->delay / 8; in xgbe_get_pfc_delay()
2372 if (!pdata->pfc->pfc_en) in xgbe_get_pfc_queues()
2376 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_get_pfc_queues()
2381 pdata->pfcq[i] = 1; in xgbe_get_pfc_queues()
2398 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_calculate_dcb_fifo()
2408 rem_fifo = fifo_size - (q_fifo_size * prio_queues); in xgbe_calculate_dcb_fifo()
2413 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); in xgbe_calculate_dcb_fifo()
2414 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); in xgbe_calculate_dcb_fifo()
2416 if (pdata->pfc_rfa > q_fifo_size) { in xgbe_calculate_dcb_fifo()
2417 addn_fifo = pdata->pfc_rfa - q_fifo_size; in xgbe_calculate_dcb_fifo()
2424 * - distribute remaining fifo between the VLAN priority in xgbe_calculate_dcb_fifo()
2430 i--; in xgbe_calculate_dcb_fifo()
2432 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1; in xgbe_calculate_dcb_fifo()
2434 if (!pdata->pfcq[i] || !addn_fifo) in xgbe_calculate_dcb_fifo()
2438 netdev_warn(pdata->netdev, in xgbe_calculate_dcb_fifo()
2447 rem_fifo -= addn_fifo; in xgbe_calculate_dcb_fifo()
2467 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
2469 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_fifo_size()
2472 netif_info(pdata, drv, pdata->netdev, in xgbe_config_tx_fifo_size()
2474 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
2485 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); in xgbe_config_rx_fifo_size()
2486 pdata->pfc_rfa = 0; in xgbe_config_rx_fifo_size()
2489 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2491 /* Assign a minimum fifo to the non-VLAN priority queues */ in xgbe_config_rx_fifo_size()
2492 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
2494 if (pdata->pfc && pdata->ets) in xgbe_config_rx_fifo_size()
2499 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2505 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { in xgbe_config_rx_fifo_size()
2506 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2507 "%u Rx hardware queues\n", pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2508 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2509 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2513 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2514 "%u Rx hardware queues, %u byte fifo per queue\n", in xgbe_config_rx_fifo_size()
2515 pdata->rx_q_count, in xgbe_config_rx_fifo_size()
2528 /* Map the MTL Tx Queues to Traffic Classes in xgbe_config_queue_mapping()
2531 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2532 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2534 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
2536 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2540 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2544 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2548 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2552 /* Map the 8 VLAN priority values to available MTL Rx queues */ in xgbe_config_queue_mapping()
2553 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
2562 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2565 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2569 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2572 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2585 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ in xgbe_config_queue_mapping()
2588 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2591 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2606 netdev_reset_tc(pdata->netdev); in xgbe_config_tc()
2607 if (!pdata->num_tcs) in xgbe_config_tc()
2610 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); in xgbe_config_tc()
2612 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { in xgbe_config_tc()
2613 while ((queue < pdata->tx_q_count) && in xgbe_config_tc()
2614 (pdata->q2tc_map[queue] == i)) in xgbe_config_tc()
2617 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", in xgbe_config_tc()
2618 i, offset, queue - 1); in xgbe_config_tc()
2619 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); in xgbe_config_tc()
2623 if (!pdata->ets) in xgbe_config_tc()
2627 netdev_set_prio_tc_map(pdata->netdev, prio, in xgbe_config_tc()
2628 pdata->ets->prio_tc[prio]); in xgbe_config_tc()
2633 struct ieee_ets *ets = pdata->ets; in xgbe_config_dcb_tc()
2647 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; in xgbe_config_dcb_tc()
2652 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_dcb_tc()
2656 if (ets->prio_tc[prio] == i) in xgbe_config_dcb_tc()
2661 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", in xgbe_config_dcb_tc()
2672 switch (ets->tc_tsa[i]) { in xgbe_config_dcb_tc()
2674 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2680 weight = total_weight * ets->tc_tx_bw[i] / 100; in xgbe_config_dcb_tc()
2683 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2698 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2699 /* Just stop the Tx queues while Rx fifo is changed */ in xgbe_config_dcb_pfc()
2700 netif_tx_stop_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2702 /* Suspend Rx so that fifo's can be adjusted */ in xgbe_config_dcb_pfc()
2703 pdata->hw_if.disable_rx(pdata); in xgbe_config_dcb_pfc()
2709 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2710 /* Resume Rx */ in xgbe_config_dcb_pfc()
2711 pdata->hw_if.enable_rx(pdata); in xgbe_config_dcb_pfc()
2714 netif_tx_start_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2720 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); in xgbe_config_mac_address()
2723 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2734 if (pdata->netdev->mtu > XGMAC_JUMBO_PACKET_MTU) { in xgbe_config_jumbo_enable()
2741 val = pdata->netdev->mtu > XGMAC_STD_PACKET_MTU ? 1 : 0; in xgbe_config_jumbo_enable()
2751 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2756 if (pdata->netdev->features & NETIF_F_RXCSUM) in xgbe_config_checksum_offload()
2771 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_config_vlan_support()
2776 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) in xgbe_config_vlan_support()
2787 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2826 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2830 stats->txoctetcount_gb += in xgbe_tx_mmc_int()
2834 stats->txframecount_gb += in xgbe_tx_mmc_int()
2838 stats->txbroadcastframes_g += in xgbe_tx_mmc_int()
2842 stats->txmulticastframes_g += in xgbe_tx_mmc_int()
2846 stats->tx64octets_gb += in xgbe_tx_mmc_int()
2850 stats->tx65to127octets_gb += in xgbe_tx_mmc_int()
2854 stats->tx128to255octets_gb += in xgbe_tx_mmc_int()
2858 stats->tx256to511octets_gb += in xgbe_tx_mmc_int()
2862 stats->tx512to1023octets_gb += in xgbe_tx_mmc_int()
2866 stats->tx1024tomaxoctets_gb += in xgbe_tx_mmc_int()
2870 stats->txunicastframes_gb += in xgbe_tx_mmc_int()
2874 stats->txmulticastframes_gb += in xgbe_tx_mmc_int()
2878 stats->txbroadcastframes_g += in xgbe_tx_mmc_int()
2882 stats->txunderflowerror += in xgbe_tx_mmc_int()
2886 stats->txoctetcount_g += in xgbe_tx_mmc_int()
2890 stats->txframecount_g += in xgbe_tx_mmc_int()
2894 stats->txpauseframes += in xgbe_tx_mmc_int()
2898 stats->txvlanframes_g += in xgbe_tx_mmc_int()
2904 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
2908 stats->rxframecount_gb += in xgbe_rx_mmc_int()
2912 stats->rxoctetcount_gb += in xgbe_rx_mmc_int()
2916 stats->rxoctetcount_g += in xgbe_rx_mmc_int()
2920 stats->rxbroadcastframes_g += in xgbe_rx_mmc_int()
2924 stats->rxmulticastframes_g += in xgbe_rx_mmc_int()
2928 stats->rxcrcerror += in xgbe_rx_mmc_int()
2932 stats->rxrunterror += in xgbe_rx_mmc_int()
2936 stats->rxjabbererror += in xgbe_rx_mmc_int()
2940 stats->rxundersize_g += in xgbe_rx_mmc_int()
2944 stats->rxoversize_g += in xgbe_rx_mmc_int()
2948 stats->rx64octets_gb += in xgbe_rx_mmc_int()
2952 stats->rx65to127octets_gb += in xgbe_rx_mmc_int()
2956 stats->rx128to255octets_gb += in xgbe_rx_mmc_int()
2960 stats->rx256to511octets_gb += in xgbe_rx_mmc_int()
2964 stats->rx512to1023octets_gb += in xgbe_rx_mmc_int()
2968 stats->rx1024tomaxoctets_gb += in xgbe_rx_mmc_int()
2972 stats->rxunicastframes_g += in xgbe_rx_mmc_int()
2976 stats->rxlengtherror += in xgbe_rx_mmc_int()
2980 stats->rxoutofrangetype += in xgbe_rx_mmc_int()
2984 stats->rxpauseframes += in xgbe_rx_mmc_int()
2988 stats->rxfifooverflow += in xgbe_rx_mmc_int()
2992 stats->rxvlanframes_gb += in xgbe_rx_mmc_int()
2996 stats->rxwatchdogerror += in xgbe_rx_mmc_int()
3002 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
3007 stats->txoctetcount_gb += in xgbe_read_mmc_stats()
3010 stats->txframecount_gb += in xgbe_read_mmc_stats()
3013 stats->txbroadcastframes_g += in xgbe_read_mmc_stats()
3016 stats->txmulticastframes_g += in xgbe_read_mmc_stats()
3019 stats->tx64octets_gb += in xgbe_read_mmc_stats()
3022 stats->tx65to127octets_gb += in xgbe_read_mmc_stats()
3025 stats->tx128to255octets_gb += in xgbe_read_mmc_stats()
3028 stats->tx256to511octets_gb += in xgbe_read_mmc_stats()
3031 stats->tx512to1023octets_gb += in xgbe_read_mmc_stats()
3034 stats->tx1024tomaxoctets_gb += in xgbe_read_mmc_stats()
3037 stats->txunicastframes_gb += in xgbe_read_mmc_stats()
3040 stats->txmulticastframes_gb += in xgbe_read_mmc_stats()
3043 stats->txbroadcastframes_g += in xgbe_read_mmc_stats()
3046 stats->txunderflowerror += in xgbe_read_mmc_stats()
3049 stats->txoctetcount_g += in xgbe_read_mmc_stats()
3052 stats->txframecount_g += in xgbe_read_mmc_stats()
3055 stats->txpauseframes += in xgbe_read_mmc_stats()
3058 stats->txvlanframes_g += in xgbe_read_mmc_stats()
3061 stats->rxframecount_gb += in xgbe_read_mmc_stats()
3064 stats->rxoctetcount_gb += in xgbe_read_mmc_stats()
3067 stats->rxoctetcount_g += in xgbe_read_mmc_stats()
3070 stats->rxbroadcastframes_g += in xgbe_read_mmc_stats()
3073 stats->rxmulticastframes_g += in xgbe_read_mmc_stats()
3076 stats->rxcrcerror += in xgbe_read_mmc_stats()
3079 stats->rxrunterror += in xgbe_read_mmc_stats()
3082 stats->rxjabbererror += in xgbe_read_mmc_stats()
3085 stats->rxundersize_g += in xgbe_read_mmc_stats()
3088 stats->rxoversize_g += in xgbe_read_mmc_stats()
3091 stats->rx64octets_gb += in xgbe_read_mmc_stats()
3094 stats->rx65to127octets_gb += in xgbe_read_mmc_stats()
3097 stats->rx128to255octets_gb += in xgbe_read_mmc_stats()
3100 stats->rx256to511octets_gb += in xgbe_read_mmc_stats()
3103 stats->rx512to1023octets_gb += in xgbe_read_mmc_stats()
3106 stats->rx1024tomaxoctets_gb += in xgbe_read_mmc_stats()
3109 stats->rxunicastframes_g += in xgbe_read_mmc_stats()
3112 stats->rxlengtherror += in xgbe_read_mmc_stats()
3115 stats->rxoutofrangetype += in xgbe_read_mmc_stats()
3118 stats->rxpauseframes += in xgbe_read_mmc_stats()
3121 stats->rxfifooverflow += in xgbe_read_mmc_stats()
3124 stats->rxvlanframes_gb += in xgbe_read_mmc_stats()
3127 stats->rxwatchdogerror += in xgbe_read_mmc_stats()
3130 /* Un-freeze counters */ in xgbe_read_mmc_stats()
3164 netdev_info(pdata->netdev, in xgbe_txq_prepare_tx_stop()
3176 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
3184 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; in xgbe_prepare_tx_stop()
3207 netdev_info(pdata->netdev, in xgbe_prepare_tx_stop()
3217 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
3218 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
3221 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
3225 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
3238 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3245 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3249 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
3250 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
3253 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
3263 /* The Rx engine cannot be stopped if it is actively processing in xgbe_prepare_rx_stop()
3264 * packets. Wait for the Rx queue to empty the Rx fifo. Don't in xgbe_prepare_rx_stop()
3278 netdev_info(pdata->netdev, in xgbe_prepare_rx_stop()
3279 "timed out waiting for Rx queue %u to empty\n", in xgbe_prepare_rx_stop()
3287 /* Enable each Rx DMA channel */ in xgbe_enable_rx()
3288 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
3289 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
3292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
3295 /* Enable each Rx queue */ in xgbe_enable_rx()
3297 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
3301 /* Enable MAC Rx */ in xgbe_enable_rx()
3312 /* Disable MAC Rx */ in xgbe_disable_rx()
3318 /* Prepare for Rx DMA channel stop */ in xgbe_disable_rx()
3319 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
3322 /* Disable each Rx queue */ in xgbe_disable_rx()
3325 /* Disable each Rx DMA channel */ in xgbe_disable_rx()
3326 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
3327 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
3330 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
3339 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
3340 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
3343 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
3355 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
3362 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
3363 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
3366 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
3374 /* Enable each Rx DMA channel */ in xgbe_powerup_rx()
3375 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
3376 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
3379 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
3387 /* Disable each Rx DMA channel */ in xgbe_powerdown_rx()
3388 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
3389 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
3392 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
3398 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
3401 DBGPR("-->xgbe_init\n"); in xgbe_init()
3406 netdev_err(pdata->netdev, "error flushing TX queues\n"); in xgbe_init()
3422 if (pdata->netdev->features & NETIF_F_RXCSUM) { in xgbe_init()
3427 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
3428 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
3432 * Initialize MTL related features in xgbe_init()
3436 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
3437 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
3438 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
3439 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
3466 DBGPR("<--xgbe_init\n"); in xgbe_init()
3473 DBGPR("-->xgbe_init_function_ptrs\n"); in xgbe_init_function_ptrs_dev()
3475 hw_if->tx_complete = xgbe_tx_complete; in xgbe_init_function_ptrs_dev()
3477 hw_if->set_mac_address = xgbe_set_mac_address; in xgbe_init_function_ptrs_dev()
3478 hw_if->config_rx_mode = xgbe_config_rx_mode; in xgbe_init_function_ptrs_dev()
3480 hw_if->enable_rx_csum = xgbe_enable_rx_csum; in xgbe_init_function_ptrs_dev()
3481 hw_if->disable_rx_csum = xgbe_disable_rx_csum; in xgbe_init_function_ptrs_dev()
3483 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; in xgbe_init_function_ptrs_dev()
3484 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; in xgbe_init_function_ptrs_dev()
3485 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; in xgbe_init_function_ptrs_dev()
3486 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; in xgbe_init_function_ptrs_dev()
3487 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; in xgbe_init_function_ptrs_dev()
3489 hw_if->read_mmd_regs = xgbe_read_mmd_regs; in xgbe_init_function_ptrs_dev()
3490 hw_if->write_mmd_regs = xgbe_write_mmd_regs; in xgbe_init_function_ptrs_dev()
3492 hw_if->set_speed = xgbe_set_speed; in xgbe_init_function_ptrs_dev()
3494 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; in xgbe_init_function_ptrs_dev()
3495 hw_if->read_ext_mii_regs_c22 = xgbe_read_ext_mii_regs_c22; in xgbe_init_function_ptrs_dev()
3496 hw_if->write_ext_mii_regs_c22 = xgbe_write_ext_mii_regs_c22; in xgbe_init_function_ptrs_dev()
3497 hw_if->read_ext_mii_regs_c45 = xgbe_read_ext_mii_regs_c45; in xgbe_init_function_ptrs_dev()
3498 hw_if->write_ext_mii_regs_c45 = xgbe_write_ext_mii_regs_c45; in xgbe_init_function_ptrs_dev()
3500 hw_if->set_gpio = xgbe_set_gpio; in xgbe_init_function_ptrs_dev()
3501 hw_if->clr_gpio = xgbe_clr_gpio; in xgbe_init_function_ptrs_dev()
3503 hw_if->enable_tx = xgbe_enable_tx; in xgbe_init_function_ptrs_dev()
3504 hw_if->disable_tx = xgbe_disable_tx; in xgbe_init_function_ptrs_dev()
3505 hw_if->enable_rx = xgbe_enable_rx; in xgbe_init_function_ptrs_dev()
3506 hw_if->disable_rx = xgbe_disable_rx; in xgbe_init_function_ptrs_dev()
3508 hw_if->powerup_tx = xgbe_powerup_tx; in xgbe_init_function_ptrs_dev()
3509 hw_if->powerdown_tx = xgbe_powerdown_tx; in xgbe_init_function_ptrs_dev()
3510 hw_if->powerup_rx = xgbe_powerup_rx; in xgbe_init_function_ptrs_dev()
3511 hw_if->powerdown_rx = xgbe_powerdown_rx; in xgbe_init_function_ptrs_dev()
3513 hw_if->dev_xmit = xgbe_dev_xmit; in xgbe_init_function_ptrs_dev()
3514 hw_if->dev_read = xgbe_dev_read; in xgbe_init_function_ptrs_dev()
3515 hw_if->enable_int = xgbe_enable_int; in xgbe_init_function_ptrs_dev()
3516 hw_if->disable_int = xgbe_disable_int; in xgbe_init_function_ptrs_dev()
3517 hw_if->init = xgbe_init; in xgbe_init_function_ptrs_dev()
3518 hw_if->exit = xgbe_exit; in xgbe_init_function_ptrs_dev()
3521 hw_if->tx_desc_init = xgbe_tx_desc_init; in xgbe_init_function_ptrs_dev()
3522 hw_if->rx_desc_init = xgbe_rx_desc_init; in xgbe_init_function_ptrs_dev()
3523 hw_if->tx_desc_reset = xgbe_tx_desc_reset; in xgbe_init_function_ptrs_dev()
3524 hw_if->rx_desc_reset = xgbe_rx_desc_reset; in xgbe_init_function_ptrs_dev()
3525 hw_if->is_last_desc = xgbe_is_last_desc; in xgbe_init_function_ptrs_dev()
3526 hw_if->is_context_desc = xgbe_is_context_desc; in xgbe_init_function_ptrs_dev()
3527 hw_if->tx_start_xmit = xgbe_tx_start_xmit; in xgbe_init_function_ptrs_dev()
3530 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; in xgbe_init_function_ptrs_dev()
3531 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; in xgbe_init_function_ptrs_dev()
3533 /* For RX coalescing */ in xgbe_init_function_ptrs_dev()
3534 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; in xgbe_init_function_ptrs_dev()
3535 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; in xgbe_init_function_ptrs_dev()
3536 hw_if->usec_to_riwt = xgbe_usec_to_riwt; in xgbe_init_function_ptrs_dev()
3537 hw_if->riwt_to_usec = xgbe_riwt_to_usec; in xgbe_init_function_ptrs_dev()
3539 /* For RX and TX threshold config */ in xgbe_init_function_ptrs_dev()
3540 hw_if->config_rx_threshold = xgbe_config_rx_threshold; in xgbe_init_function_ptrs_dev()
3541 hw_if->config_tx_threshold = xgbe_config_tx_threshold; in xgbe_init_function_ptrs_dev()
3543 /* For RX and TX Store and Forward Mode config */ in xgbe_init_function_ptrs_dev()
3544 hw_if->config_rsf_mode = xgbe_config_rsf_mode; in xgbe_init_function_ptrs_dev()
3545 hw_if->config_tsf_mode = xgbe_config_tsf_mode; in xgbe_init_function_ptrs_dev()
3547 /* For TX DMA Operating on Second Frame config */ in xgbe_init_function_ptrs_dev()
3548 hw_if->config_osp_mode = xgbe_config_osp_mode; in xgbe_init_function_ptrs_dev()
3551 hw_if->tx_mmc_int = xgbe_tx_mmc_int; in xgbe_init_function_ptrs_dev()
3552 hw_if->rx_mmc_int = xgbe_rx_mmc_int; in xgbe_init_function_ptrs_dev()
3553 hw_if->read_mmc_stats = xgbe_read_mmc_stats; in xgbe_init_function_ptrs_dev()
3555 /* For Data Center Bridging config */ in xgbe_init_function_ptrs_dev()
3556 hw_if->config_tc = xgbe_config_tc; in xgbe_init_function_ptrs_dev()
3557 hw_if->config_dcb_tc = xgbe_config_dcb_tc; in xgbe_init_function_ptrs_dev()
3558 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; in xgbe_init_function_ptrs_dev()
3561 hw_if->enable_rss = xgbe_enable_rss; in xgbe_init_function_ptrs_dev()
3562 hw_if->disable_rss = xgbe_disable_rss; in xgbe_init_function_ptrs_dev()
3563 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; in xgbe_init_function_ptrs_dev()
3564 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; in xgbe_init_function_ptrs_dev()
3567 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded; in xgbe_init_function_ptrs_dev()
3568 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec; in xgbe_init_function_ptrs_dev()
3571 hw_if->enable_vxlan = xgbe_enable_vxlan; in xgbe_init_function_ptrs_dev()
3572 hw_if->disable_vxlan = xgbe_disable_vxlan; in xgbe_init_function_ptrs_dev()
3573 hw_if->set_vxlan_id = xgbe_set_vxlan_id; in xgbe_init_function_ptrs_dev()
3576 hw_if->enable_sph = xgbe_config_sph_mode; in xgbe_init_function_ptrs_dev()
3577 hw_if->disable_sph = xgbe_disable_sph_mode; in xgbe_init_function_ptrs_dev()
3579 DBGPR("<--xgbe_init_function_ptrs\n"); in xgbe_init_function_ptrs_dev()