58 #define LANCE_OBIO 0x120000
62  *  0 = silent, print only serious errors
68 #define	LANCE_DEBUG	0
75 module_param(lance_debug, int, 0);
76 MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)");
84 	} while( 0 )
164 #define	DREG	lp->iobase[0]
171 #define TMD1_ENP		0x01	/* end of packet */
172 #define TMD1_STP		0x02	/* start of packet */
173 #define TMD1_DEF		0x04	/* deferred */
174 #define TMD1_ONE		0x08	/* one retry needed */
175 #define TMD1_MORE		0x10	/* more than one retry needed */
176 #define TMD1_ERR		0x40	/* error summary */
177 #define TMD1_OWN 		0x80	/* ownership (set: chip owns) */
180 #define TMD1_OWN_HOST	0
183 #define TMD3_TDR		0x03FF	/* Time Domain Reflectometry counter */
184 #define TMD3_RTRY		0x0400	/* failed after 16 retries */
185 #define TMD3_LCAR		0x0800	/* carrier lost */
186 #define TMD3_LCOL		0x1000	/* late collision */
187 #define TMD3_UFLO		0x4000	/* underflow (late memory) */
188 #define TMD3_BUFF		0x8000	/* buffering error (no ENP) */
191 #define RMD1_ENP		0x01	/* end of packet */
192 #define RMD1_STP		0x02	/* start of packet */
193 #define RMD1_BUFF		0x04	/* buffer error */
194 #define RMD1_CRC		0x08	/* CRC error */
195 #define RMD1_OFLO		0x10	/* overflow */
196 #define RMD1_FRAM		0x20	/* framing error */
197 #define RMD1_ERR		0x40	/* error summary */
198 #define RMD1_OWN 		0x80	/* ownership (set: ship owns) */
201 #define RMD1_OWN_HOST	0
204 #define CSR0	0		/* mode/status */
213 #define CSR0_INIT	0x0001		/* initialize (RS) */
214 #define CSR0_STRT	0x0002		/* start (RS) */
215 #define CSR0_STOP	0x0004		/* stop (RS) */
216 #define CSR0_TDMD	0x0008		/* transmit demand (RS) */
217 #define CSR0_TXON	0x0010		/* transmitter on (R) */
218 #define CSR0_RXON	0x0020		/* receiver on (R) */
219 #define CSR0_INEA	0x0040		/* interrupt enable (RW) */
220 #define CSR0_INTR	0x0080		/* interrupt active (R) */
221 #define CSR0_IDON	0x0100		/* initialization done (RC) */
222 #define CSR0_TINT	0x0200		/* transmitter interrupt (RC) */
223 #define CSR0_RINT	0x0400		/* receiver interrupt (RC) */
224 #define CSR0_MERR	0x0800		/* memory error (RC) */
225 #define CSR0_MISS	0x1000		/* missed frame (RC) */
226 #define CSR0_CERR	0x2000		/* carrier error (no heartbeat :-) (RC) */
227 #define CSR0_BABL	0x4000		/* babble: tx-ed too many bits (RC) */
228 #define CSR0_ERR	0x8000		/* error (RC) */
231 #define CSR3_BCON	0x0001		/* byte control */
232 #define CSR3_ACON	0x0002		/* ALE control */
233 #define CSR3_BSWP	0x0004		/* byte swap (1=big endian) */
316 		return 0;  in lance_probe()
325 	tmp1 = ioaddr_probe[0];  in lance_probe()
329 	ioaddr_probe[0] = CSR0_INIT | CSR0_STOP;  in lance_probe()
331 	if(ioaddr_probe[0] != CSR0_STOP) {  in lance_probe()
332 		ioaddr_probe[0] = tmp1;  in lance_probe()
338 		return 0;  in lance_probe()
344 	MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000);  in lance_probe()
350 		return 0;  in lance_probe()
358 	if (request_irq(LANCE_IRQ, lance_interrupt, 0, "SUN3 Lance", dev) < 0) {  in lance_probe()
364 		return 0;  in lance_probe()
379 	MEM->init.hwaddr[0] = dev->dev_addr[1];  in lance_probe()
380 	MEM->init.hwaddr[1] = dev->dev_addr[0];  in lance_probe()
388 	MEM->init.mode = 0x0000;  in lance_probe()
389 	MEM->init.filter[0] = 0x00000000;  in lance_probe()
390 	MEM->init.filter[1] = 0x00000000;  in lance_probe()
402 	if (did_version++ == 0)  in lance_probe()
428 	while (--i > 0)  in lance_open()
431 	if (i <= 0 || (DREG & CSR0_ERR)) {  in lance_open()
444 	return 0;  in lance_open()
455 	lp->lock = 0;  in lance_init_ring()
456 	lp->tx_full = 0;  in lance_init_ring()
457 	lp->new_rx = lp->new_tx = 0;  in lance_init_ring()
458 	lp->old_rx = lp->old_tx = 0;  in lance_init_ring()
460 	for( i = 0; i < TX_RING_SIZE; i++ ) {  in lance_init_ring()
462 		MEM->tx_head[i].flag = 0;  in lance_init_ring()
465 		MEM->tx_head[i].length = 0;  in lance_init_ring()
466 		MEM->tx_head[i].misc = 0;  in lance_init_ring()
469 	for( i = 0; i < RX_RING_SIZE; i++ ) {  in lance_init_ring()
474 		MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000;  in lance_init_ring()
475 		MEM->rx_head[i].msg_length = 0;  in lance_init_ring()
479 	MEM->init.hwaddr[0] = dev->dev_addr[1];  in lance_init_ring()
480 	MEM->init.hwaddr[1] = dev->dev_addr[0];  in lance_init_ring()
486 	MEM->init.mode = 0x0000;  in lance_init_ring()
487 	MEM->init.filter[0] = 0x00000000;  in lance_init_ring()
488 	MEM->init.filter[1] = 0x00000000;  in lance_init_ring()
543 			for( i = 0 ; i < RX_RING_SIZE; i++ )  in lance_start_xmit()
548 			for( i = 0 ; i < TX_RING_SIZE; i++ )  in lance_start_xmit()
572 	if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {  in lance_start_xmit()
593 #if 0  in lance_start_xmit()
595 		printk( "%s: TX pkt %d type 0x%04x"  in lance_start_xmit()
597 			" data at 0x%08x len %d\n",  in lance_start_xmit()
620 	head->length = (-len) | 0xf000;  in lance_start_xmit()
621 	head->misc = 0;  in lance_start_xmit()
625 		memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len);  in lance_start_xmit()
638 	lp->lock = 0;  in lance_start_xmit()
681 //			for(i = 0; i < TX_RING_SIZE; i++)  in lance_interrupt()
790 //			short pkt_len = head->msg_length;// & 0xfff;  in lance_rx()
791 			short pkt_len = (head->msg_length & 0xfff) - 4;  in lance_rx()
802 					head->msg_length = 0;  in lance_rx()
808 #if 0  in lance_rx()
811 					printk("%s: RX pkt %d type 0x%04x"  in lance_rx()
825 …			printk( "%s: RX pkt %d type 0x%04x len %d\n ", dev->name, entry, ((u_short *)data)[6], pkt_len);  in lance_rx()
842 //		head->buf_length = -PKT_BUF_SZ | 0xf000;  in lance_rx()
843 		head->msg_length = 0;  in lance_rx()
853 	return 0;  in lance_rx()
871 	return 0;  in lance_close()
877    num_addrs == 0		Normal mode, clear multicast list
878    num_addrs > 0		Multicast mode, receive normal and MC packets, and do
897 		REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */  in set_multicast_list()
904 		memset( multicast_table, (num_addrs == 0) ? 0 : -1,  in set_multicast_list()
906 		for( i = 0; i < 4; i++ )  in set_multicast_list()
908 		REGA( CSR15 ) = 0; /* Unset promiscuous mode */  in set_multicast_list()