Lines Matching +full:tse +full:- +full:mdio
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
113 /* MDIO registers within MAC register Space
120 u32 auto_negotiation_advertisement; /* Auto-negotiation
172 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
176 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
180 /* 14-bit maximum frame length. The MAC receive logic */
186 /* 12-bit receive FIFO section-empty threshold */
188 /* 12-bit receive FIFO section-full threshold */
190 /* 12-bit transmit FIFO section-empty threshold */
192 /* 12-bit transmit FIFO section-full threshold */
194 /* 12-bit receive FIFO almost-empty threshold */
196 /* 12-bit receive FIFO almost-full threshold */
198 /* 12-bit transmit FIFO almost-empty threshold */
200 /* 12-bit transmit FIFO almost-full threshold */
202 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
204 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
207 /* Bit[15:0]—16-bit holdoff quanta */
244 /* IETF MIB (MIB-II) Object Support */
321 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY
404 /* TSE Revision */
465 int phy_addr; /* PHY's MDIO address, -1 for autodetection */
467 struct mii_bus *mdio; member