Lines Matching +full:0 +full:x00010001
15 return 0; in msgdma_initialize()
36 counter = 0; in msgdma_reset()
58 counter = 0; in msgdma_reset()
108 /* return 0 to indicate transmit is pending */
115 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo)); in msgdma_tx_buffer()
116 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi)); in msgdma_tx_buffer()
118 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num)); in msgdma_tx_buffer()
123 return 0; in msgdma_tx_buffer()
128 u32 ready = 0; in msgdma_tx_completions()
134 & 0xffff; in msgdma_tx_completions()
138 priv->tx_prod - priv->tx_cons - inuse - 1, 0); in msgdma_tx_completions()
164 csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo)); in msgdma_add_rx_desc()
165 csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi)); in msgdma_add_rx_desc()
171 csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num)); in msgdma_add_rx_desc()
172 csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride)); in msgdma_add_rx_desc()
181 u32 rxstatus = 0; in msgdma_rx_status()
186 & 0xffff) { in msgdma_rx_status()
193 rxstatus |= (pktlength & 0xffff); in msgdma_rx_status()