Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
33 #define FE_DMA_GLO_PG_SZ_MASK BIT(3)
36 #define FE_RST_GDM4_MBI_ARB_MASK BIT(3)
37 #define FE_RST_GDM3_MBI_ARB_MASK BIT(2)
38 #define FE_RST_CORE_MASK BIT(0)
43 #define WAN1_EN_MASK BIT(16)
59 #define PCE_DPI_EN_MASK BIT(2)
60 #define PCE_KA_EN_MASK BIT(1)
61 #define PCE_MC_EN_MASK BIT(0)
65 #define PSE_CFG_QUEUE_ID_MASK GENMASK(20, 16)
66 #define PSE_CFG_WR_EN_MASK BIT(8)
67 #define PSE_CFG_OQRSV_SEL_MASK BIT(0)
76 #define PSE_SHARE_USED_LTHD_MASK GENMASK(31, 16)
80 #define PSE_SHARE_USED_MTHD_MASK GENMASK(31, 16)
84 #define GDM2_RDM_ACK_WAIT_PREF_MASK BIT(9)
85 #define GDM2_CHN_VLD_MODE_MASK BIT(5)
88 #define FE_IFC_EN_MASK BIT(0)
94 #define PSE_IQ_RES1_P2_MASK GENMASK(23, 16)
101 #define PATN_FCPU_EN_MASK BIT(7)
102 #define PATN_SWP_EN_MASK BIT(6)
103 #define PATN_DP_EN_MASK BIT(5)
104 #define PATN_SP_EN_MASK BIT(4)
106 #define PATN_EN_MASK BIT(0)
109 #define PATN_DP_MASK GENMASK(31, 16)
113 #define CDM1_VLAN_MASK GENMASK(31, 16)
131 #define GDM_DROP_CRC_ERR BIT(23)
132 #define GDM_IP4_CKSUM BIT(22)
133 #define GDM_TCP_CKSUM BIT(21)
134 #define GDM_UDP_CKSUM BIT(20)
135 #define GDM_STRIP_CRC BIT(16)
142 #define GDM_INGRESS_FC_EN_MASK BIT(1)
143 #define GDM_STAG_EN_MASK BIT(0)
147 #define GDM_LONG_LEN_MASK GENMASK(29, 16)
154 #define LBK_GAP_MODE_MASK BIT(3)
155 #define LBK_LEN_MODE_MASK BIT(2)
156 #define LBK_CHAN_MODE_MASK BIT(1)
157 #define LPBK_EN_MASK BIT(0)
163 #define FE_CPORT_PAD BIT(26)
164 #define FE_CPORT_PORT_XFC_MASK BIT(25)
165 #define FE_CPORT_QUEUE_XFC_MASK BIT(24)
168 #define FE_GDM_MIB_RX_CLEAR_MASK BIT(1)
169 #define FE_GDM_MIB_TX_CLEAR_MASK BIT(0)
172 #define FE_STRICT_RFC2819_MODE_MASK BIT(31)
173 #define FE_GDM1_TX_MIB_SPLIT_EN_MASK BIT(17)
174 #define FE_GDM1_RX_MIB_SPLIT_EN_MASK BIT(16)
218 #define PPE_GLO_CFG_BUSY_MASK BIT(31)
219 #define PPE_GLO_CFG_FLOW_DROP_UPDATE_MASK BIT(9)
220 #define PPE_GLO_CFG_PSE_HASH_OFS_MASK BIT(6)
221 #define PPE_GLO_CFG_PPE_BSWAP_MASK BIT(5)
222 #define PPE_GLO_CFG_TTL_DROP_MASK BIT(4)
223 #define PPE_GLO_CFG_IP4_CS_DROP_MASK BIT(3)
224 #define PPE_GLO_CFG_IP4_L4_CS_DROP_MASK BIT(2)
225 #define PPE_GLO_CFG_EN_MASK BIT(0)
228 #define PPE_FLOW_CFG_IP6_HASH_GRE_KEY_MASK BIT(20)
229 #define PPE_FLOW_CFG_IP4_HASH_GRE_KEY_MASK BIT(19)
230 #define PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL_MASK BIT(18)
231 #define PPE_FLOW_CFG_IP4_NAT_FRAG_MASK BIT(17)
232 #define PPE_FLOW_CFG_IP_PROTO_BLACKLIST_MASK BIT(16)
233 #define PPE_FLOW_CFG_IP4_DSLITE_MASK BIT(14)
234 #define PPE_FLOW_CFG_IP4_NAPT_MASK BIT(13)
235 #define PPE_FLOW_CFG_IP4_NAT_MASK BIT(12)
236 #define PPE_FLOW_CFG_IP6_6RD_MASK BIT(10)
237 #define PPE_FLOW_CFG_IP6_5T_ROUTE_MASK BIT(9)
238 #define PPE_FLOW_CFG_IP6_3T_ROUTE_MASK BIT(8)
239 #define PPE_FLOW_CFG_IP4_UDP_FRAG_MASK BIT(7)
240 #define PPE_FLOW_CFG_IP4_TCP_FRAG_MASK BIT(6)
243 #define PPE_IP_PROTO_CHK_IPV4_MASK GENMASK(31, 16)
249 #define PPE_TB_CFG_AGE_TCP_FIN_MASK BIT(11)
250 #define PPE_TB_CFG_AGE_UDP_MASK BIT(10)
251 #define PPE_TB_CFG_AGE_TCP_MASK BIT(9)
252 #define PPE_TB_CFG_AGE_UNBIND_MASK BIT(8)
253 #define PPE_TB_CFG_AGE_NON_L4_MASK BIT(7)
254 #define PPE_TB_CFG_AGE_PREBIND_MASK BIT(6)
256 #define PPE_TB_ENTRY_SIZE_MASK BIT(3)
262 #define PPE_BIND_RATE_L2B_BIND_MASK GENMASK(31, 16)
266 #define PPE_BIND_LIMIT0_HALF_MASK GENMASK(29, 16)
270 #define PPE_BIND_LIMIT1_NON_L4_MASK GENMASK(23, 16)
274 #define PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)
278 #define PPE_UNBIND_AGE_MIN_PACKETS_MASK GENMASK(31, 16)
282 #define PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)
295 #define PPE_DRAM_HASH1_EN_MASK BIT(24)
297 #define PPE_DRAM_TABLE_EN_MASK BIT(16)
299 #define PPE_SRAM_HASH1_EN_MASK BIT(8)
301 #define PPE_SRAM_TABLE_EN_MASK BIT(0)
305 #define FP1_EGRESS_MTU_MASK GENMASK(29, 16)
309 #define PPE_SRAM_CTRL_ACK_MASK BIT(31)
310 #define PPE_SRAM_CTRL_DUAL_SUCESS_MASK BIT(30)
312 #define PPE_SRAM_WR_DUAL_DIRECTION_MASK BIT(2)
313 #define PPE_SRAM_CTRL_WR_MASK BIT(1)
314 #define PPE_SRAM_CTRL_REQ_MASK BIT(0)
320 #define PPE_UPDMEM_ACK_MASK BIT(31)
324 #define PPE_UPDMEM_WR_MASK BIT(1)
325 #define PPE_UPDMEM_REQ_MASK BIT(0)
356 #define GDM3_PAD_EN_MASK BIT(28)
359 #define GDM4_PAD_EN_MASK BIT(28)
363 #define GDM4_SPORT_OFF2_MASK GENMASK(19, 16)
369 #define IP_ASSEMBLE_NBQ_MASK GENMASK(20, 16)
374 #define MC_VLAN_EN_MASK BIT(0)
377 #define MC_VLAN_CFG_CMD_DONE_MASK BIT(31)
378 #define MC_VLAN_CFG_TABLE_ID_MASK GENMASK(21, 16)
380 #define MC_VLAN_CFG_TABLE_SEL_MASK BIT(4)
381 #define MC_VLAN_CFG_RW_MASK BIT(0)
393 #define FC_ID_OF_SRC_PORT26_MASK GENMASK(20, 16)
401 #define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31)
403 #define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28)
404 #define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27)
405 #define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26)
406 #define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25)
407 #define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24)
408 #define GLOBAL_CFG_RESET_MASK BIT(23)
409 #define GLOBAL_CFG_RESET_DONE_MASK BIT(22)
410 #define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21)
411 #define GLOBAL_CFG_IRQ1_EN_MASK BIT(20)
412 #define GLOBAL_CFG_IRQ0_EN_MASK BIT(19)
413 #define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18)
414 #define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17)
415 #define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16)
417 #define GLOBAL_CFG_CHECK_DONE_MASK BIT(7)
418 #define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6)
420 #define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3)
421 #define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2)
422 #define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1)
423 #define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0)
430 #define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16)
447 #define RX15_COHERENT_INT_MASK BIT(31)
448 #define RX14_COHERENT_INT_MASK BIT(30)
449 #define RX13_COHERENT_INT_MASK BIT(29)
450 #define RX12_COHERENT_INT_MASK BIT(28)
451 #define RX11_COHERENT_INT_MASK BIT(27)
452 #define RX10_COHERENT_INT_MASK BIT(26)
453 #define RX9_COHERENT_INT_MASK BIT(25)
454 #define RX8_COHERENT_INT_MASK BIT(24)
455 #define RX7_COHERENT_INT_MASK BIT(23)
456 #define RX6_COHERENT_INT_MASK BIT(22)
457 #define RX5_COHERENT_INT_MASK BIT(21)
458 #define RX4_COHERENT_INT_MASK BIT(20)
459 #define RX3_COHERENT_INT_MASK BIT(19)
460 #define RX2_COHERENT_INT_MASK BIT(18)
461 #define RX1_COHERENT_INT_MASK BIT(17)
462 #define RX0_COHERENT_INT_MASK BIT(16)
463 #define TX7_COHERENT_INT_MASK BIT(15)
464 #define TX6_COHERENT_INT_MASK BIT(14)
465 #define TX5_COHERENT_INT_MASK BIT(13)
466 #define TX4_COHERENT_INT_MASK BIT(12)
467 #define TX3_COHERENT_INT_MASK BIT(11)
468 #define TX2_COHERENT_INT_MASK BIT(10)
469 #define TX1_COHERENT_INT_MASK BIT(9)
470 #define TX0_COHERENT_INT_MASK BIT(8)
471 #define CNT_OVER_FLOW_INT_MASK BIT(7)
472 #define IRQ1_FULL_INT_MASK BIT(5)
473 #define IRQ1_INT_MASK BIT(4)
474 #define HWFWD_DSCP_LOW_INT_MASK BIT(3)
475 #define HWFWD_DSCP_EMPTY_INT_MASK BIT(2)
476 #define IRQ0_FULL_INT_MASK BIT(1)
477 #define IRQ0_INT_MASK BIT(0)
508 #define RX15_NO_CPU_DSCP_INT_MASK BIT(31)
509 #define RX14_NO_CPU_DSCP_INT_MASK BIT(30)
510 #define RX13_NO_CPU_DSCP_INT_MASK BIT(29)
511 #define RX12_NO_CPU_DSCP_INT_MASK BIT(28)
512 #define RX11_NO_CPU_DSCP_INT_MASK BIT(27)
513 #define RX10_NO_CPU_DSCP_INT_MASK BIT(26)
514 #define RX9_NO_CPU_DSCP_INT_MASK BIT(25)
515 #define RX8_NO_CPU_DSCP_INT_MASK BIT(24)
516 #define RX7_NO_CPU_DSCP_INT_MASK BIT(23)
517 #define RX6_NO_CPU_DSCP_INT_MASK BIT(22)
518 #define RX5_NO_CPU_DSCP_INT_MASK BIT(21)
519 #define RX4_NO_CPU_DSCP_INT_MASK BIT(20)
520 #define RX3_NO_CPU_DSCP_INT_MASK BIT(19)
521 #define RX2_NO_CPU_DSCP_INT_MASK BIT(18)
522 #define RX1_NO_CPU_DSCP_INT_MASK BIT(17)
523 #define RX0_NO_CPU_DSCP_INT_MASK BIT(16)
524 #define RX15_DONE_INT_MASK BIT(15)
525 #define RX14_DONE_INT_MASK BIT(14)
526 #define RX13_DONE_INT_MASK BIT(13)
527 #define RX12_DONE_INT_MASK BIT(12)
528 #define RX11_DONE_INT_MASK BIT(11)
529 #define RX10_DONE_INT_MASK BIT(10)
530 #define RX9_DONE_INT_MASK BIT(9)
531 #define RX8_DONE_INT_MASK BIT(8)
532 #define RX7_DONE_INT_MASK BIT(7)
533 #define RX6_DONE_INT_MASK BIT(6)
534 #define RX5_DONE_INT_MASK BIT(5)
535 #define RX4_DONE_INT_MASK BIT(4)
536 #define RX3_DONE_INT_MASK BIT(3)
537 #define RX2_DONE_INT_MASK BIT(2)
538 #define RX1_DONE_INT_MASK BIT(1)
539 #define RX0_DONE_INT_MASK BIT(0)
567 #define RX31_NO_CPU_DSCP_INT_MASK BIT(31)
568 #define RX30_NO_CPU_DSCP_INT_MASK BIT(30)
569 #define RX29_NO_CPU_DSCP_INT_MASK BIT(29)
570 #define RX28_NO_CPU_DSCP_INT_MASK BIT(28)
571 #define RX27_NO_CPU_DSCP_INT_MASK BIT(27)
572 #define RX26_NO_CPU_DSCP_INT_MASK BIT(26)
573 #define RX25_NO_CPU_DSCP_INT_MASK BIT(25)
574 #define RX24_NO_CPU_DSCP_INT_MASK BIT(24)
575 #define RX23_NO_CPU_DSCP_INT_MASK BIT(23)
576 #define RX22_NO_CPU_DSCP_INT_MASK BIT(22)
577 #define RX21_NO_CPU_DSCP_INT_MASK BIT(21)
578 #define RX20_NO_CPU_DSCP_INT_MASK BIT(20)
579 #define RX19_NO_CPU_DSCP_INT_MASK BIT(19)
580 #define RX18_NO_CPU_DSCP_INT_MASK BIT(18)
581 #define RX17_NO_CPU_DSCP_INT_MASK BIT(17)
582 #define RX16_NO_CPU_DSCP_INT_MASK BIT(16)
583 #define RX31_DONE_INT_MASK BIT(15)
584 #define RX30_DONE_INT_MASK BIT(14)
585 #define RX29_DONE_INT_MASK BIT(13)
586 #define RX28_DONE_INT_MASK BIT(12)
587 #define RX27_DONE_INT_MASK BIT(11)
588 #define RX26_DONE_INT_MASK BIT(10)
589 #define RX25_DONE_INT_MASK BIT(9)
590 #define RX24_DONE_INT_MASK BIT(8)
591 #define RX23_DONE_INT_MASK BIT(7)
592 #define RX22_DONE_INT_MASK BIT(6)
593 #define RX21_DONE_INT_MASK BIT(5)
594 #define RX20_DONE_INT_MASK BIT(4)
595 #define RX19_DONE_INT_MASK BIT(3)
596 #define RX18_DONE_INT_MASK BIT(2)
597 #define RX17_DONE_INT_MASK BIT(1)
598 #define RX16_DONE_INT_MASK BIT(0)
629 #define RX31_COHERENT_INT_MASK BIT(31)
630 #define RX30_COHERENT_INT_MASK BIT(30)
631 #define RX29_COHERENT_INT_MASK BIT(29)
632 #define RX28_COHERENT_INT_MASK BIT(28)
633 #define RX27_COHERENT_INT_MASK BIT(27)
634 #define RX26_COHERENT_INT_MASK BIT(26)
635 #define RX25_COHERENT_INT_MASK BIT(25)
636 #define RX24_COHERENT_INT_MASK BIT(24)
637 #define RX23_COHERENT_INT_MASK BIT(23)
638 #define RX22_COHERENT_INT_MASK BIT(22)
639 #define RX21_COHERENT_INT_MASK BIT(21)
640 #define RX20_COHERENT_INT_MASK BIT(20)
641 #define RX19_COHERENT_INT_MASK BIT(19)
642 #define RX18_COHERENT_INT_MASK BIT(18)
643 #define RX17_COHERENT_INT_MASK BIT(17)
644 #define RX16_COHERENT_INT_MASK BIT(16)
659 #define TX31_COHERENT_INT_MASK BIT(31)
660 #define TX30_COHERENT_INT_MASK BIT(30)
661 #define TX29_COHERENT_INT_MASK BIT(29)
662 #define TX28_COHERENT_INT_MASK BIT(28)
663 #define TX27_COHERENT_INT_MASK BIT(27)
664 #define TX26_COHERENT_INT_MASK BIT(26)
665 #define TX25_COHERENT_INT_MASK BIT(25)
666 #define TX24_COHERENT_INT_MASK BIT(24)
667 #define TX23_COHERENT_INT_MASK BIT(23)
668 #define TX22_COHERENT_INT_MASK BIT(22)
669 #define TX21_COHERENT_INT_MASK BIT(21)
670 #define TX20_COHERENT_INT_MASK BIT(20)
671 #define TX19_COHERENT_INT_MASK BIT(19)
672 #define TX18_COHERENT_INT_MASK BIT(18)
673 #define TX17_COHERENT_INT_MASK BIT(17)
674 #define TX16_COHERENT_INT_MASK BIT(16)
675 #define TX15_COHERENT_INT_MASK BIT(15)
676 #define TX14_COHERENT_INT_MASK BIT(14)
677 #define TX13_COHERENT_INT_MASK BIT(13)
678 #define TX12_COHERENT_INT_MASK BIT(12)
679 #define TX11_COHERENT_INT_MASK BIT(11)
680 #define TX10_COHERENT_INT_MASK BIT(10)
681 #define TX9_COHERENT_INT_MASK BIT(9)
682 #define TX8_COHERENT_INT_MASK BIT(8)
701 #define TX_IRQ_THR_MASK GENMASK(27, 16)
708 #define IRQ_ENTRY_LEN_MASK GENMASK(27, 16)
712 (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5))
715 (((_n) < 8) ? 0x0104 + ((_n) << 5) : 0x0b04 + (((_n) - 8) << 5))
717 #define TX_RING_IRQ_BLOCKING_MAP_MASK BIT(6)
718 #define TX_RING_IRQ_BLOCKING_CFG_MASK BIT(4)
719 #define TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK BIT(2)
720 #define TX_RING_IRQ_BLOCKING_MAX_TH_TXRING_EN_MASK BIT(1)
721 #define TX_RING_IRQ_BLOCKING_MIN_TH_TXRING_EN_MASK BIT(0)
724 (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5))
729 (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5))
733 #define IRQ_RING_IDX_MASK GENMASK(20, 16)
737 (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5))
740 (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5))
742 #define RX_RING_THR_MASK GENMASK(31, 16)
746 (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5))
751 (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5))
754 (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
757 (((_n) < 16) ? 0x0214 + ((_n) << 5) : 0x0e14 + (((_n) - 16) << 5))
763 #define RX_RING_SG_EN_MASK BIT(0)
766 #define INGRESS_TRTCM_EN_MASK BIT(31)
767 #define INGRESS_TRTCM_MODE_MASK BIT(30)
768 #define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
772 #define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) BIT((_m) + (((_n) & 0x3) << 3))
778 #define CNTR_EN_MASK BIT(31)
779 #define CNTR_ALL_CHAN_EN_MASK BIT(30)
780 #define CNTR_ALL_QUEUE_EN_MASK BIT(29)
781 #define CNTR_ALL_DSCP_RING_EN_MASK BIT(28)
783 #define CNTR_DSCP_RING_MASK GENMASK(20, 16)
790 #define LMGR_INIT_START BIT(31)
791 #define LMGR_SRAM_MODE_MASK BIT(30)
793 #define HW_FWD_DESC_NUM_MASK GENMASK(16, 0)
799 #define EGRESS_RATE_METER_EN_MASK BIT(31)
800 #define EGRESS_RATE_METER_EQ_RATE_EN_MASK BIT(17)
801 #define EGRESS_RATE_METER_WINDOW_SZ_MASK GENMASK(16, 12)
805 #define EGRESS_TRTCM_EN_MASK BIT(31)
806 #define EGRESS_TRTCM_MODE_MASK BIT(30)
807 #define EGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
810 #define TRTCM_PARAM_RW_MASK BIT(31)
811 #define TRTCM_PARAM_RW_DONE_MASK BIT(30)
815 #define TRTCM_PARAM_RATE_TYPE_MASK BIT(16)
821 #define RATE_LIMIT_PARAM_RW_MASK BIT(31)
822 #define RATE_LIMIT_PARAM_RW_DONE_MASK BIT(30)
825 #define RATE_LIMIT_PARAM_INDEX_MASK GENMASK(23, 16)
828 #define TWRR_WEIGHT_SCALE_MASK BIT(31)
829 #define TWRR_WEIGHT_BASE_MASK BIT(3)
832 #define TWRR_RW_CMD_MASK BIT(31)
833 #define TWRR_RW_CMD_DONE BIT(30)
835 #define TWRR_QUEUE_IDX_MASK GENMASK(18, 16)
839 #define PSE_BUF_ESTIMATE_EN_MASK BIT(29)
845 #define GLB_TRTCM_EN_MASK BIT(31)
846 #define GLB_TRTCM_MODE_MASK BIT(30)
847 #define GLB_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
851 #define TXQ_CNGST_DROP_EN BIT(31)
852 #define TXQ_CNGST_DEI_DROP_EN BIT(30)
855 #define SLA_TRTCM_EN_MASK BIT(31)
856 #define SLA_TRTCM_MODE_MASK BIT(30)
857 #define SLA_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
861 #define QDMA_DESC_DONE_MASK BIT(31)
862 #define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */
863 #define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */
864 #define QDMA_DESC_DEI_MASK BIT(25)
865 #define QDMA_DESC_NO_DROP_MASK BIT(24)
870 #define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30)
872 #define QDMA_ETH_TXMSG_ICO_MASK BIT(13)
873 #define QDMA_ETH_TXMSG_UCO_MASK BIT(12)
874 #define QDMA_ETH_TXMSG_TCO_MASK BIT(11)
875 #define QDMA_ETH_TXMSG_TSO_MASK BIT(10)
876 #define QDMA_ETH_TXMSG_FAST_MASK BIT(9)
877 #define QDMA_ETH_TXMSG_OAM_MASK BIT(8)
881 #define QDMA_ETH_TXMSG_NO_DROP BIT(31)
885 #define QDMA_ETH_TXMSG_HWF_MASK BIT(14)
886 #define QDMA_ETH_TXMSG_HOP_MASK BIT(13)
887 #define QDMA_ETH_TXMSG_PTP_MASK BIT(12)
894 #define QDMA_ETH_RXMSG_DEI_MASK BIT(31)
895 #define QDMA_ETH_RXMSG_IP6_MASK BIT(30)
896 #define QDMA_ETH_RXMSG_IP4_MASK BIT(29)
897 #define QDMA_ETH_RXMSG_IP4F_MASK BIT(28)
898 #define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27)
899 #define QDMA_ETH_RXMSG_L4F_MASK BIT(26)
901 #define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16)
916 #define QDMA_FWD_DESC_CTX_MASK BIT(31)
918 #define QDMA_FWD_DESC_IDX_MASK GENMASK(27, 16)