Lines Matching full:structure

87 /* structure for power management control status reg in global address map
183 /* structure for txdma packet ring base address hi reg in txdma address map
188 /* structure for txdma packet ring base address low reg in txdma address map
193 /* structure for txdma packet ring number of descriptor reg in txdma address
221  * structure for txdma service complete reg in txdma address map at 0x1028
271 /* structure for control status reg in rxdma address map
300 /* structure for dma writeback lo reg in rxdma address map
305 /* structure for dma writeback hi reg in rxdma address map
310 /* structure for number of packets done reg in rxdma address map
317 /* structure for max packet time reg in rxdma address map
324 /* structure for rx queue read address reg in rxdma address map
329 /* structure for rx queue read address external reg in rxdma address map
334 /* structure for rx queue write address reg in rxdma address map
339 /* structure for packet status ring base address lo reg in rxdma address map
344 /* structure for packet status ring base address hi reg in rxdma address map
349 /* structure for packet status ring number of descriptors reg in rxdma address
357 /* structure for packet status ring available offset reg in rxdma address map
365 /* structure for packet status ring full offset reg in rxdma address map
373 /* structure for packet status ring access index reg in rxdma address map
380 /* structure for packet status ring minimum descriptors reg in rxdma address
387 /* structure for free buffer ring base lo address reg in rxdma address map
392 /* structure for free buffer ring base hi address reg in rxdma address map
397 /* structure for free buffer ring number of descriptors reg in rxdma address
404 /* structure for free buffer ring 0 available offset reg in rxdma address map
409 /* structure for free buffer ring 0 full offset reg in rxdma address map
414 /* structure for free buffer cache 0 full offset reg in rxdma address map
421 /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
428 /* structure for free buffer ring 1 base address lo reg in rxdma address map
433 /* structure for free buffer ring 1 number of descriptors reg in rxdma address
438 /* structure for free buffer ring 1 available offset reg in rxdma address map
443 /* structure for free buffer ring 1 full offset reg in rxdma address map
448 /* structure for free buffer cache 1 read index reg in rxdma address map
453 /* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
496 /* structure for control reg in txmac address map
513 /* structure for shadow pointer reg in txmac address map
521 /* structure for error count reg in txmac address map
530 /* structure for max fill reg in txmac address map
536 /* structure for cf parameter reg in txmac address map
542 /* structure for tx test reg in txmac address map
551 /* structure for error reg in txmac address map
565 /* structure for error interrupt reg in txmac address map
579 /* structure for error interrupt reg in txmac address map
605 /* structure for rxmac control reg in rxmac address map
620 /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
634 /* structure for CRC 1 and CRC 2 reg in rxmac address map
641 /* structure for CRC 3 and CRC 4 reg in rxmac address map
648 /* structure for Wake On Lan Source Address Lo reg in rxmac address map
660 /* structure for Wake On Lan Source Address Hi reg in rxmac address map
669 /* structure for Wake On Lan mask reg in rxmac address map
674 /* structure for Unicast Packet Filter Address 1 reg in rxmac address map
686 /* structure for Unicast Packet Filter Address 2 reg in rxmac address map
698 /* structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
710 /* structure for Multicast Hash reg in rxmac address map
715 /* structure for Packet Filter Control reg in rxmac address map
732 /* structure for Memory Controller Interface Control Max Segment reg in rxmac
744 /* structure for Memory Controller Interface Water Mark reg in rxmac address
753 /* structure for Rx Queue Dialog reg in rxmac address map.
762 /* structure for space available reg in rxmac address map.
771 /* structure for management interface reg in rxmac address map.
779 /* structure for Error reg in rxmac address map.
838 /* structure for configuration #1 reg in mac address map.
871 /* structure for configuration #2 reg in mac address map.
895 /* structure for Interpacket gap reg in mac address map.
905  * structure for half duplex reg in mac address map.
918 /* structure for Maximum Frame Length reg in mac address map.
922 /* structure for Reserve 1 reg in mac address map.
927 /* structure for Test reg in mac address map.
932 /* structure for MII Management Configuration reg in mac address map.
944 /* structure for MII Management Command reg in mac address map.
950 /* structure for MII Management Address reg in mac address map.
959 /* structure for MII Management Control reg in mac address map.
965 /* structure for MII Management Status reg in mac address map.
972 /* structure for MII Management Indicators reg in mac address map.
982 /* structure for Interface Control reg in mac address map.
1006 /* structure for Interface Status reg in mac address map.
1022 /* structure for Mac Station Address, Part 1 reg in mac address map.
1034 /* structure for Mac Station Address, Part 2 reg in mac address map.
1070 /* structure for Carry Register One and it's Mask Register reg located in mac
1100 /* structure for Carry Register Two Mask Register reg in mac stat address map.
1203 /* structure for Main Memory Controller Host Memory Access Data reg in mmc