Lines Matching +full:0 +full:x4048
53 #define LBCIF_DWORD0_GROUP 0xAC
54 #define LBCIF_DWORD1_GROUP 0xB0
57 #define LBCIF_ADDRESS_REGISTER 0xAC
58 #define LBCIF_DATA_REGISTER 0xB0
59 #define LBCIF_CONTROL_REGISTER 0xB1
60 #define LBCIF_STATUS_REGISTER 0xB2
63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
64 #define LBCIF_CONTROL_PAGE_WRITE 0x02
65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
67 #define LBCIF_CONTROL_I2C_WRITE 0x40
68 #define LBCIF_CONTROL_LBCIF_ENABLE 0x80
71 #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
72 #define LBCIF_STATUS_I2C_IDLE 0x02
73 #define LBCIF_STATUS_ACK_ERROR 0x04
74 #define LBCIF_STATUS_GENERAL_ERROR 0x08
75 #define LBCIF_STATUS_CHECKSUM_ERROR 0x40
76 #define LBCIF_STATUS_EEPROM_PRESENT 0x80
81 * Tx queue start address reg in global address map at address 0x0000
82 * tx queue end address reg in global address map at address 0x0004
83 * rx queue start address reg in global address map at address 0x0008
84 * rx queue end address reg in global address map at address 0x000C
88 * located at address 0x0010
98 * gigephy_en bit 0
100 #define ET_PM_PHY_SW_COMA 0x40
101 #define ET_PMCSR_INIT 0x38
103 /* Interrupt status reg at address 0x0018
105 #define ET_INTR_TXDMA_ISR 0x00000008
106 #define ET_INTR_TXDMA_ERR 0x00000010
107 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
108 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
109 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
110 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
111 #define ET_INTR_RXDMA_ERR 0x00000200
112 #define ET_INTR_WATCHDOG 0x00004000
113 #define ET_INTR_WOL 0x00008000
114 #define ET_INTR_PHY 0x00010000
115 #define ET_INTR_TXMAC 0x00020000
116 #define ET_INTR_RXMAC 0x00040000
117 #define ET_INTR_MAC_STAT 0x00080000
118 #define ET_INTR_SLV_TIMEOUT 0x00100000
120 /* Interrupt mask register at address 0x001C
121 * Interrupt alias clear mask reg at address 0x0020
122 * Interrupt status alias reg at address 0x0024
127 /* Software reset reg at address 0x0028
128 * 0: txdma_sw_reset
137 #define ET_RESET_ALL 0x007F
139 /* SLV Timer reg at address 0x002C (low 24 bits)
142 /* MSI Configuration reg at address 0x0030
144 #define ET_MSI_VECTOR 0x0000001F
145 #define ET_MSI_TC 0x00070000
147 /* Loopback reg located at address 0x0034
149 #define ET_LOOP_MAC 0x00000001
150 #define ET_LOOP_DMA 0x00000002
153 * Located at address 0x0000
156 u32 txq_start_addr; /* 0x0000 */
157 u32 txq_end_addr; /* 0x0004 */
158 u32 rxq_start_addr; /* 0x0008 */
159 u32 rxq_end_addr; /* 0x000C */
160 u32 pm_csr; /* 0x0010 */
161 u32 unused; /* 0x0014 */
162 u32 int_status; /* 0x0018 */
163 u32 int_mask; /* 0x001C */
164 u32 int_alias_clr_en; /* 0x0020 */
165 u32 int_status_alias; /* 0x0024 */
166 u32 sw_reset; /* 0x0028 */
167 u32 slv_timer; /* 0x002C */
168 u32 msi_config; /* 0x0030 */
169 u32 loopback; /* 0x0034 */
170 u32 watchdog_timer; /* 0x0038 */
174 /* txdma control status reg at address 0x1000
176 #define ET_TXDMA_CSR_HALT 0x00000001
177 #define ET_TXDMA_DROP_TLP 0x00000002
178 #define ET_TXDMA_CACHE_THRS 0x000000F0
180 #define ET_TXDMA_SNGL_EPKT 0x00000100
181 #define ET_TXDMA_CLASS 0x00001E00
184 * located at address 0x1004
189 * located at address 0x1008
194 * map. Located at address 0x100C
197 * 9-0: pr ndes
199 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
200 #define ET_DMA12_WRAP 0x1000
201 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
202 #define ET_DMA10_WRAP 0x0400
203 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
204 #define ET_DMA4_WRAP 0x0010
211 * txdma tx queue write address reg in txdma address map at 0x1010
212 * txdma tx queue write address external reg in txdma address map at 0x1014
213 * txdma tx queue read address reg in txdma address map at 0x1018
217 * txdma status writeback address lo reg in txdma address map at 0x1020
220 * txdma service request reg in txdma address map at 0x1024
221 * structure for txdma service complete reg in txdma address map at 0x1028
224 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
225 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
227 * txdma error reg in txdma address map at address 0x1034
228 * 0: PyldResend
237 * Located at address 0x1000
240 u32 csr; /* 0x1000 */
241 u32 pr_base_hi; /* 0x1004 */
242 u32 pr_base_lo; /* 0x1008 */
243 u32 pr_num_des; /* 0x100C */
244 u32 txq_wr_addr; /* 0x1010 */
245 u32 txq_wr_addr_ext; /* 0x1014 */
246 u32 txq_rd_addr; /* 0x1018 */
247 u32 dma_wb_base_hi; /* 0x101C */
248 u32 dma_wb_base_lo; /* 0x1020 */
249 u32 service_request; /* 0x1024 */
250 u32 service_complete; /* 0x1028 */
251 u32 cache_rd_index; /* 0x102C */
252 u32 cache_wr_index; /* 0x1030 */
253 u32 tx_dma_error; /* 0x1034 */
254 u32 desc_abort_cnt; /* 0x1038 */
255 u32 payload_abort_cnt; /* 0x103c */
256 u32 writeback_abort_cnt; /* 0x1040 */
257 u32 desc_timeout_cnt; /* 0x1044 */
258 u32 payload_timeout_cnt; /* 0x1048 */
259 u32 writeback_timeout_cnt; /* 0x104c */
260 u32 desc_error_cnt; /* 0x1050 */
261 u32 payload_error_cnt; /* 0x1054 */
262 u32 writeback_error_cnt; /* 0x1058 */
263 u32 dropped_tlp_cnt; /* 0x105c */
264 u32 new_service_complete; /* 0x1060 */
265 u32 ethernet_packet_cnt; /* 0x1064 */
272 * Located at address 0x2000
275 * 0: halt
291 #define ET_RXDMA_CSR_HALT 0x0001
292 #define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100
293 #define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200
294 #define ET_RXDMA_CSR_FBR0_ENABLE 0x0400
295 #define ET_RXDMA_CSR_FBR1_SIZE_LO 0x0800
296 #define ET_RXDMA_CSR_FBR1_SIZE_HI 0x1000
297 #define ET_RXDMA_CSR_FBR1_ENABLE 0x2000
298 #define ET_RXDMA_CSR_HALT_STATUS 0x00020000
301 * located at address 0x2004
306 * located at address 0x2008
311 * located at address 0x200C
314 * 7-0: num done
318 * located at address 0x2010
321 * 17-0: time done
325 * located at address 0x2014
330 * located at address 0x2018
335 * located at address 0x201C
340 * located at address 0x2020
345 * located at address 0x2024
350 * map. Located at address 0x2028
353 * 11-0: psr ndes
355 #define ET_RXDMA_PSR_NUM_DES_MASK 0xFFF
358 * located at address 0x202C
362 * 11-0: psr avail
366 * located at address 0x2030
370 * 11-0: psr full
374 * located at address 0x2034
377 * 4-0: psr_ai
381 * map. Located at address 0x2038
384 * 11-0: psr_min
388 * located at address 0x203C
393 * located at address 0x2040
398 * map. Located at address 0x2044
401 * 9-0: fbr ndesc
404 /* structure for free buffer ring 0 available offset reg in rxdma address map
405 * located at address 0x2048
409 /* structure for free buffer ring 0 full offset reg in rxdma address map
410 * located at address 0x204C
414 /* structure for free buffer cache 0 full offset reg in rxdma address map
415 * located at address 0x2050
418 * 4-0: fbc rdi
421 /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
422 * located at address 0x2054
425 * 9-0: fbr min
429 * located at address 0x2058 - 0x205C
434 * map. Located at address 0x2060
439 * located at address 0x2064
444 * located at address 0x2068
449 * located at address 0x206C
454 * located at address 0x2070
459 * Located at address 0x2000
462 u32 csr; /* 0x2000 */
463 u32 dma_wb_base_lo; /* 0x2004 */
464 u32 dma_wb_base_hi; /* 0x2008 */
465 u32 num_pkt_done; /* 0x200C */
466 u32 max_pkt_time; /* 0x2010 */
467 u32 rxq_rd_addr; /* 0x2014 */
468 u32 rxq_rd_addr_ext; /* 0x2018 */
469 u32 rxq_wr_addr; /* 0x201C */
470 u32 psr_base_lo; /* 0x2020 */
471 u32 psr_base_hi; /* 0x2024 */
472 u32 psr_num_des; /* 0x2028 */
473 u32 psr_avail_offset; /* 0x202C */
474 u32 psr_full_offset; /* 0x2030 */
475 u32 psr_access_index; /* 0x2034 */
476 u32 psr_min_des; /* 0x2038 */
477 u32 fbr0_base_lo; /* 0x203C */
478 u32 fbr0_base_hi; /* 0x2040 */
479 u32 fbr0_num_des; /* 0x2044 */
480 u32 fbr0_avail_offset; /* 0x2048 */
481 u32 fbr0_full_offset; /* 0x204C */
482 u32 fbr0_rd_index; /* 0x2050 */
483 u32 fbr0_min_des; /* 0x2054 */
484 u32 fbr1_base_lo; /* 0x2058 */
485 u32 fbr1_base_hi; /* 0x205C */
486 u32 fbr1_num_des; /* 0x2060 */
487 u32 fbr1_avail_offset; /* 0x2064 */
488 u32 fbr1_full_offset; /* 0x2068 */
489 u32 fbr1_rd_index; /* 0x206C */
490 u32 fbr1_min_des; /* 0x2070 */
497 * located at address 0x3000
508 * 0: txmac_en
510 #define ET_TX_CTRL_FC_DISABLE 0x0008
511 #define ET_TX_CTRL_TXMAC_ENABLE 0x0001
514 * located at address 0x3004
518 * 10-0: txq wr ptr
522 * located at address 0x3008
527 * 3-0: fifo_underrun
531 * located at address 0x300C
533 * 11-0: max fill
537 * located at address 0x3010
539 * 15-0: cfpt
543 * located at address 0x3014
548 * 10-0: txq test pointer
552 * located at address 0x3018
562 * 0: seg0_err
566 * located at address 0x301C
576 * 0: seg0_err
580 * located at address 0x3020
584 * 0: bp_xonxoff
590 u32 ctl; /* 0x3000 */
591 u32 shadow_ptr; /* 0x3004 */
592 u32 err_cnt; /* 0x3008 */
593 u32 max_fill; /* 0x300C */
594 u32 cf_param; /* 0x3010 */
595 u32 tx_test; /* 0x3014 */
596 u32 err; /* 0x3018 */
597 u32 err_int; /* 0x301C */
598 u32 bp_ctrl; /* 0x3020 */
606 * located at address 0x4000
615 * 0: rxmac_en
617 #define ET_RX_CTRL_WOL_DISABLE 0x0008
618 #define ET_RX_CTRL_RXMAC_ENABLE 0x0001
620 /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
621 * located at address 0x4004
631 * 4-0: valid_crc 4-0
635 * located at address 0x4008
638 * 15-0: crc1
642 * located at address 0x400C
645 * 15-0: crc3
649 * located at address 0x4010
654 * 7-0: sa6
661 * located at address 0x4014
665 * 7-0: sa2
670 * located at address 0x4018 - 0x4064
675 * located at address 0x4068
680 * 7-0: addr1_6
687 * located at address 0x406C
692 * 7-0: addr2_6
699 * located at address 0x4070
704 * 7-0: addr1_2
711 * located at address 0x4074 - 0x4080
716 * located at address 0x4084
724 * 0: filter_broad_en
727 #define ET_RX_PFCTRL_FRAG_FILTER_ENABLE 0x0008
728 #define ET_RX_PFCTRL_UNICST_FILTER_ENABLE 0x0004
729 #define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE 0x0002
730 #define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE 0x0001
733 * address map. Located at address 0x4088
738 * 0: seg_en
741 #define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE 0x0002
742 #define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE 0x0001
745 * map. Located at address 0x408C
750 * 9-0: mark_lo
754 * located at address 0x4090
759 * 9-0: wr_ptr
763 * located at address 0x4094
768 * 9-0: space_avail
772 * located at address 0x4098
776 * 16-0: drop_pkt_mask
780 * located at address 0x409C
786 * 0: mcif
792 u32 ctrl; /* 0x4000 */
793 u32 crc0; /* 0x4004 */
794 u32 crc12; /* 0x4008 */
795 u32 crc34; /* 0x400C */
796 u32 sa_lo; /* 0x4010 */
797 u32 sa_hi; /* 0x4014 */
798 u32 mask0_word0; /* 0x4018 */
799 u32 mask0_word1; /* 0x401C */
800 u32 mask0_word2; /* 0x4020 */
801 u32 mask0_word3; /* 0x4024 */
802 u32 mask1_word0; /* 0x4028 */
803 u32 mask1_word1; /* 0x402C */
804 u32 mask1_word2; /* 0x4030 */
805 u32 mask1_word3; /* 0x4034 */
806 u32 mask2_word0; /* 0x4038 */
807 u32 mask2_word1; /* 0x403C */
808 u32 mask2_word2; /* 0x4040 */
809 u32 mask2_word3; /* 0x4044 */
810 u32 mask3_word0; /* 0x4048 */
811 u32 mask3_word1; /* 0x404C */
812 u32 mask3_word2; /* 0x4050 */
813 u32 mask3_word3; /* 0x4054 */
814 u32 mask4_word0; /* 0x4058 */
815 u32 mask4_word1; /* 0x405C */
816 u32 mask4_word2; /* 0x4060 */
817 u32 mask4_word3; /* 0x4064 */
818 u32 uni_pf_addr1; /* 0x4068 */
819 u32 uni_pf_addr2; /* 0x406C */
820 u32 uni_pf_addr3; /* 0x4070 */
821 u32 multi_hash1; /* 0x4074 */
822 u32 multi_hash2; /* 0x4078 */
823 u32 multi_hash3; /* 0x407C */
824 u32 multi_hash4; /* 0x4080 */
825 u32 pf_ctrl; /* 0x4084 */
826 u32 mcif_ctrl_max_seg; /* 0x4088 */
827 u32 mcif_water_mark; /* 0x408C */
828 u32 rxq_diag; /* 0x4090 */
829 u32 space_avail; /* 0x4094 */
831 u32 mif_ctrl; /* 0x4098 */
832 u32 err_reg; /* 0x409C */
839 * located at address 0x5000
856 * 0: tx enable
858 #define ET_MAC_CFG1_SOFT_RESET 0x80000000
859 #define ET_MAC_CFG1_SIM_RESET 0x40000000
860 #define ET_MAC_CFG1_RESET_RXMC 0x00080000
861 #define ET_MAC_CFG1_RESET_TXMC 0x00040000
862 #define ET_MAC_CFG1_RESET_RXFUNC 0x00020000
863 #define ET_MAC_CFG1_RESET_TXFUNC 0x00010000
864 #define ET_MAC_CFG1_LOOPBACK 0x00000100
865 #define ET_MAC_CFG1_RX_FLOW 0x00000020
866 #define ET_MAC_CFG1_TX_FLOW 0x00000010
867 #define ET_MAC_CFG1_RX_ENABLE 0x00000004
868 #define ET_MAC_CFG1_TX_ENABLE 0x00000001
869 #define ET_MAC_CFG1_WAIT 0x0000000A /* RX & TX syncd */
872 * located at address 0x5004
883 * 0: full duplex
886 #define ET_MAC_CFG2_IFMODE_MASK 0x0300
887 #define ET_MAC_CFG2_IFMODE_1000 0x0200
888 #define ET_MAC_CFG2_IFMODE_100 0x0100
889 #define ET_MAC_CFG2_IFMODE_HUGE_FRAME 0x0020
890 #define ET_MAC_CFG2_IFMODE_LEN_CHECK 0x0010
891 #define ET_MAC_CFG2_IFMODE_PAD_CRC 0x0004
892 #define ET_MAC_CFG2_IFMODE_CRC_ENABLE 0x0002
893 #define ET_MAC_CFG2_IFMODE_FULL_DPLX 0x0001
896 * located at address 0x5008
903 * 7-0: B2B ipg
906 * located at address 0x500C
915 * 9-0: collision window
919 * located at address 0x5010: bits 0-15 hold the length.
923 * located at address 0x5014 - 0x5018
928 * located at address 0x501C
929 * test: bits 0-2, rest unused
933 * located at address 0x5020
940 * 2-0: mgmt clock reset
942 #define ET_MAC_MIIMGMT_CLK_RST 0x0007
945 * located at address 0x5024
947 * bit 0: read cycle
951 * located at address 0x5028
955 * 4-0: register
960 * located at address 0x502C
962 * 15-0: phy control
966 * located at address 0x5030
968 * 15-0: phy control
970 #define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
973 * located at address 0x5034
977 * 0: busy
979 #define ET_MAC_MGMT_BUSY 0x00000001 /* busy */
980 #define ET_MAC_MGMT_WAIT 0x00000005 /* busy | not valid */
983 * located at address 0x5038
1001 * 0: enable jabber protection
1007 * located at address 0x503C
1019 * 0: pe10t_jabber
1023 * located at address 0x5040
1028 * 7-0: Octet3
1035 * located at address 0x5044
1039 * 15-0: reserved
1047 u32 cfg1; /* 0x5000 */
1048 u32 cfg2; /* 0x5004 */
1049 u32 ipg; /* 0x5008 */
1050 u32 hfdp; /* 0x500C */
1051 u32 max_fm_len; /* 0x5010 */
1052 u32 rsv1; /* 0x5014 */
1053 u32 rsv2; /* 0x5018 */
1054 u32 mac_test; /* 0x501C */
1055 u32 mii_mgmt_cfg; /* 0x5020 */
1056 u32 mii_mgmt_cmd; /* 0x5024 */
1057 u32 mii_mgmt_addr; /* 0x5028 */
1058 u32 mii_mgmt_ctrl; /* 0x502C */
1059 u32 mii_mgmt_stat; /* 0x5030 */
1060 u32 mii_mgmt_indicator; /* 0x5034 */
1061 u32 if_ctrl; /* 0x5038 */
1062 u32 if_stat; /* 0x503C */
1063 u32 station_addr_1; /* 0x5040 */
1064 u32 station_addr_2; /* 0x5044 */
1071 * stat address map address 0x6130 and 0x6138.
1097 * 0: rdrp
1101 * located at address 0x613C
1123 * 0: tdrp
1129 u32 pad[32]; /* 0x6000 - 607C */
1132 u32 txrx_0_64_byte_frames; /* 0x6080 */
1133 u32 txrx_65_127_byte_frames; /* 0x6084 */
1134 u32 txrx_128_255_byte_frames; /* 0x6088 */
1135 u32 txrx_256_511_byte_frames; /* 0x608C */
1136 u32 txrx_512_1023_byte_frames; /* 0x6090 */
1137 u32 txrx_1024_1518_byte_frames; /* 0x6094 */
1138 u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
1139 u32 rx_bytes; /* 0x609C */
1140 u32 rx_packets; /* 0x60A0 */
1141 u32 rx_fcs_errs; /* 0x60A4 */
1142 u32 rx_multicast_packets; /* 0x60A8 */
1143 u32 rx_broadcast_packets; /* 0x60AC */
1144 u32 rx_control_frames; /* 0x60B0 */
1145 u32 rx_pause_frames; /* 0x60B4 */
1146 u32 rx_unknown_opcodes; /* 0x60B8 */
1147 u32 rx_align_errs; /* 0x60BC */
1148 u32 rx_frame_len_errs; /* 0x60C0 */
1149 u32 rx_code_errs; /* 0x60C4 */
1150 u32 rx_carrier_sense_errs; /* 0x60C8 */
1151 u32 rx_undersize_packets; /* 0x60CC */
1152 u32 rx_oversize_packets; /* 0x60D0 */
1153 u32 rx_fragment_packets; /* 0x60D4 */
1154 u32 rx_jabbers; /* 0x60D8 */
1155 u32 rx_drops; /* 0x60DC */
1156 u32 tx_bytes; /* 0x60E0 */
1157 u32 tx_packets; /* 0x60E4 */
1158 u32 tx_multicast_packets; /* 0x60E8 */
1159 u32 tx_broadcast_packets; /* 0x60EC */
1160 u32 tx_pause_frames; /* 0x60F0 */
1161 u32 tx_deferred; /* 0x60F4 */
1162 u32 tx_excessive_deferred; /* 0x60F8 */
1163 u32 tx_single_collisions; /* 0x60FC */
1164 u32 tx_multiple_collisions; /* 0x6100 */
1165 u32 tx_late_collisions; /* 0x6104 */
1166 u32 tx_excessive_collisions; /* 0x6108 */
1167 u32 tx_total_collisions; /* 0x610C */
1168 u32 tx_pause_honored_frames; /* 0x6110 */
1169 u32 tx_drops; /* 0x6114 */
1170 u32 tx_jabbers; /* 0x6118 */
1171 u32 tx_fcs_errs; /* 0x611C */
1172 u32 tx_control_frames; /* 0x6120 */
1173 u32 tx_oversize_frames; /* 0x6124 */
1174 u32 tx_undersize_frames; /* 0x6128 */
1175 u32 tx_fragments; /* 0x612C */
1176 u32 carry_reg1; /* 0x6130 */
1177 u32 carry_reg2; /* 0x6134 */
1178 u32 carry_reg1_mask; /* 0x6138 */
1179 u32 carry_reg2_mask; /* 0x613C */
1186 * located at address 0x7000
1197 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1204 * address map. Located at address 0x7008 - 0x7014
1211 u32 mmc_ctrl; /* 0x7000 */
1212 u32 sram_access; /* 0x7004 */
1213 u32 sram_word1; /* 0x7008 */
1214 u32 sram_word2; /* 0x700C */
1215 u32 sram_word3; /* 0x7010 */
1216 u32 sram_word4; /* 0x7014 */
1254 /* Defines for generic MII registers 0x00 -> 0x0F can be found in
1258 #define PHY_INDEX_REG 0x10
1259 #define PHY_DATA_REG 0x11
1260 #define PHY_MPHY_CONTROL_REG 0x12
1263 #define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
1265 #define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
1266 #define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
1267 #define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
1268 #define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
1269 #define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
1270 #define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
1271 #define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
1272 #define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
1276 /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
1277 #define ET_1000BT_MSTR_SLV 0x4000
1279 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
1281 /* MI Register 19: Loopback Control Reg(0x13)
1288 * 9-0: reserved
1291 /* MI Register 20: Reserved Reg(0x14) */
1293 /* MI Register 21: Management Interface Control Reg(0x15)
1299 * 0: preamble_suppress_en
1302 /* MI Register 22: PHY Configuration Reg(0x16)
1314 * 2-0: mac_if_mode
1316 #define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
1318 #define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
1319 #define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
1320 #define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
1321 #define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
1323 /* MI Register 23: PHY CONTROL Reg(0x17)
1334 * 0: force_int
1337 /* MI Register 24: Interrupt Mask Reg(0x18)
1348 * 0: int_en
1351 /* MI Register 25: Interrupt Status Reg(0x19)
1362 * 0: int_en
1365 /* MI Register 26: PHY Status Reg(0x1A)
1379 * 0: asymmetric_dir
1381 #define ET_PHY_AUTONEG_STATUS 0x1000
1382 #define ET_PHY_POLARITY_STATUS 0x0400
1383 #define ET_PHY_SPEED_STATUS 0x0300
1384 #define ET_PHY_DUPLEX_STATUS 0x0080
1385 #define ET_PHY_LSTATUS 0x0040
1386 #define ET_PHY_AUTONEG_ENABLE 0x0020
1388 /* MI Register 27: LED Control Reg 1(0x1B)
1396 * 0: pulse_stretch0
1399 /* MI Register 28: LED Control Reg 2(0x1C)
1403 * 3-0: led_1000BaseT
1405 #define ET_LED2_LED_LINK 0xF000
1406 #define ET_LED2_LED_TXRX 0x0F00
1407 #define ET_LED2_LED_100TX 0x00F0
1408 #define ET_LED2_LED_1000T 0x000F
1411 #define LED_VAL_1000BT 0x0
1412 #define LED_VAL_100BTX 0x1
1413 #define LED_VAL_10BT 0x2
1414 #define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
1415 #define LED_VAL_LINKON 0x4
1416 #define LED_VAL_TX 0x5
1417 #define LED_VAL_RX 0x6
1418 #define LED_VAL_TXRX 0x7 /* TX or RX */
1419 #define LED_VAL_DUPLEXFULL 0x8
1420 #define LED_VAL_COLLISION 0x9
1421 #define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
1422 #define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
1423 #define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
1424 #define LED_VAL_BLINK 0xD
1425 #define LED_VAL_ON 0xE
1426 #define LED_VAL_OFF 0xF
1432 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */