Lines Matching +full:wr +full:- +full:active
1 /* SPDX-License-Identifier: GPL-1.0+ */
6 * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
21 /* The 8390 specific per-packet-header format. */
34 /* Without I/O delay - non ISA or later chips */
70 /* You have one of these per-board */
85 unsigned word16:1; /* We have the 16-bit (vs 8-bit)
88 unsigned bigendian:1; /* 16-bit big endian mode. Do NOT
91 unsigned txing:1; /* Transmit Active */
93 unsigned dmaing:1; /* Remote DMA Active */
98 short tx1, tx2; /* Packet lengths for ping-pong tx. */
102 unsigned char saved_irq; /* Original dev->irq value. */
148 #define E8390_PAGE1 0x40 /* using the two high-order bits */
152 * - removed AMIGA_PCMCIA from this list, handled as ISA io now
153 * - the _p for generates no delay by default 8390p.c overrides this.
170 #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
172 #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
173 #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
175 #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
177 #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
179 #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
180 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
185 #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
186 #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
188 #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
189 #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
191 #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
193 #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
196 /* Bits in EN0_ISR - Interrupt status register */
207 /* Bits in EN0_DCFG - Data config register */
212 #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
214 #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
215 #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
236 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */