Lines Matching +full:page +full:- +full:mode +full:- +full:read +full:- +full:delay

1 /* SPDX-License-Identifier: GPL-1.0+ */
6  * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
21 /* The 8390 specific per-packet-header format. */
34 /* Without I/O delay - non ISA or later chips */
52 /* With I/O delay form */
70 /* You have one of these per-board */
85 	unsigned word16:1;		/* We have the 16-bit (vs 8-bit)
88 	unsigned bigendian:1;		/* 16-bit big endian mode. Do NOT
95 	unsigned char current_page;	/* Read pointer in buffer  */
98 	short tx1, tx2;			/* Packet lengths for ping-pong tx. */
102 	unsigned char saved_irq;	/* Original dev->irq value. */
104 	spinlock_t page_lock;		/* Page register locks */
134 /* EN0_TXCR: Normal transmit mode */
144 #define E8390_RREAD	0x08	/* Remote read */
147 #define E8390_PAGE0	0x00	/* Select page chip registers */
148 #define E8390_PAGE1	0x40	/* using the two high-order bits */
149 #define E8390_PAGE2	0x80	/* Page 3 is invalid. */
152  * - removed AMIGA_PCMCIA from this list, handled as ISA io now
153  * - the _p for generates no delay by default 8390p.c overrides this.
168 /* Page 0 register offsets. */
170 #define EN0_STARTPG	EI_SHIFT(0x01)	/* Starting page of ring bfr WR */
172 #define EN0_STOPPG	EI_SHIFT(0x02)	/* Ending page +1 of ring bfr WR */
173 #define EN0_BOUNDARY	EI_SHIFT(0x03)	/* Boundary page of ring bfr RD WR */
175 #define EN0_TPSR	EI_SHIFT(0x04)	/* Transmit starting page WR */
196 /* Bits in EN0_ISR - Interrupt status register */
207 /* Bits in EN0_DCFG - Data config register */
208 #define ENDCFG_WTS	0x01	/* word transfer mode selection */
211 /* Page 1 register offsets. */
214 #define EN1_CURPAG EI_SHIFT(0x07)	/* Current memory page RD WR */
225 #define ENRSR_DIS	0x40	/* receiver disable. set in monitor mode */
236 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */