21 	memset(buf, 0, size);  in sja1105_spi_message_pack()
38 	u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0};  in sja1105_xfer()
40 	struct spi_transfer xfers[2] = {0};  in sja1105_xfer()
45 	int rc, i = 0;  in sja1105_xfer()
53 	hdr_xfer = &xfers[0];  in sja1105_xfer()
56 	for (i = 0; i < num_chunks; i++) {  in sja1105_xfer()
67 			msg.read_count = 0;  in sja1105_xfer()
106 		if (rc < 0) {  in sja1105_xfer()
112 	return 0;  in sja1105_xfer()
139 		sja1105_pack(packed_buf, value, 63, 0, 8);  in sja1105_xfer_u64()
144 		sja1105_unpack(packed_buf, value, 63, 0, 8);  in sja1105_xfer_u64()
163 		sja1105_pack(packed_buf, &tmp, 31, 0, 4);  in sja1105_xfer_u32()
169 		sja1105_unpack(packed_buf, &tmp, 31, 0, 4);  in sja1105_xfer_u32()
219 	if (rc < 0)  in sja1105_inhibit_tx()
250 	 * the register pointer, and never access p[0].  in sja1105_status_unpack()
253 	sja1105_unpack(p + 0x1, &status->configs,   31, 31, 4);  in sja1105_status_unpack()
254 	sja1105_unpack(p + 0x1, &status->crcchkl,   30, 30, 4);  in sja1105_status_unpack()
255 	sja1105_unpack(p + 0x1, &status->ids,       29, 29, 4);  in sja1105_status_unpack()
256 	sja1105_unpack(p + 0x1, &status->crcchkg,   28, 28, 4);  in sja1105_status_unpack()
267 	if (rc < 0)  in sja1105_status_get()
272 	return 0;  in sja1105_status_get()
298 	/* Recalculate CRC of the last header (right now 0xDEADBEEF).  in static_config_buf_prepare_for_upload()
310 	return 0;  in static_config_buf_prepare_for_upload()
332 	if (rc < 0) {  in sja1105_static_config_upload()
341 	rc = sja1105_inhibit_tx(priv, GENMASK_ULL(ds->num_ports - 1, 0), true);  in sja1105_static_config_upload()
342 	if (rc < 0) {  in sja1105_static_config_upload()
355 		if (rc < 0) {  in sja1105_static_config_upload()
364 		if (rc < 0) {  in sja1105_static_config_upload()
370 		if (rc < 0)  in sja1105_static_config_upload()
375 				"device id. Wrote 0x%llx, wants 0x%llx\n",  in sja1105_static_config_upload()
389 		if (status.configs == 0) {  in sja1105_static_config_upload()
412 	.device_id = 0x0,
413 	.prod_id = 0x100BC3,
414 	.status = 0x1,
415 	.port_control = 0x11,
416 	.vl_status = 0x10000,
417 	.config = 0x020000,
418 	.rgu = 0x100440,
420 	.pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
421 	.pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
422 	.rmii_pll1 = 0x10000A,
423 	.cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
424 	.stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
425 	.stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
426 	.stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
428 	.mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F},
429 	.mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030},
430 	.mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
431 	.mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035},
432 	.rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032},
433 	.rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031},
434 	.rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
435 	.ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8},
436 	.ptpschtm = 0x12, /* Spans 0x12 to 0x13 */
437 	.ptppinst = 0x14,
438 	.ptppindur = 0x16,
439 	.ptp_control = 0x17,
440 	.ptpclkval = 0x18, /* Spans 0x18 to 0x19 */
441 	.ptpclkrate = 0x1A,
442 	.ptpclkcorp = 0x1D,
448 	.device_id = 0x0,
449 	.prod_id = 0x100BC3,
450 	.status = 0x1,
451 	.port_control = 0x12,
452 	.vl_status = 0x10000,
453 	.config = 0x020000,
454 	.rgu = 0x100440,
456 	.pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
457 	.pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
458 	.pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814},
459 	.rmii_pll1 = 0x10000A,
460 	.cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
461 	.stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
462 	.stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
463 	.stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
464 	.stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460},
466 	.mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B},
467 	.mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C},
468 	.mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
469 	.mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030},
470 	.rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E},
471 	.rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D},
472 	.rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
473 	.ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0},
474 	.ptpschtm = 0x13, /* Spans 0x13 to 0x14 */
475 	.ptppinst = 0x15,
476 	.ptppindur = 0x17,
477 	.ptp_control = 0x18,
478 	.ptpclkval = 0x19,
479 	.ptpclkrate = 0x1B,
480 	.ptpclkcorp = 0x1E,
481 	.ptpsyncts = 0x1F,
487 	.device_id = SJA1110_SPI_ADDR(0x0),
488 	.prod_id = SJA1110_ACU_ADDR(0xf00),
489 	.status = SJA1110_SPI_ADDR(0x4),
490 	.port_control = SJA1110_SPI_ADDR(0x50), /* actually INHIB_TX */
491 	.vl_status = 0x10000,
492 	.config = 0x020000,
493 	.rgu = SJA1110_RGU_ADDR(0x100), /* Reset Control Register 0 */
510 		       SJA1110_ACU_ADDR(0x18), SJA1110_ACU_ADDR(0x28),
520 	.stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208, 0x20a,
521 		       0x20c, 0x20e, 0x210, 0x212, 0x214},
522 	.stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440, 0x450,
523 		       0x460, 0x470, 0x480, 0x490, 0x4a0},
524 	.stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640, 0x650,
525 		       0x660, 0x670, 0x680, 0x690, 0x6a0},
526 	.stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460, 0x1478,
527 			 0x1490, 0x14a8, 0x14c0, 0x14d8, 0x14f0},
558 	.ptpschtm = SJA1110_SPI_ADDR(0x54),
559 	.ptppinst = SJA1110_SPI_ADDR(0x5c),
560 	.ptppindur = SJA1110_SPI_ADDR(0x64),
561 	.ptp_control = SJA1110_SPI_ADDR(0x68),
562 	.ptpclkval = SJA1110_SPI_ADDR(0x6c),
563 	.ptpclkrate = SJA1110_SPI_ADDR(0x74),
564 	.ptpclkcorp = SJA1110_SPI_ADDR(0x80),
565 	.ptpsyncts = SJA1110_SPI_ADDR(0x84),
566 	.mdio_100base_tx = 0x1c2400,
567 	.mdio_100base_t1 = 0x1c1000,
568 	.pcs_base = {SJA1105_RSV_ADDR, 0x1c1400, 0x1c1800, 0x1c1c00, 0x1c2000,
593 		[SJA1105_SPEED_AUTO] = 0,
597 		[SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
625 		[SJA1105_SPEED_AUTO] = 0,
629 		[SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
658 		[SJA1105_SPEED_AUTO] = 0,
662 		[SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
691 		[SJA1105_SPEED_AUTO] = 0,
695 		[SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
726 		[SJA1105_SPEED_AUTO] = 0,
730 		[SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
762 		[SJA1105_SPEED_AUTO] = 0,
766 		[SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
801 		[SJA1105_SPEED_AUTO] = 0,
852 		[SJA1105_SPEED_AUTO] = 0,
903 		[SJA1105_SPEED_AUTO] = 0,
954 		[SJA1105_SPEED_AUTO] = 0,