Lines Matching +full:disable +full:- +full:hi +full:- +full:speed
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022 Schneider-Electric
73 writel(value, a5psw->base + offset); in a5psw_reg_writel()
78 return readl(a5psw->base + offset); in a5psw_reg_readl()
85 spin_lock(&a5psw->reg_lock); in a5psw_reg_rmw()
92 spin_unlock(&a5psw->reg_lock); in a5psw_reg_rmw()
156 ret = readl_poll_timeout(a5psw->base + A5PSW_LK_ADDR_CTRL, *ctrl, in a5psw_lk_execute_ctrl()
160 dev_err(a5psw->dev, "LK_CTRL timeout waiting for BUSY bit\n"); in a5psw_lk_execute_ctrl()
169 mutex_lock(&a5psw->lk_lock); in a5psw_port_fdb_flush()
171 mutex_unlock(&a5psw->lk_lock); in a5psw_port_fdb_flush()
189 struct a5psw *a5psw = ds->priv; in a5psw_port_disable()
198 struct a5psw *a5psw = ds->priv; in a5psw_port_enable()
208 struct a5psw *a5psw = ds->priv; in a5psw_port_change_mtu()
224 unsigned long *intf = config->supported_interfaces; in a5psw_phylink_get_caps()
226 config->mac_capabilities = MAC_1000FD; in a5psw_phylink_get_caps()
230 * using 1000Mbps Full-Duplex mode only (cf ethernet manual) in a5psw_phylink_get_caps()
234 config->mac_capabilities |= MAC_100 | MAC_10; in a5psw_phylink_get_caps()
246 struct a5psw *a5psw = dp->ds->priv; in a5psw_phylink_mac_select_pcs()
251 return a5psw->pcs[dp->index]; in a5psw_phylink_mac_select_pcs()
265 struct a5psw *a5psw = dp->ds->priv; in a5psw_phylink_mac_link_down()
266 int port = dp->index; in a5psw_phylink_mac_link_down()
278 int speed, int duplex, bool tx_pause, in a5psw_phylink_mac_link_up() argument
284 struct a5psw *a5psw = dp->ds->priv; in a5psw_phylink_mac_link_up()
286 if (speed == SPEED_1000) in a5psw_phylink_mac_link_up()
297 a5psw_reg_writel(a5psw, A5PSW_CMD_CFG(dp->index), cmd_cfg); in a5psw_phylink_mac_link_up()
302 struct a5psw *a5psw = ds->priv; in a5psw_set_ageing_time()
307 rate = clk_get_rate(a5psw->clk); in a5psw_set_ageing_time()
311 return -EINVAL; in a5psw_set_ageing_time()
363 struct a5psw *a5psw = ds->priv; in a5psw_port_bridge_join()
366 if (a5psw->br_dev && bridge.dev != a5psw->br_dev) { in a5psw_port_bridge_join()
369 return -EOPNOTSUPP; in a5psw_port_bridge_join()
372 a5psw->br_dev = bridge.dev; in a5psw_port_bridge_join()
375 a5psw->bridged_ports |= BIT(port); in a5psw_port_bridge_join()
383 struct a5psw *a5psw = ds->priv; in a5psw_port_bridge_leave()
385 a5psw->bridged_ports &= ~BIT(port); in a5psw_port_bridge_leave()
390 if (a5psw->bridged_ports == BIT(A5PSW_CPU_PORT)) in a5psw_port_bridge_leave()
391 a5psw->br_dev = NULL; in a5psw_port_bridge_leave()
400 return -EINVAL; in a5psw_port_pre_bridge_flags()
410 struct a5psw *a5psw = ds->priv; in a5psw_port_bridge_flags()
417 * standalone port (ie enable flooding, disable learning). In that case in a5psw_port_bridge_flags()
420 if (!(a5psw->bridged_ports & BIT(port))) in a5psw_port_bridge_flags()
451 struct a5psw *a5psw = ds->priv; in a5psw_port_stp_state_set()
464 learning_enabled = dp->learning; in a5psw_port_stp_state_set()
469 learning_enabled = dp->learning; in a5psw_port_stp_state_set()
472 dev_err(ds->dev, "invalid STP state: %d\n", state); in a5psw_port_stp_state_set()
483 struct a5psw *a5psw = ds->priv; in a5psw_port_fast_age()
494 a5psw_reg_writel(a5psw, A5PSW_LK_DATA_LO, lk_data->lo); in a5psw_lk_execute_lookup()
495 a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data->hi); in a5psw_lk_execute_lookup()
511 struct a5psw *a5psw = ds->priv; in a5psw_port_fdb_add()
521 mutex_lock(&a5psw->lk_lock); in a5psw_port_fdb_add()
528 lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI); in a5psw_port_fdb_add()
540 a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data.hi); in a5psw_port_fdb_add()
553 mutex_unlock(&a5psw->lk_lock); in a5psw_port_fdb_add()
562 struct a5psw *a5psw = ds->priv; in a5psw_port_fdb_del()
571 mutex_lock(&a5psw->lk_lock); in a5psw_port_fdb_del()
577 lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI); in a5psw_port_fdb_del()
593 a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data.hi); in a5psw_port_fdb_del()
612 mutex_unlock(&a5psw->lk_lock); in a5psw_port_fdb_del()
620 struct a5psw *a5psw = ds->priv; in a5psw_port_fdb_dump()
625 mutex_lock(&a5psw->lk_lock); in a5psw_port_fdb_dump()
634 lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI); in a5psw_port_fdb_dump()
648 mutex_unlock(&a5psw->lk_lock); in a5psw_port_fdb_dump()
660 struct a5psw *a5psw = ds->priv; in a5psw_port_vlan_filtering()
662 /* Disable/enable vlan tagging */ in a5psw_port_vlan_filtering()
666 /* Disable/enable vlan input filtering */ in a5psw_port_vlan_filtering()
684 return -1; in a5psw_find_vlan_entry()
702 return -1; in a5psw_new_vlan_res_entry()
743 bool tagged = !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); in a5psw_port_vlan_add()
744 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in a5psw_port_vlan_add()
745 struct a5psw *a5psw = ds->priv; in a5psw_port_vlan_add()
746 u16 vid = vlan->vid; in a5psw_port_vlan_add()
753 return -ENOSPC; in a5psw_port_vlan_add()
773 struct a5psw *a5psw = ds->priv; in a5psw_port_vlan_del()
774 u16 vid = vlan->vid; in a5psw_port_vlan_del()
779 return -EINVAL; in a5psw_port_vlan_del()
813 struct a5psw *a5psw = ds->priv; in a5psw_get_ethtool_stats()
831 struct a5psw *a5psw = ds->priv; in a5psw_get_eth_mac_stats()
834 mac_stats->FramesTransmittedOK = RD(aFramesTransmittedOK); in a5psw_get_eth_mac_stats()
835 mac_stats->SingleCollisionFrames = RD(aSingleCollisions); in a5psw_get_eth_mac_stats()
836 mac_stats->MultipleCollisionFrames = RD(aMultipleCollisions); in a5psw_get_eth_mac_stats()
837 mac_stats->FramesReceivedOK = RD(aFramesReceivedOK); in a5psw_get_eth_mac_stats()
838 mac_stats->FrameCheckSequenceErrors = RD(aFrameCheckSequenceErrors); in a5psw_get_eth_mac_stats()
839 mac_stats->AlignmentErrors = RD(aAlignmentErrors); in a5psw_get_eth_mac_stats()
840 mac_stats->OctetsTransmittedOK = RD(aOctetsTransmittedOK); in a5psw_get_eth_mac_stats()
841 mac_stats->FramesWithDeferredXmissions = RD(aDeferred); in a5psw_get_eth_mac_stats()
842 mac_stats->LateCollisions = RD(aLateCollisions); in a5psw_get_eth_mac_stats()
843 mac_stats->FramesAbortedDueToXSColls = RD(aExcessiveCollisions); in a5psw_get_eth_mac_stats()
844 mac_stats->FramesLostDueToIntMACXmitError = RD(ifOutErrors); in a5psw_get_eth_mac_stats()
845 mac_stats->CarrierSenseErrors = RD(aCarrierSenseErrors); in a5psw_get_eth_mac_stats()
846 mac_stats->OctetsReceivedOK = RD(aOctetsReceivedOK); in a5psw_get_eth_mac_stats()
847 mac_stats->FramesLostDueToIntMACRcvError = RD(ifInErrors); in a5psw_get_eth_mac_stats()
848 mac_stats->MulticastFramesXmittedOK = RD(ifOutMulticastPkts); in a5psw_get_eth_mac_stats()
849 mac_stats->BroadcastFramesXmittedOK = RD(ifOutBroadcastPkts); in a5psw_get_eth_mac_stats()
850 mac_stats->FramesWithExcessiveDeferral = RD(aDeferred); in a5psw_get_eth_mac_stats()
851 mac_stats->MulticastFramesReceivedOK = RD(ifInMulticastPkts); in a5psw_get_eth_mac_stats()
852 mac_stats->BroadcastFramesReceivedOK = RD(ifInBroadcastPkts); in a5psw_get_eth_mac_stats()
871 struct a5psw *a5psw = ds->priv; in a5psw_get_rmon_stats()
874 rmon_stats->undersize_pkts = RD(etherStatsUndersizePkts); in a5psw_get_rmon_stats()
875 rmon_stats->oversize_pkts = RD(etherStatsOversizePkts); in a5psw_get_rmon_stats()
876 rmon_stats->fragments = RD(etherStatsFragments); in a5psw_get_rmon_stats()
877 rmon_stats->jabbers = RD(etherStatsJabbers); in a5psw_get_rmon_stats()
878 rmon_stats->hist[0] = RD(etherStatsPkts64Octets); in a5psw_get_rmon_stats()
879 rmon_stats->hist[1] = RD(etherStatsPkts65to127Octets); in a5psw_get_rmon_stats()
880 rmon_stats->hist[2] = RD(etherStatsPkts128to255Octets); in a5psw_get_rmon_stats()
881 rmon_stats->hist[3] = RD(etherStatsPkts256to511Octets); in a5psw_get_rmon_stats()
882 rmon_stats->hist[4] = RD(etherStatsPkts512to1023Octets); in a5psw_get_rmon_stats()
883 rmon_stats->hist[5] = RD(etherStatsPkts1024to1518Octets); in a5psw_get_rmon_stats()
884 rmon_stats->hist[6] = RD(etherStatsPkts1519toXOctets); in a5psw_get_rmon_stats()
893 struct a5psw *a5psw = ds->priv; in a5psw_get_eth_ctrl_stats()
897 ctrl_stats->MACControlFramesTransmitted = stat; in a5psw_get_eth_ctrl_stats()
899 ctrl_stats->MACControlFramesReceived = stat; in a5psw_get_eth_ctrl_stats()
925 struct a5psw *a5psw = ds->priv; in a5psw_setup()
932 if (dp->index != A5PSW_CPU_PORT) { in a5psw_setup()
933 dev_err(a5psw->dev, "Invalid CPU port\n"); in a5psw_setup()
934 return -EINVAL; in a5psw_setup()
957 ret = readl_poll_timeout(a5psw->base + A5PSW_LK_CTRL, reg, in a5psw_setup()
961 dev_err(a5psw->dev, "Failed to clear lookup table\n"); in a5psw_setup()
976 port = dp->index; in a5psw_setup()
1045 err = readl_poll_timeout(a5psw->base + A5PSW_MDIO_CFG_STATUS, status, in a5psw_mdio_wait_busy()
1049 dev_err(a5psw->dev, "MDIO command timeout\n"); in a5psw_mdio_wait_busy()
1056 struct a5psw *a5psw = bus->priv; in a5psw_mdio_read()
1074 return -EIO; in a5psw_mdio_read()
1082 struct a5psw *a5psw = bus->priv; in a5psw_mdio_write()
1100 rate = clk_get_rate(a5psw->hclk); in a5psw_mdio_config()
1104 dev_err(a5psw->dev, "MDIO clock div %ld out of range\n", div); in a5psw_mdio_config()
1105 return -ERANGE; in a5psw_mdio_config()
1117 struct device *dev = a5psw->dev; in a5psw_probe_mdio()
1122 if (of_property_read_u32(node, "clock-frequency", &mdio_freq)) in a5psw_probe_mdio()
1131 return -ENOMEM; in a5psw_probe_mdio()
1133 bus->name = "a5psw_mdio"; in a5psw_probe_mdio()
1134 bus->read = a5psw_mdio_read; in a5psw_probe_mdio()
1135 bus->write = a5psw_mdio_write; in a5psw_probe_mdio()
1136 bus->priv = a5psw; in a5psw_probe_mdio()
1137 bus->parent = dev; in a5psw_probe_mdio()
1138 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); in a5psw_probe_mdio()
1140 a5psw->mii_bus = bus; in a5psw_probe_mdio()
1149 for (i = 0; i < ARRAY_SIZE(a5psw->pcs); i++) { in a5psw_pcs_free()
1150 if (a5psw->pcs[i]) in a5psw_pcs_free()
1151 miic_destroy(a5psw->pcs[i]); in a5psw_pcs_free()
1162 ports = of_get_child_by_name(a5psw->dev->of_node, "ethernet-ports"); in a5psw_pcs_get()
1164 return -EINVAL; in a5psw_pcs_get()
1167 pcs_node = of_parse_phandle(port, "pcs-handle", 0); in a5psw_pcs_get()
1172 ret = -EINVAL; in a5psw_pcs_get()
1176 if (reg >= ARRAY_SIZE(a5psw->pcs)) { in a5psw_pcs_get()
1177 ret = -ENODEV; in a5psw_pcs_get()
1181 pcs = miic_create(a5psw->dev, pcs_node); in a5psw_pcs_get()
1183 dev_err(a5psw->dev, "Failed to create PCS for port %d\n", in a5psw_pcs_get()
1189 a5psw->pcs[reg] = pcs; in a5psw_pcs_get()
1207 struct device *dev = &pdev->dev; in a5psw_probe()
1215 return -ENOMEM; in a5psw_probe()
1217 a5psw->dev = dev; in a5psw_probe()
1218 mutex_init(&a5psw->lk_lock); in a5psw_probe()
1219 spin_lock_init(&a5psw->reg_lock); in a5psw_probe()
1220 a5psw->base = devm_platform_ioremap_resource(pdev, 0); in a5psw_probe()
1221 if (IS_ERR(a5psw->base)) in a5psw_probe()
1222 return PTR_ERR(a5psw->base); in a5psw_probe()
1224 a5psw->bridged_ports = BIT(A5PSW_CPU_PORT); in a5psw_probe()
1230 a5psw->hclk = devm_clk_get_enabled(dev, "hclk"); in a5psw_probe()
1231 if (IS_ERR(a5psw->hclk)) { in a5psw_probe()
1233 ret = PTR_ERR(a5psw->hclk); in a5psw_probe()
1237 a5psw->clk = devm_clk_get_enabled(dev, "clk"); in a5psw_probe()
1238 if (IS_ERR(a5psw->clk)) { in a5psw_probe()
1240 ret = PTR_ERR(a5psw->clk); in a5psw_probe()
1244 mdio = of_get_available_child_by_name(dev->of_node, "mdio"); in a5psw_probe()
1254 ds = &a5psw->ds; in a5psw_probe()
1255 ds->dev = dev; in a5psw_probe()
1256 ds->num_ports = A5PSW_PORTS_NUM; in a5psw_probe()
1257 ds->ops = &a5psw_switch_ops; in a5psw_probe()
1258 ds->phylink_mac_ops = &a5psw_phylink_mac_ops; in a5psw_probe()
1259 ds->priv = a5psw; in a5psw_probe()
1282 dsa_unregister_switch(&a5psw->ds); in a5psw_remove()
1293 dsa_switch_shutdown(&a5psw->ds); in a5psw_shutdown()
1299 { .compatible = "renesas,rzn1-a5psw", },
1316 MODULE_DESCRIPTION("Renesas RZ/N1 Advanced 5-port Switch driver");