Lines Matching +full:1 +full:mb
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
23 * | interface 1 GMAC 1 |
35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the
111 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
133 #define RTL8365MB_INTR_POLARITY_LOW 1
175 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1
177 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1
197 #define RTL8365MB_EXT_PORT_MODE_RGMII 1
211 /* External interface mode configuration registers 0~1 */
215 ((_extint) <= 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \
229 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \
237 #define RTL8365MB_PORT_SPEED_100M 1
246 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \
290 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3))
291 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1)
476 RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1),
487 * @id: the external interface ID, which is either 0, 1, or 2
529 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
540 { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) },
552 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
564 RTL8365MB_STP_STATE_BLOCKING = 1,
571 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1,
577 RTL8365MB_CPU_POS_BEFORE_CRC = 1,
582 RTL8365MB_CPU_FORMAT_4BYTES = 1,
587 RTL8365MB_CPU_RXLEN_64BYTES = 1,
678 ocp_addr >> 1);
834 struct rtl8365mb *mb = priv->chip_data;
839 &mb->chip_info->extints[i];
857 struct rtl8365mb *mb;
859 mb = priv->chip_data;
860 cpu = &mb->cpu;
893 * 0 = no delay, 1 = 2 ns delay
969 r_link = 1;
970 r_rx_pause = rx_pause ? 1 : 0;
971 r_tx_pause = tx_pause ? 1 : 0;
986 r_duplex = 1;
1003 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) |
1088 struct rtl8365mb *mb;
1092 mb = priv->chip_data;
1093 p = &mb->ports[port];
1118 struct rtl8365mb *mb;
1122 mb = priv->chip_data;
1123 p = &mb->ports[port];
1253 offset = (offset + 1) % 4;
1274 struct rtl8365mb *mb;
1278 mb = priv->chip_data;
1280 mutex_lock(&mb->mib_lock);
1293 mutex_unlock(&mb->mib_lock);
1322 struct rtl8365mb *mb;
1324 mb = priv->chip_data;
1327 mutex_lock(&mb->mib_lock);
1330 mutex_unlock(&mb->mib_lock);
1337 [RTL8365MB_MIB_ifOutOctets] = 1,
1338 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1339 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1340 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1341 [RTL8365MB_MIB_dot3OutPauseFrames] = 1,
1342 [RTL8365MB_MIB_ifOutDiscards] = 1,
1343 [RTL8365MB_MIB_ifInOctets] = 1,
1344 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1345 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1346 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1347 [RTL8365MB_MIB_dot3InPauseFrames] = 1,
1348 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1,
1349 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1,
1350 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1351 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1,
1352 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1353 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1,
1357 struct rtl8365mb *mb;
1361 mb = priv->chip_data;
1363 mutex_lock(&mb->mib_lock);
1367 /* Only fetch required MIB counters (marked = 1 above) */
1376 mutex_unlock(&mb->mib_lock);
1423 struct rtl8365mb *mb;
1425 mb = priv->chip_data;
1428 mutex_lock(&mb->mib_lock);
1431 mutex_unlock(&mb->mib_lock);
1437 [RTL8365MB_MIB_ifOutOctets] = 1,
1438 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1439 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1440 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1441 [RTL8365MB_MIB_ifOutDiscards] = 1,
1442 [RTL8365MB_MIB_ifInOctets] = 1,
1443 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1444 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1445 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1446 [RTL8365MB_MIB_etherStatsDropEvents] = 1,
1447 [RTL8365MB_MIB_etherStatsCollisions] = 1,
1448 [RTL8365MB_MIB_etherStatsFragments] = 1,
1449 [RTL8365MB_MIB_etherStatsJabbers] = 1,
1450 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1451 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1453 struct rtl8365mb *mb = priv->chip_data;
1458 stats = &mb->ports[port].stats;
1460 mutex_lock(&mb->mib_lock);
1464 /* Only fetch required MIB counters (marked = 1 above) */
1473 mutex_unlock(&mb->mib_lock);
1479 spin_lock(&mb->ports[port].stats_lock);
1510 spin_unlock(&mb->ports[port].stats_lock);
1530 struct rtl8365mb *mb;
1532 mb = priv->chip_data;
1533 p = &mb->ports[port];
1542 struct rtl8365mb *mb = priv->chip_data;
1549 mutex_init(&mb->mib_lock);
1552 struct rtl8365mb_port *p = &mb->ports[i];
1569 struct rtl8365mb *mb = priv->chip_data;
1574 struct rtl8365mb_port *p = &mb->ports[i];
1658 irq_set_nested_thread(irq, 1);
1682 enable ? 1 : 0));
1697 struct rtl8365mb *mb = priv->chip_data;
1785 mb->irq = irq;
1796 free_irq(mb->irq, priv);
1797 mb->irq = 0;
1816 struct rtl8365mb *mb = priv->chip_data;
1820 if (mb->irq) {
1821 free_irq(mb->irq, priv);
1822 mb->irq = 0;
1838 struct rtl8365mb *mb = priv->chip_data;
1839 struct rtl8365mb_cpu *cpu = &mb->cpu;
1850 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |
1870 struct rtl8365mb *mb;
1872 mb = priv->chip_data;
1873 cpu = &mb->cpu;
1898 struct rtl8365mb *mb = priv->chip_data;
1903 ci = mb->chip_info;
1931 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1));
1933 /* Realtek documentation says the chip needs 1 second to reset. Sleep
1939 20000, 1e6);
1947 struct rtl8365mb *mb;
1951 mb = priv->chip_data;
1952 cpu = &mb->cpu;
1988 struct rtl8365mb_port *p = &mb->ports[i];
2073 struct rtl8365mb *mb = priv->chip_data;
2090 mb->chip_info = ci;
2095 if (!mb->chip_info) {
2102 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name);
2105 mb->priv = priv;
2106 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;
2107 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
2108 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
2109 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
2110 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;