31 #define VSC9959_IMDIO_PCI_BAR		0
49 	REG(ANA_ADVLEARN,			0x0089a0),
50 	REG(ANA_VLANMASK,			0x0089a4),
52 	REG(ANA_ANAGEFIL,			0x0089ac),
53 	REG(ANA_ANEVENTS,			0x0089b0),
54 	REG(ANA_STORMLIMIT_BURST,		0x0089b4),
55 	REG(ANA_STORMLIMIT_CFG,			0x0089b8),
56 	REG(ANA_ISOLATED_PORTS,			0x0089c8),
57 	REG(ANA_COMMUNITY_PORTS,		0x0089cc),
58 	REG(ANA_AUTOAGE,			0x0089d0),
59 	REG(ANA_MACTOPTIONS,			0x0089d4),
60 	REG(ANA_LEARNDISC,			0x0089d8),
61 	REG(ANA_AGENCTRL,			0x0089dc),
62 	REG(ANA_MIRRORPORTS,			0x0089e0),
63 	REG(ANA_EMIRRORPORTS,			0x0089e4),
64 	REG(ANA_FLOODING,			0x0089e8),
65 	REG(ANA_FLOODING_IPMC,			0x008a08),
66 	REG(ANA_SFLOW_CFG,			0x008a0c),
67 	REG(ANA_PORT_MODE,			0x008a28),
68 	REG(ANA_CUT_THRU_CFG,			0x008a48),
69 	REG(ANA_PGID_PGID,			0x008400),
70 	REG(ANA_TABLES_ANMOVED,			0x007f1c),
71 	REG(ANA_TABLES_MACHDATA,		0x007f20),
72 	REG(ANA_TABLES_MACLDATA,		0x007f24),
73 	REG(ANA_TABLES_STREAMDATA,		0x007f28),
74 	REG(ANA_TABLES_MACACCESS,		0x007f2c),
75 	REG(ANA_TABLES_MACTINDX,		0x007f30),
76 	REG(ANA_TABLES_VLANACCESS,		0x007f34),
77 	REG(ANA_TABLES_VLANTIDX,		0x007f38),
78 	REG(ANA_TABLES_ISDXACCESS,		0x007f3c),
79 	REG(ANA_TABLES_ISDXTIDX,		0x007f40),
80 	REG(ANA_TABLES_ENTRYLIM,		0x007f00),
81 	REG(ANA_TABLES_PTP_ID_HIGH,		0x007f44),
82 	REG(ANA_TABLES_PTP_ID_LOW,		0x007f48),
83 	REG(ANA_TABLES_STREAMACCESS,		0x007f4c),
84 	REG(ANA_TABLES_STREAMTIDX,		0x007f50),
85 	REG(ANA_TABLES_SEQ_HISTORY,		0x007f54),
86 	REG(ANA_TABLES_SEQ_MASK,		0x007f58),
87 	REG(ANA_TABLES_SFID_MASK,		0x007f5c),
88 	REG(ANA_TABLES_SFIDACCESS,		0x007f60),
89 	REG(ANA_TABLES_SFIDTIDX,		0x007f64),
90 	REG(ANA_MSTI_STATE,			0x008600),
91 	REG(ANA_OAM_UPM_LM_CNT,			0x008000),
92 	REG(ANA_SG_ACCESS_CTRL,			0x008a64),
93 	REG(ANA_SG_CONFIG_REG_1,		0x007fb0),
94 	REG(ANA_SG_CONFIG_REG_2,		0x007fb4),
95 	REG(ANA_SG_CONFIG_REG_3,		0x007fb8),
96 	REG(ANA_SG_CONFIG_REG_4,		0x007fbc),
97 	REG(ANA_SG_CONFIG_REG_5,		0x007fc0),
98 	REG(ANA_SG_GCL_GS_CONFIG,		0x007f80),
99 	REG(ANA_SG_GCL_TI_CONFIG,		0x007f90),
100 	REG(ANA_SG_STATUS_REG_1,		0x008980),
101 	REG(ANA_SG_STATUS_REG_2,		0x008984),
102 	REG(ANA_SG_STATUS_REG_3,		0x008988),
103 	REG(ANA_PORT_VLAN_CFG,			0x007800),
104 	REG(ANA_PORT_DROP_CFG,			0x007804),
105 	REG(ANA_PORT_QOS_CFG,			0x007808),
106 	REG(ANA_PORT_VCAP_CFG,			0x00780c),
107 	REG(ANA_PORT_VCAP_S1_KEY_CFG,		0x007810),
108 	REG(ANA_PORT_VCAP_S2_CFG,		0x00781c),
109 	REG(ANA_PORT_PCP_DEI_MAP,		0x007820),
110 	REG(ANA_PORT_CPU_FWD_CFG,		0x007860),
111 	REG(ANA_PORT_CPU_FWD_BPDU_CFG,		0x007864),
112 	REG(ANA_PORT_CPU_FWD_GARP_CFG,		0x007868),
113 	REG(ANA_PORT_CPU_FWD_CCM_CFG,		0x00786c),
114 	REG(ANA_PORT_PORT_CFG,			0x007870),
115 	REG(ANA_PORT_POL_CFG,			0x007874),
116 	REG(ANA_PORT_PTP_CFG,			0x007878),
117 	REG(ANA_PORT_PTP_DLY1_CFG,		0x00787c),
118 	REG(ANA_PORT_PTP_DLY2_CFG,		0x007880),
119 	REG(ANA_PORT_SFID_CFG,			0x007884),
120 	REG(ANA_PFC_PFC_CFG,			0x008800),
126 	REG(ANA_AGGR_CFG,			0x008a68),
127 	REG(ANA_CPUQ_CFG,			0x008a6c),
129 	REG(ANA_CPUQ_8021_CFG,			0x008a74),
130 	REG(ANA_DSCP_CFG,			0x008ab4),
131 	REG(ANA_DSCP_REWR_CFG,			0x008bb4),
132 	REG(ANA_VCAP_RNG_TYPE_CFG,		0x008bf4),
133 	REG(ANA_VCAP_RNG_VAL_CFG,		0x008c14),
137 	REG(ANA_DISCARD_CFG,			0x008c40),
138 	REG(ANA_FID_CFG,			0x008c44),
139 	REG(ANA_POL_PIR_CFG,			0x004000),
140 	REG(ANA_POL_CIR_CFG,			0x004004),
141 	REG(ANA_POL_MODE_CFG,			0x004008),
142 	REG(ANA_POL_PIR_STATE,			0x00400c),
143 	REG(ANA_POL_CIR_STATE,			0x004010),
145 	REG(ANA_POL_FLOWC,			0x008c48),
146 	REG(ANA_POL_HYST,			0x008cb4),
151 	REG(QS_XTR_GRP_CFG,			0x000000),
152 	REG(QS_XTR_RD,				0x000008),
153 	REG(QS_XTR_FRM_PRUNING,			0x000010),
154 	REG(QS_XTR_FLUSH,			0x000018),
155 	REG(QS_XTR_DATA_PRESENT,		0x00001c),
156 	REG(QS_XTR_CFG,				0x000020),
157 	REG(QS_INJ_GRP_CFG,			0x000024),
158 	REG(QS_INJ_WR,				0x00002c),
159 	REG(QS_INJ_CTRL,			0x000034),
160 	REG(QS_INJ_STATUS,			0x00003c),
161 	REG(QS_INJ_ERR,				0x000040),
167 	REG(VCAP_CORE_UPDATE_CTRL,		0x000000),
168 	REG(VCAP_CORE_MV_CFG,			0x000004),
170 	REG(VCAP_CACHE_ENTRY_DAT,		0x000008),
171 	REG(VCAP_CACHE_MASK_DAT,		0x000108),
172 	REG(VCAP_CACHE_ACTION_DAT,		0x000208),
173 	REG(VCAP_CACHE_CNT_DAT,			0x000308),
174 	REG(VCAP_CACHE_TG_DAT,			0x000388),
176 	REG(VCAP_CONST_VCAP_VER,		0x000398),
177 	REG(VCAP_CONST_ENTRY_WIDTH,		0x00039c),
178 	REG(VCAP_CONST_ENTRY_CNT,		0x0003a0),
179 	REG(VCAP_CONST_ENTRY_SWCNT,		0x0003a4),
180 	REG(VCAP_CONST_ENTRY_TG_WIDTH,		0x0003a8),
181 	REG(VCAP_CONST_ACTION_DEF_CNT,		0x0003ac),
182 	REG(VCAP_CONST_ACTION_WIDTH,		0x0003b0),
183 	REG(VCAP_CONST_CNT_WIDTH,		0x0003b4),
184 	REG(VCAP_CONST_CORE_CNT,		0x0003b8),
185 	REG(VCAP_CONST_IF_CNT,			0x0003bc),
189 	REG(QSYS_PORT_MODE,			0x00f460),
190 	REG(QSYS_SWITCH_PORT_MODE,		0x00f480),
191 	REG(QSYS_STAT_CNT_CFG,			0x00f49c),
192 	REG(QSYS_EEE_CFG,			0x00f4a0),
193 	REG(QSYS_EEE_THRES,			0x00f4b8),
194 	REG(QSYS_IGR_NO_SHARING,		0x00f4bc),
195 	REG(QSYS_EGR_NO_SHARING,		0x00f4c0),
196 	REG(QSYS_SW_STATUS,			0x00f4c4),
197 	REG(QSYS_EXT_CPU_CFG,			0x00f4e0),
199 	REG(QSYS_CPU_GROUP_MAP,			0x00f4e8),
203 	REG(QSYS_TFRM_MISC,			0x00f50c),
204 	REG(QSYS_TFRM_PORT_DLY,			0x00f510),
205 	REG(QSYS_TFRM_TIMER_CFG_1,		0x00f514),
206 	REG(QSYS_TFRM_TIMER_CFG_2,		0x00f518),
207 	REG(QSYS_TFRM_TIMER_CFG_3,		0x00f51c),
208 	REG(QSYS_TFRM_TIMER_CFG_4,		0x00f520),
209 	REG(QSYS_TFRM_TIMER_CFG_5,		0x00f524),
210 	REG(QSYS_TFRM_TIMER_CFG_6,		0x00f528),
211 	REG(QSYS_TFRM_TIMER_CFG_7,		0x00f52c),
212 	REG(QSYS_TFRM_TIMER_CFG_8,		0x00f530),
213 	REG(QSYS_RED_PROFILE,			0x00f534),
214 	REG(QSYS_RES_QOS_MODE,			0x00f574),
215 	REG(QSYS_RES_CFG,			0x00c000),
216 	REG(QSYS_RES_STAT,			0x00c004),
217 	REG(QSYS_EGR_DROP_MODE,			0x00f578),
218 	REG(QSYS_EQ_CTRL,			0x00f57c),
220 	REG(QSYS_QMAXSDU_CFG_0,			0x00f584),
221 	REG(QSYS_QMAXSDU_CFG_1,			0x00f5a0),
222 	REG(QSYS_QMAXSDU_CFG_2,			0x00f5bc),
223 	REG(QSYS_QMAXSDU_CFG_3,			0x00f5d8),
224 	REG(QSYS_QMAXSDU_CFG_4,			0x00f5f4),
225 	REG(QSYS_QMAXSDU_CFG_5,			0x00f610),
226 	REG(QSYS_QMAXSDU_CFG_6,			0x00f62c),
227 	REG(QSYS_QMAXSDU_CFG_7,			0x00f648),
228 	REG(QSYS_PREEMPTION_CFG,		0x00f664),
229 	REG(QSYS_CIR_CFG,			0x000000),
230 	REG(QSYS_EIR_CFG,			0x000004),
231 	REG(QSYS_SE_CFG,			0x000008),
232 	REG(QSYS_SE_DWRR_CFG,			0x00000c),
234 	REG(QSYS_SE_DLB_SENSE,			0x000040),
235 	REG(QSYS_CIR_STATE,			0x000044),
236 	REG(QSYS_EIR_STATE,			0x000048),
238 	REG(QSYS_HSCH_MISC_CFG,			0x00f67c),
239 	REG(QSYS_TAG_CONFIG,			0x00f680),
240 	REG(QSYS_TAS_PARAM_CFG_CTRL,		0x00f698),
241 	REG(QSYS_PORT_MAX_SDU,			0x00f69c),
242 	REG(QSYS_PARAM_CFG_REG_1,		0x00f440),
243 	REG(QSYS_PARAM_CFG_REG_2,		0x00f444),
244 	REG(QSYS_PARAM_CFG_REG_3,		0x00f448),
245 	REG(QSYS_PARAM_CFG_REG_4,		0x00f44c),
246 	REG(QSYS_PARAM_CFG_REG_5,		0x00f450),
247 	REG(QSYS_GCL_CFG_REG_1,			0x00f454),
248 	REG(QSYS_GCL_CFG_REG_2,			0x00f458),
249 	REG(QSYS_PARAM_STATUS_REG_1,		0x00f400),
250 	REG(QSYS_PARAM_STATUS_REG_2,		0x00f404),
251 	REG(QSYS_PARAM_STATUS_REG_3,		0x00f408),
252 	REG(QSYS_PARAM_STATUS_REG_4,		0x00f40c),
253 	REG(QSYS_PARAM_STATUS_REG_5,		0x00f410),
254 	REG(QSYS_PARAM_STATUS_REG_6,		0x00f414),
255 	REG(QSYS_PARAM_STATUS_REG_7,		0x00f418),
256 	REG(QSYS_PARAM_STATUS_REG_8,		0x00f41c),
257 	REG(QSYS_PARAM_STATUS_REG_9,		0x00f420),
258 	REG(QSYS_GCL_STATUS_REG_1,		0x00f424),
259 	REG(QSYS_GCL_STATUS_REG_2,		0x00f428),
263 	REG(REW_PORT_VLAN_CFG,			0x000000),
264 	REG(REW_TAG_CFG,			0x000004),
265 	REG(REW_PORT_CFG,			0x000008),
266 	REG(REW_DSCP_CFG,			0x00000c),
267 	REG(REW_PCP_DEI_QOS_MAP_CFG,		0x000010),
268 	REG(REW_PTP_CFG,			0x000050),
269 	REG(REW_PTP_DLY1_CFG,			0x000054),
270 	REG(REW_RED_TAG_CFG,			0x000058),
271 	REG(REW_DSCP_REMAP_DP1_CFG,		0x000410),
272 	REG(REW_DSCP_REMAP_CFG,			0x000510),
279 	REG(SYS_COUNT_RX_OCTETS,		0x000000),
280 	REG(SYS_COUNT_RX_UNICAST,		0x000004),
281 	REG(SYS_COUNT_RX_MULTICAST,		0x000008),
282 	REG(SYS_COUNT_RX_BROADCAST,		0x00000c),
283 	REG(SYS_COUNT_RX_SHORTS,		0x000010),
284 	REG(SYS_COUNT_RX_FRAGMENTS,		0x000014),
285 	REG(SYS_COUNT_RX_JABBERS,		0x000018),
286 	REG(SYS_COUNT_RX_CRC_ALIGN_ERRS,	0x00001c),
287 	REG(SYS_COUNT_RX_SYM_ERRS,		0x000020),
288 	REG(SYS_COUNT_RX_64,			0x000024),
289 	REG(SYS_COUNT_RX_65_127,		0x000028),
290 	REG(SYS_COUNT_RX_128_255,		0x00002c),
291 	REG(SYS_COUNT_RX_256_511,		0x000030),
292 	REG(SYS_COUNT_RX_512_1023,		0x000034),
293 	REG(SYS_COUNT_RX_1024_1526,		0x000038),
294 	REG(SYS_COUNT_RX_1527_MAX,		0x00003c),
295 	REG(SYS_COUNT_RX_PAUSE,			0x000040),
296 	REG(SYS_COUNT_RX_CONTROL,		0x000044),
297 	REG(SYS_COUNT_RX_LONGS,			0x000048),
298 	REG(SYS_COUNT_RX_CLASSIFIED_DROPS,	0x00004c),
299 	REG(SYS_COUNT_RX_RED_PRIO_0,		0x000050),
300 	REG(SYS_COUNT_RX_RED_PRIO_1,		0x000054),
301 	REG(SYS_COUNT_RX_RED_PRIO_2,		0x000058),
302 	REG(SYS_COUNT_RX_RED_PRIO_3,		0x00005c),
303 	REG(SYS_COUNT_RX_RED_PRIO_4,		0x000060),
304 	REG(SYS_COUNT_RX_RED_PRIO_5,		0x000064),
305 	REG(SYS_COUNT_RX_RED_PRIO_6,		0x000068),
306 	REG(SYS_COUNT_RX_RED_PRIO_7,		0x00006c),
307 	REG(SYS_COUNT_RX_YELLOW_PRIO_0,		0x000070),
308 	REG(SYS_COUNT_RX_YELLOW_PRIO_1,		0x000074),
309 	REG(SYS_COUNT_RX_YELLOW_PRIO_2,		0x000078),
310 	REG(SYS_COUNT_RX_YELLOW_PRIO_3,		0x00007c),
311 	REG(SYS_COUNT_RX_YELLOW_PRIO_4,		0x000080),
312 	REG(SYS_COUNT_RX_YELLOW_PRIO_5,		0x000084),
313 	REG(SYS_COUNT_RX_YELLOW_PRIO_6,		0x000088),
314 	REG(SYS_COUNT_RX_YELLOW_PRIO_7,		0x00008c),
315 	REG(SYS_COUNT_RX_GREEN_PRIO_0,		0x000090),
316 	REG(SYS_COUNT_RX_GREEN_PRIO_1,		0x000094),
317 	REG(SYS_COUNT_RX_GREEN_PRIO_2,		0x000098),
318 	REG(SYS_COUNT_RX_GREEN_PRIO_3,		0x00009c),
319 	REG(SYS_COUNT_RX_GREEN_PRIO_4,		0x0000a0),
320 	REG(SYS_COUNT_RX_GREEN_PRIO_5,		0x0000a4),
321 	REG(SYS_COUNT_RX_GREEN_PRIO_6,		0x0000a8),
322 	REG(SYS_COUNT_RX_GREEN_PRIO_7,		0x0000ac),
323 	REG(SYS_COUNT_RX_ASSEMBLY_ERRS,		0x0000b0),
324 	REG(SYS_COUNT_RX_SMD_ERRS,		0x0000b4),
325 	REG(SYS_COUNT_RX_ASSEMBLY_OK,		0x0000b8),
326 	REG(SYS_COUNT_RX_MERGE_FRAGMENTS,	0x0000bc),
327 	REG(SYS_COUNT_RX_PMAC_OCTETS,		0x0000c0),
328 	REG(SYS_COUNT_RX_PMAC_UNICAST,		0x0000c4),
329 	REG(SYS_COUNT_RX_PMAC_MULTICAST,	0x0000c8),
330 	REG(SYS_COUNT_RX_PMAC_BROADCAST,	0x0000cc),
331 	REG(SYS_COUNT_RX_PMAC_SHORTS,		0x0000d0),
332 	REG(SYS_COUNT_RX_PMAC_FRAGMENTS,	0x0000d4),
333 	REG(SYS_COUNT_RX_PMAC_JABBERS,		0x0000d8),
334 	REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS,	0x0000dc),
335 	REG(SYS_COUNT_RX_PMAC_SYM_ERRS,		0x0000e0),
336 	REG(SYS_COUNT_RX_PMAC_64,		0x0000e4),
337 	REG(SYS_COUNT_RX_PMAC_65_127,		0x0000e8),
338 	REG(SYS_COUNT_RX_PMAC_128_255,		0x0000ec),
339 	REG(SYS_COUNT_RX_PMAC_256_511,		0x0000f0),
340 	REG(SYS_COUNT_RX_PMAC_512_1023,		0x0000f4),
341 	REG(SYS_COUNT_RX_PMAC_1024_1526,	0x0000f8),
342 	REG(SYS_COUNT_RX_PMAC_1527_MAX,		0x0000fc),
343 	REG(SYS_COUNT_RX_PMAC_PAUSE,		0x000100),
344 	REG(SYS_COUNT_RX_PMAC_CONTROL,		0x000104),
345 	REG(SYS_COUNT_RX_PMAC_LONGS,		0x000108),
346 	REG(SYS_COUNT_TX_OCTETS,		0x000200),
347 	REG(SYS_COUNT_TX_UNICAST,		0x000204),
348 	REG(SYS_COUNT_TX_MULTICAST,		0x000208),
349 	REG(SYS_COUNT_TX_BROADCAST,		0x00020c),
350 	REG(SYS_COUNT_TX_COLLISION,		0x000210),
351 	REG(SYS_COUNT_TX_DROPS,			0x000214),
352 	REG(SYS_COUNT_TX_PAUSE,			0x000218),
353 	REG(SYS_COUNT_TX_64,			0x00021c),
354 	REG(SYS_COUNT_TX_65_127,		0x000220),
355 	REG(SYS_COUNT_TX_128_255,		0x000224),
356 	REG(SYS_COUNT_TX_256_511,		0x000228),
357 	REG(SYS_COUNT_TX_512_1023,		0x00022c),
358 	REG(SYS_COUNT_TX_1024_1526,		0x000230),
359 	REG(SYS_COUNT_TX_1527_MAX,		0x000234),
360 	REG(SYS_COUNT_TX_YELLOW_PRIO_0,		0x000238),
361 	REG(SYS_COUNT_TX_YELLOW_PRIO_1,		0x00023c),
362 	REG(SYS_COUNT_TX_YELLOW_PRIO_2,		0x000240),
363 	REG(SYS_COUNT_TX_YELLOW_PRIO_3,		0x000244),
364 	REG(SYS_COUNT_TX_YELLOW_PRIO_4,		0x000248),
365 	REG(SYS_COUNT_TX_YELLOW_PRIO_5,		0x00024c),
366 	REG(SYS_COUNT_TX_YELLOW_PRIO_6,		0x000250),
367 	REG(SYS_COUNT_TX_YELLOW_PRIO_7,		0x000254),
368 	REG(SYS_COUNT_TX_GREEN_PRIO_0,		0x000258),
369 	REG(SYS_COUNT_TX_GREEN_PRIO_1,		0x00025c),
370 	REG(SYS_COUNT_TX_GREEN_PRIO_2,		0x000260),
371 	REG(SYS_COUNT_TX_GREEN_PRIO_3,		0x000264),
372 	REG(SYS_COUNT_TX_GREEN_PRIO_4,		0x000268),
373 	REG(SYS_COUNT_TX_GREEN_PRIO_5,		0x00026c),
374 	REG(SYS_COUNT_TX_GREEN_PRIO_6,		0x000270),
375 	REG(SYS_COUNT_TX_GREEN_PRIO_7,		0x000274),
376 	REG(SYS_COUNT_TX_AGED,			0x000278),
377 	REG(SYS_COUNT_TX_MM_HOLD,		0x00027c),
378 	REG(SYS_COUNT_TX_MERGE_FRAGMENTS,	0x000280),
379 	REG(SYS_COUNT_TX_PMAC_OCTETS,		0x000284),
380 	REG(SYS_COUNT_TX_PMAC_UNICAST,		0x000288),
381 	REG(SYS_COUNT_TX_PMAC_MULTICAST,	0x00028c),
382 	REG(SYS_COUNT_TX_PMAC_BROADCAST,	0x000290),
383 	REG(SYS_COUNT_TX_PMAC_PAUSE,		0x000294),
384 	REG(SYS_COUNT_TX_PMAC_64,		0x000298),
385 	REG(SYS_COUNT_TX_PMAC_65_127,		0x00029c),
386 	REG(SYS_COUNT_TX_PMAC_128_255,		0x0002a0),
387 	REG(SYS_COUNT_TX_PMAC_256_511,		0x0002a4),
388 	REG(SYS_COUNT_TX_PMAC_512_1023,		0x0002a8),
389 	REG(SYS_COUNT_TX_PMAC_1024_1526,	0x0002ac),
390 	REG(SYS_COUNT_TX_PMAC_1527_MAX,		0x0002b0),
391 	REG(SYS_COUNT_DROP_LOCAL,		0x000400),
392 	REG(SYS_COUNT_DROP_TAIL,		0x000404),
393 	REG(SYS_COUNT_DROP_YELLOW_PRIO_0,	0x000408),
394 	REG(SYS_COUNT_DROP_YELLOW_PRIO_1,	0x00040c),
395 	REG(SYS_COUNT_DROP_YELLOW_PRIO_2,	0x000410),
396 	REG(SYS_COUNT_DROP_YELLOW_PRIO_3,	0x000414),
397 	REG(SYS_COUNT_DROP_YELLOW_PRIO_4,	0x000418),
398 	REG(SYS_COUNT_DROP_YELLOW_PRIO_5,	0x00041c),
399 	REG(SYS_COUNT_DROP_YELLOW_PRIO_6,	0x000420),
400 	REG(SYS_COUNT_DROP_YELLOW_PRIO_7,	0x000424),
401 	REG(SYS_COUNT_DROP_GREEN_PRIO_0,	0x000428),
402 	REG(SYS_COUNT_DROP_GREEN_PRIO_1,	0x00042c),
403 	REG(SYS_COUNT_DROP_GREEN_PRIO_2,	0x000430),
404 	REG(SYS_COUNT_DROP_GREEN_PRIO_3,	0x000434),
405 	REG(SYS_COUNT_DROP_GREEN_PRIO_4,	0x000438),
406 	REG(SYS_COUNT_DROP_GREEN_PRIO_5,	0x00043c),
407 	REG(SYS_COUNT_DROP_GREEN_PRIO_6,	0x000440),
408 	REG(SYS_COUNT_DROP_GREEN_PRIO_7,	0x000444),
409 	REG(SYS_COUNT_SF_MATCHING_FRAMES,	0x000800),
410 	REG(SYS_COUNT_SF_NOT_PASSING_FRAMES,	0x000804),
411 	REG(SYS_COUNT_SF_NOT_PASSING_SDU,	0x000808),
412 	REG(SYS_COUNT_SF_RED_FRAMES,		0x00080c),
413 	REG(SYS_RESET_CFG,			0x000e00),
414 	REG(SYS_SR_ETYPE_CFG,			0x000e04),
415 	REG(SYS_VLAN_ETYPE_CFG,			0x000e08),
416 	REG(SYS_PORT_MODE,			0x000e0c),
417 	REG(SYS_FRONT_PORT_MODE,		0x000e2c),
418 	REG(SYS_FRM_AGING,			0x000e44),
419 	REG(SYS_STAT_CFG,			0x000e48),
420 	REG(SYS_SW_STATUS,			0x000e4c),
422 	REG(SYS_REW_MAC_HIGH_CFG,		0x000e6c),
423 	REG(SYS_REW_MAC_LOW_CFG,		0x000e84),
424 	REG(SYS_TIMESTAMP_OFFSET,		0x000e9c),
425 	REG(SYS_PAUSE_CFG,			0x000ea0),
426 	REG(SYS_PAUSE_TOT_CFG,			0x000ebc),
427 	REG(SYS_ATOP,				0x000ec0),
428 	REG(SYS_ATOP_TOT_CFG,			0x000edc),
429 	REG(SYS_MAC_FC_CFG,			0x000ee0),
430 	REG(SYS_MMGT,				0x000ef8),
434 	REG(SYS_PTP_STATUS,			0x000f14),
435 	REG(SYS_PTP_TXSTAMP,			0x000f18),
436 	REG(SYS_PTP_NXT,			0x000f1c),
437 	REG(SYS_PTP_CFG,			0x000f20),
438 	REG(SYS_RAM_INIT,			0x000f24),
447 	REG(PTP_PIN_CFG,			0x000000),
448 	REG(PTP_PIN_TOD_SEC_MSB,		0x000004),
449 	REG(PTP_PIN_TOD_SEC_LSB,		0x000008),
450 	REG(PTP_PIN_TOD_NSEC,			0x00000c),
451 	REG(PTP_PIN_WF_HIGH_PERIOD,		0x000014),
452 	REG(PTP_PIN_WF_LOW_PERIOD,		0x000018),
453 	REG(PTP_CFG_MISC,			0x0000a0),
454 	REG(PTP_CLK_CFG_ADJ_CFG,		0x0000a4),
455 	REG(PTP_CLK_CFG_ADJ_FREQ,		0x0000a8),
459 	REG(GCB_SOFT_RST,			0x000004),
463 	REG(DEV_CLOCK_CFG,			0x0),
464 	REG(DEV_PORT_MISC,			0x4),
465 	REG(DEV_EVENTS,				0x8),
466 	REG(DEV_EEE_CFG,			0xc),
467 	REG(DEV_RX_PATH_DELAY,			0x10),
468 	REG(DEV_TX_PATH_DELAY,			0x14),
469 	REG(DEV_PTP_PREDICT_CFG,		0x18),
470 	REG(DEV_MAC_ENA_CFG,			0x1c),
471 	REG(DEV_MAC_MODE_CFG,			0x20),
472 	REG(DEV_MAC_MAXLEN_CFG,			0x24),
473 	REG(DEV_MAC_TAGS_CFG,			0x28),
474 	REG(DEV_MAC_ADV_CHK_CFG,		0x2c),
475 	REG(DEV_MAC_IFG_CFG,			0x30),
476 	REG(DEV_MAC_HDX_CFG,			0x34),
477 	REG(DEV_MAC_DBG_CFG,			0x38),
478 	REG(DEV_MAC_FC_MAC_LOW_CFG,		0x3c),
479 	REG(DEV_MAC_FC_MAC_HIGH_CFG,		0x40),
480 	REG(DEV_MAC_STICKY,			0x44),
481 	REG(DEV_MM_ENABLE_CONFIG,		0x48),
482 	REG(DEV_MM_VERIF_CONFIG,		0x4C),
483 	REG(DEV_MM_STATUS,			0x50),
523 	DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"),
524 	DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"),
525 	DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"),
526 	DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"),
527 	DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"),
528 	DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"),
529 	DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"),
530 	DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"),
531 	DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"),
532 	DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"),
533 	DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"),
534 	DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"),
535 	DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"),
536 	DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"),
537 	DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
538 	DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"),
554 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
558 	DEFINE_RES_MEM_NAMED(0x8030, 0x10, "imdio");
562 	[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
588 	[ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
591 	[ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
592 	[SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
593 	[GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
600 	[QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
604 	[SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
607 	[SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
611 	[VCAP_ES0_EGR_PORT]			= {  0,  3},
622 	[VCAP_ES0_ACT_PUSH_OUTER_TAG]		= {  0,  2},
643 	[VCAP_IS1_HK_TYPE]			= {  0,   1},
694 	[VCAP_IS1_ACT_DSCP_ENA]			= {  0,  1},
719 	[VCAP_IS2_TYPE]				= {  0,   4},
798 	[VCAP_IS2_ACT_HIT_ME_ONCE]		= {  0,  1},
817 		.action_type_width = 0,
829 		.action_type_width = 0,
861 	.max_adj	= 0x7fffffff,
862 	.n_alarm	= 0,
863 	.n_ext_ts	= 0,
866 	.pps		= 0,
923 	return 0;  in vsc9959_reset()
927  * Bit 8:   Unit; 0:1, 1:16
928  * Bit 7-0: Value to be multiplied with unit
942 	WARN_ON(wm & ~GENMASK(8, 0));  in vsc9959_wm_dec()
945 		return (wm & GENMASK(7, 0)) * 16;  in vsc9959_wm_dec()
953 	*maxuse = val & GENMASK(11, 0);  in vsc9959_wm_stat()
1009 	mdio_priv->mdio_base = 0;  in vsc9959_mdio_bus_alloc()
1014 	if (rc < 0) {  in vsc9959_mdio_bus_alloc()
1022 	for (port = 0; port < felix->info->num_ports; port++) {  in vsc9959_mdio_bus_alloc()
1041 	return 0;  in vsc9959_mdio_bus_alloc()
1049 	for (port = 0; port < ocelot->num_phys_ports; port++) {  in vsc9959_mdio_bus_free()
1074 		return 0;  in vsc9959_tas_remaining_gate_len_ps()
1081  * considered U64_MAX. If the gate is always closed, it is considered 0.
1088 	u8 gates_ever_opened = 0;  in vsc9959_tas_min_gate_lengths()
1092 	for (tc = 0; tc < OCELOT_NUM_TC; tc++) {  in vsc9959_tas_min_gate_lengths()
1094 		gate_len[tc] = 0;  in vsc9959_tas_min_gate_lengths()
1110 	for (i = 0; i < 2 * n; i++) {  in vsc9959_tas_min_gate_lengths()
1113 		for (tc = 0; tc < OCELOT_NUM_TC; tc++) {  in vsc9959_tas_min_gate_lengths()
1124 				gate_len[tc] = 0;  in vsc9959_tas_min_gate_lengths()
1132 	 * open gates. Overwrite the gate len with 0 when we know they're  in vsc9959_tas_min_gate_lengths()
1135 	for (tc = 0; tc < OCELOT_NUM_TC; tc++)  in vsc9959_tas_min_gate_lengths()
1137 			min_gate_len[tc] = 0;  in vsc9959_tas_min_gate_lengths()
1148 	case 0:  in vsc9959_port_qmaxsdu_set()
1186 	case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port);  in vsc9959_port_qmaxsdu_get()
1195 		return 0;  in vsc9959_port_qmaxsdu_get()
1202 		return 0;  in vsc9959_tas_tc_max_sdu()
1277 	for (tc = 0; tc < OCELOT_NUM_TC; tc++) {  in vsc9959_tas_guard_bands_update()
1288 			/* Setting QMAXSDU_CFG to 0 disables oversized frame  in vsc9959_tas_guard_bands_update()
1316 			 * max_sdu to go negative or to 0. Here we use 20  in vsc9959_tas_guard_bands_update()
1429 		ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,  in vsc9959_qos_port_tas_set()
1438 		return 0;  in vsc9959_qos_port_tas_set()
1488 		       QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |  in vsc9959_qos_port_tas_set()
1489 		       QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),  in vsc9959_qos_port_tas_set()
1507 	for (i = 0; i < taprio->num_entries; i++)  in vsc9959_qos_port_tas_set()
1525 	return 0;  in vsc9959_qos_port_tas_set()
1528 	taprio->mqprio.qopt.num_tc = 0;  in vsc9959_qos_port_tas_set()
1546 	for (port = 0; port < ocelot->num_phys_ports; port++) {  in vsc9959_tas_clock_adjust()
1558 		ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,  in vsc9959_tas_clock_adjust()
1596 		ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |  in vsc9959_qos_port_cbs_set()
1597 				 QSYS_CIR_CFG_CIR_BURST(0),  in vsc9959_qos_port_cbs_set()
1600 		ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,  in vsc9959_qos_port_cbs_set()
1603 		return 0;  in vsc9959_qos_port_cbs_set()
1609 	rate = clamp_t(u32, rate, 1, GENMASK(14, 0));  in vsc9959_qos_port_cbs_set()
1613 	burst = clamp_t(u32, burst, 1, GENMASK(5, 0));  in vsc9959_qos_port_cbs_set()
1621 		       QSYS_SE_CFG_SE_FRM_MODE(0) |  in vsc9959_qos_port_cbs_set()
1628 	return 0;  in vsc9959_qos_port_cbs_set()
1639 		return 0;  in vsc9959_qos_query_caps()
1646 		return 0;  in vsc9959_qos_query_caps()
1793 	return 0;  in vsc9959_stream_identify()
1867 	return 0;  in vsc9959_stream_table_add()
1922 		     (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |  in vsc9959_psfp_sfi_set()
1924 		     (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |  in vsc9959_psfp_sfi_set()
1930 		     (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |  in vsc9959_psfp_sfi_set()
1988 	return 0;  in vsc9959_psfp_sfi_list_add()
1997 	u32 insert = 0;  in vsc9959_psfp_sfi_table_add()
2011 			return 0;  in vsc9959_psfp_sfi_table_add()
2031 	u32 insert = 0;  in vsc9959_psfp_sfi_table_add2()
2081 				tmp->enable = 0;  in vsc9959_psfp_sfi_table_del()
2094 	sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;  in vsc9959_psfp_parse_gate()
2095 	sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;  in vsc9959_psfp_parse_gate()
2115 	u32 interval_sum = 0;  in vsc9959_psfp_sgi_set()
2131 		return 0;  in vsc9959_psfp_sgi_set()
2148 		     (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |  in vsc9959_psfp_sgi_set()
2159 	for (i = 0; i < sgi->num_entries; i++) {  in vsc9959_psfp_sgi_set()
2160 		u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);  in vsc9959_psfp_sgi_set()
2164 				  ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),  in vsc9959_psfp_sgi_set()
2192 			return 0;  in vsc9959_psfp_sgi_table_add()
2209 	return 0;  in vsc9959_psfp_sgi_table_add()
2216 	struct felix_stream_gate sgi = {0};  in vsc9959_psfp_sgi_table_del()
2227 				sgi.enable = 0;  in vsc9959_psfp_sgi_table_del()
2241 	struct felix_stream_filter sfi = {0};  in vsc9959_psfp_filter_add()
2244 	struct felix_stream stream = {0};  in vsc9959_psfp_filter_add()
2312 	sfi.prio_valid = (stream.prio < 0 ? 0 : 1);  in vsc9959_psfp_filter_add()
2313 	sfi.prio = (sfi.prio_valid ? stream.prio : 0);  in vsc9959_psfp_filter_add()
2375 	return 0;  in vsc9959_psfp_filter_add()
2420 	stream->sfid_valid = 0;  in vsc9959_psfp_filter_del()
2436 	return 0;  in vsc9959_psfp_filter_del()
2460 		     SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),  in vsc9959_update_sfid_stats()
2508 	memset(s, 0, sizeof(*s));  in vsc9959_psfp_stats_get()
2512 	return 0;  in vsc9959_psfp_stats_get()
2542 	for (port = 0; port < ocelot->num_phys_ports; port++) {  in vsc9959_cut_through_fwd()
2546 		unsigned long mask = 0;  in vsc9959_cut_through_fwd()
2547 		u32 tmp, val = 0;  in vsc9959_cut_through_fwd()
2550 		if (ocelot_port->speed <= 0)  in vsc9959_cut_through_fwd()
2562 			if (ocelot->npi >= 0)  in vsc9959_cut_through_fwd()
2576 			if (other_ocelot_port->speed <= 0)  in vsc9959_cut_through_fwd()
2590 			val = GENMASK(7, 0) & ~mm->active_preemptible_tcs;  in vsc9959_cut_through_fwd()
2592 			for (tc = 0; tc < OCELOT_NUM_TC; tc++)  in vsc9959_cut_through_fwd()
2603 			"port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n",  in vsc9959_cut_through_fwd()
2660 	.vcap_pol_base2		= 0,
2661 	.vcap_pol_max2		= 0,
2698 	return 0;  in felix_pci_probe()
2732 		PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
2734 	{ 0, }