Lines Matching +full:chip +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
13 #include "chip.h"
16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) in mv88e6xxx_g1_read() argument
18 int addr = chip->info->global1_addr; in mv88e6xxx_g1_read()
20 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_g1_read()
23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) in mv88e6xxx_g1_write() argument
25 int addr = chip->info->global1_addr; in mv88e6xxx_g1_write()
27 return mv88e6xxx_write(chip, addr, reg, val); in mv88e6xxx_g1_write()
30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int in mv88e6xxx_g1_wait_bit() argument
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_bit()
37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, in mv88e6xxx_g1_wait_mask() argument
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_mask()
46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) in mv88e6185_g1_wait_ppu_disabled() argument
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, in mv88e6185_g1_wait_ppu_disabled()
53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) in mv88e6185_g1_wait_ppu_polling() argument
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, in mv88e6185_g1_wait_ppu_polling()
60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) in mv88e6352_g1_wait_ppu_polling() argument
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); in mv88e6352_g1_wait_ppu_polling()
67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_wait_init_ready() argument
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 in mv88e6xxx_g1_wait_init_ready()
72 * is set to a one when all units inside the device (ATU, VTU, etc.) in mv88e6xxx_g1_wait_init_ready()
73 * have finished their initialization and are ready to accept frames. in mv88e6xxx_g1_wait_init_ready()
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); in mv88e6xxx_g1_wait_init_ready()
78 static int mv88e6250_g1_eeprom_reload(struct mv88e6xxx_chip *chip) in mv88e6250_g1_eeprom_reload() argument
85 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6250_g1_eeprom_reload()
91 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6250_g1_eeprom_reload()
95 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_CTL1, bit, 0); in mv88e6250_g1_eeprom_reload()
98 /* Returns 0 when done, -EBUSY when waiting, other negative codes on error */
99 static int mv88e6xxx_g1_is_eeprom_done(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_is_eeprom_done() argument
104 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); in mv88e6xxx_g1_is_eeprom_done()
106 dev_err(chip->dev, "Error reading status"); in mv88e6xxx_g1_is_eeprom_done()
113 * the EEPROM to be done by bit 0 being set. in mv88e6xxx_g1_is_eeprom_done()
116 return -EBUSY; in mv88e6xxx_g1_is_eeprom_done()
125 int mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_wait_eeprom_done() argument
130 /* Wait up to 1 second for the switch to finish reading the in mv88e6xxx_g1_wait_eeprom_done()
134 ret = mv88e6xxx_g1_is_eeprom_done(chip); in mv88e6xxx_g1_wait_eeprom_done()
135 if (ret != -EBUSY) in mv88e6xxx_g1_wait_eeprom_done()
139 dev_err(chip->dev, "Timeout waiting for EEPROM done"); in mv88e6xxx_g1_wait_eeprom_done()
140 return -ETIMEDOUT; in mv88e6xxx_g1_wait_eeprom_done()
143 int mv88e6250_g1_wait_eeprom_done_prereset(struct mv88e6xxx_chip *chip) in mv88e6250_g1_wait_eeprom_done_prereset() argument
147 ret = mv88e6xxx_g1_is_eeprom_done(chip); in mv88e6250_g1_wait_eeprom_done_prereset()
148 if (ret != -EBUSY) in mv88e6250_g1_wait_eeprom_done_prereset()
151 /* Pre-reset, we don't know the state of the switch - when in mv88e6250_g1_wait_eeprom_done_prereset()
152 * mv88e6xxx_g1_is_eeprom_done() returns -EBUSY, that may be because in mv88e6250_g1_wait_eeprom_done_prereset()
157 * To account for the latter case, trigger another EEPROM reload for in mv88e6250_g1_wait_eeprom_done_prereset()
160 ret = mv88e6250_g1_eeprom_reload(chip); in mv88e6250_g1_wait_eeprom_done_prereset()
164 return mv88e6xxx_g1_wait_eeprom_done(chip); in mv88e6250_g1_wait_eeprom_done_prereset()
171 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) in mv88e6xxx_g1_set_switch_mac() argument
177 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); in mv88e6xxx_g1_set_switch_mac()
182 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); in mv88e6xxx_g1_set_switch_mac()
187 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); in mv88e6xxx_g1_set_switch_mac()
196 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) in mv88e6185_g1_reset() argument
201 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart in mv88e6185_g1_reset()
202 * the PPU, including re-doing PHY detection and initialization in mv88e6185_g1_reset()
204 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_reset()
211 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_reset()
215 err = mv88e6xxx_g1_wait_init_ready(chip); in mv88e6185_g1_reset()
219 return mv88e6185_g1_wait_ppu_polling(chip); in mv88e6185_g1_reset()
222 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) in mv88e6250_g1_reset() argument
228 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6250_g1_reset()
234 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6250_g1_reset()
238 return mv88e6xxx_g1_wait_init_ready(chip); in mv88e6250_g1_reset()
241 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) in mv88e6352_g1_reset() argument
245 err = mv88e6250_g1_reset(chip); in mv88e6352_g1_reset()
249 return mv88e6352_g1_wait_ppu_polling(chip); in mv88e6352_g1_reset()
252 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) in mv88e6185_g1_ppu_enable() argument
257 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_enable()
263 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_enable()
267 return mv88e6185_g1_wait_ppu_polling(chip); in mv88e6185_g1_ppu_enable()
270 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) in mv88e6185_g1_ppu_disable() argument
275 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_disable()
281 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_disable()
285 return mv88e6185_g1_wait_ppu_disabled(chip); in mv88e6185_g1_ppu_disable()
288 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) in mv88e6185_g1_set_max_frame_size() argument
295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_set_max_frame_size()
304 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_set_max_frame_size()
307 /* Offset 0x10: IP-PRI Mapping Register 0
308 * Offset 0x11: IP-PRI Mapping Register 1
309 * Offset 0x12: IP-PRI Mapping Register 2
310 * Offset 0x13: IP-PRI Mapping Register 3
311 * Offset 0x14: IP-PRI Mapping Register 4
312 * Offset 0x15: IP-PRI Mapping Register 5
313 * Offset 0x16: IP-PRI Mapping Register 6
314 * Offset 0x17: IP-PRI Mapping Register 7
317 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) in mv88e6085_g1_ip_pri_map() argument
321 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ in mv88e6085_g1_ip_pri_map()
322 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); in mv88e6085_g1_ip_pri_map()
326 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); in mv88e6085_g1_ip_pri_map()
330 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); in mv88e6085_g1_ip_pri_map()
334 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); in mv88e6085_g1_ip_pri_map()
338 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); in mv88e6085_g1_ip_pri_map()
342 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); in mv88e6085_g1_ip_pri_map()
346 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); in mv88e6085_g1_ip_pri_map()
350 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); in mv88e6085_g1_ip_pri_map()
357 /* Offset 0x18: IEEE-PRI Register */
359 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) in mv88e6085_g1_ieee_pri_map() argument
361 /* Reset the IEEE Tag priorities to defaults */ in mv88e6085_g1_ieee_pri_map()
362 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); in mv88e6085_g1_ieee_pri_map()
365 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) in mv88e6250_g1_ieee_pri_map() argument
367 /* Reset the IEEE Tag priorities to defaults */ in mv88e6250_g1_ieee_pri_map()
368 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); in mv88e6250_g1_ieee_pri_map()
374 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, in mv88e6095_g1_set_egress_port() argument
381 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); in mv88e6095_g1_set_egress_port()
397 return -EINVAL; in mv88e6095_g1_set_egress_port()
400 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); in mv88e6095_g1_set_egress_port()
407 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) in mv88e6095_g1_set_cpu_port() argument
412 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); in mv88e6095_g1_set_cpu_port()
419 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); in mv88e6095_g1_set_cpu_port()
422 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, in mv88e6390_g1_monitor_write() argument
429 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); in mv88e6390_g1_monitor_write()
432 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, in mv88e6390_g1_set_egress_port() argument
446 return -EINVAL; in mv88e6390_g1_set_egress_port()
449 return mv88e6390_g1_monitor_write(chip, ptr, port); in mv88e6390_g1_set_egress_port()
452 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) in mv88e6390_g1_set_cpu_port() argument
456 /* Use the default high priority for management frames sent to in mv88e6390_g1_set_cpu_port()
461 return mv88e6390_g1_monitor_write(chip, ptr, port); in mv88e6390_g1_set_cpu_port()
464 int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port) in mv88e6390_g1_set_ptp_cpu_port() argument
468 /* Use the default high priority for PTP frames sent to in mv88e6390_g1_set_ptp_cpu_port()
473 return mv88e6390_g1_monitor_write(chip, ptr, port); in mv88e6390_g1_set_ptp_cpu_port()
476 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) in mv88e6390_g1_mgmt_rsvd2cpu() argument
481 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
483 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
487 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
489 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
493 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
495 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
499 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
501 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
510 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, in mv88e6xxx_g1_ctl2_mask() argument
516 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); in mv88e6xxx_g1_ctl2_mask()
523 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); in mv88e6xxx_g1_ctl2_mask()
526 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) in mv88e6185_g1_set_cascade_port() argument
530 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); in mv88e6185_g1_set_cascade_port()
533 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) in mv88e6085_g1_rmu_disable() argument
535 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | in mv88e6085_g1_rmu_disable()
539 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) in mv88e6352_g1_rmu_disable() argument
541 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, in mv88e6352_g1_rmu_disable()
545 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) in mv88e6390_g1_rmu_disable() argument
547 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, in mv88e6390_g1_rmu_disable()
551 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) in mv88e6390_g1_stats_set_histogram() argument
553 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, in mv88e6390_g1_stats_set_histogram()
557 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) in mv88e6xxx_g1_set_device_number() argument
559 return mv88e6xxx_g1_ctl2_mask(chip, in mv88e6xxx_g1_set_device_number()
566 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_stats_wait() argument
570 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); in mv88e6xxx_g1_stats_wait()
573 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) in mv88e6095_g1_stats_set_histogram() argument
578 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); in mv88e6095_g1_stats_set_histogram()
584 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); in mv88e6095_g1_stats_set_histogram()
589 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) in mv88e6xxx_g1_stats_snapshot() argument
594 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, in mv88e6xxx_g1_stats_snapshot()
601 /* Wait for the snapshotting to complete. */ in mv88e6xxx_g1_stats_snapshot()
602 return mv88e6xxx_g1_stats_wait(chip); in mv88e6xxx_g1_stats_snapshot()
605 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) in mv88e6320_g1_stats_snapshot() argument
609 return mv88e6xxx_g1_stats_snapshot(chip, port); in mv88e6320_g1_stats_snapshot()
612 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) in mv88e6390_g1_stats_snapshot() argument
619 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, in mv88e6390_g1_stats_snapshot()
625 /* Wait for the snapshotting to complete. */ in mv88e6390_g1_stats_snapshot()
626 return mv88e6xxx_g1_stats_wait(chip); in mv88e6390_g1_stats_snapshot()
629 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) in mv88e6xxx_g1_stats_read() argument
637 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, in mv88e6xxx_g1_stats_read()
643 err = mv88e6xxx_g1_stats_wait(chip); in mv88e6xxx_g1_stats_read()
647 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); in mv88e6xxx_g1_stats_read()
653 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); in mv88e6xxx_g1_stats_read()
660 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_stats_clear() argument
665 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); in mv88e6xxx_g1_stats_clear()
673 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); in mv88e6xxx_g1_stats_clear()
677 /* Wait for the flush to complete. */ in mv88e6xxx_g1_stats_clear()
678 return mv88e6xxx_g1_stats_wait(chip); in mv88e6xxx_g1_stats_clear()