Lines Matching +full:mt7531 +full:- +full:dsa +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mediatek MT7530 DSA Switch driver
23 #include <net/dsa.h>
49 if (priv->bus) in mt7530_mutex_lock()
50 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
56 if (priv->bus) in mt7530_mutex_unlock()
57 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
63 struct mii_bus *bus = priv->bus; in core_write()
69 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
75 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
81 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
87 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
91 dev_err(&bus->dev, "failed to write mmd register\n"); in core_write()
99 struct mii_bus *bus = priv->bus; in core_rmw()
106 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
112 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
118 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
124 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
129 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
133 dev_err(&bus->dev, "failed to write mmd register\n"); in core_rmw()
155 ret = regmap_write(priv->regmap, reg, val); in mt7530_mii_write()
158 dev_err(priv->dev, in mt7530_mii_write()
170 ret = regmap_read(priv->regmap, reg, &val); in mt7530_mii_read()
173 dev_err(priv->dev, in mt7530_mii_read()
194 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
202 mt7530_mutex_lock(p->priv); in _mt7530_read()
204 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
206 mt7530_mutex_unlock(p->priv); in _mt7530_read()
226 regmap_update_bits(priv->regmap, reg, mask, set); in mt7530_rmw()
258 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
267 return -EINVAL; in mt7530_fdb_cmd()
285 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
289 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
290 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
291 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
292 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
293 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
294 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
295 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
296 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
297 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
298 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
357 /* If port 6 is available as a CPU port, always prefer that as the default,
371 /* Setup port 6 interface mode and TRGMII TX circuit */
375 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port6()
396 if (priv->id == ID_MT7621) { in mt7530_setup_port6()
443 /* Step 1 : Disable MT7531 COREPLL */ in mt7531_pll_setup()
502 /* Step 6: Enable MT7531 PLL */ in mt7531_pll_setup()
516 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
522 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) in mt7530_phy_read_c22() argument
524 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read_c22()
527 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, in mt7530_phy_write_c22() argument
530 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write_c22()
533 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, in mt7530_phy_read_c45() argument
536 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); in mt7530_phy_read_c45()
539 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, in mt7530_phy_write_c45() argument
542 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); in mt7530_phy_write_c45()
546 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_read() argument
560 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
564 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
571 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
575 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
582 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
594 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_write() argument
608 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
612 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
619 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
623 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
630 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
641 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) in mt7531_ind_c22_phy_read() argument
654 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
658 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_read()
666 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
678 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, in mt7531_ind_c22_phy_write() argument
692 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
696 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_write()
704 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
715 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) in mt753x_phy_read_c22() argument
717 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c22()
719 return priv->info->phy_read_c22(priv, port, regnum); in mt753x_phy_read_c22()
723 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) in mt753x_phy_read_c45() argument
725 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c45()
727 return priv->info->phy_read_c45(priv, port, devad, regnum); in mt753x_phy_read_c45()
731 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) in mt753x_phy_write_c22() argument
733 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c22()
735 return priv->info->phy_write_c22(priv, port, regnum, val); in mt753x_phy_write_c22()
739 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, in mt753x_phy_write_c45() argument
742 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c45()
744 return priv->info->phy_write_c45(priv, port, devad, regnum, val); in mt753x_phy_write_c45()
748 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, in mt7530_get_strings() argument
761 mt7530_read_port_stats(struct mt7530_priv *priv, int port, in mt7530_read_port_stats() argument
764 u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset; in mt7530_read_port_stats()
776 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, in mt7530_get_ethtool_stats() argument
779 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
786 mt7530_read_port_stats(priv, port, mib->offset, mib->size, in mt7530_get_ethtool_stats()
792 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) in mt7530_get_sset_count() argument
800 static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port, in mt7530_get_eth_mac_stats() argument
803 struct mt7530_priv *priv = ds->priv; in mt7530_get_eth_mac_stats()
810 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, in mt7530_get_eth_mac_stats()
811 &mac_stats->FramesTransmittedOK); in mt7530_get_eth_mac_stats()
813 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, in mt7530_get_eth_mac_stats()
814 &mac_stats->SingleCollisionFrames); in mt7530_get_eth_mac_stats()
816 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1, in mt7530_get_eth_mac_stats()
817 &mac_stats->MultipleCollisionFrames); in mt7530_get_eth_mac_stats()
819 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, in mt7530_get_eth_mac_stats()
820 &mac_stats->FramesReceivedOK); in mt7530_get_eth_mac_stats()
822 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, in mt7530_get_eth_mac_stats()
823 &mac_stats->OctetsTransmittedOK); in mt7530_get_eth_mac_stats()
825 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, in mt7530_get_eth_mac_stats()
826 &mac_stats->AlignmentErrors); in mt7530_get_eth_mac_stats()
828 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, in mt7530_get_eth_mac_stats()
829 &mac_stats->FramesWithDeferredXmissions); in mt7530_get_eth_mac_stats()
831 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, in mt7530_get_eth_mac_stats()
832 &mac_stats->LateCollisions); in mt7530_get_eth_mac_stats()
834 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, in mt7530_get_eth_mac_stats()
835 &mac_stats->FramesAbortedDueToXSColls); in mt7530_get_eth_mac_stats()
837 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, in mt7530_get_eth_mac_stats()
838 &mac_stats->OctetsReceivedOK); in mt7530_get_eth_mac_stats()
840 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, in mt7530_get_eth_mac_stats()
841 &mac_stats->MulticastFramesXmittedOK); in mt7530_get_eth_mac_stats()
842 mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; in mt7530_get_eth_mac_stats()
843 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, in mt7530_get_eth_mac_stats()
844 &mac_stats->BroadcastFramesXmittedOK); in mt7530_get_eth_mac_stats()
845 mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; in mt7530_get_eth_mac_stats()
847 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, in mt7530_get_eth_mac_stats()
848 &mac_stats->MulticastFramesReceivedOK); in mt7530_get_eth_mac_stats()
849 mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; in mt7530_get_eth_mac_stats()
850 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, in mt7530_get_eth_mac_stats()
851 &mac_stats->BroadcastFramesReceivedOK); in mt7530_get_eth_mac_stats()
852 mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; in mt7530_get_eth_mac_stats()
865 static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, in mt7530_get_rmon_stats() argument
869 struct mt7530_priv *priv = ds->priv; in mt7530_get_rmon_stats()
871 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, in mt7530_get_rmon_stats()
872 &rmon_stats->undersize_pkts); in mt7530_get_rmon_stats()
873 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, in mt7530_get_rmon_stats()
874 &rmon_stats->oversize_pkts); in mt7530_get_rmon_stats()
875 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, in mt7530_get_rmon_stats()
876 &rmon_stats->fragments); in mt7530_get_rmon_stats()
877 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, in mt7530_get_rmon_stats()
878 &rmon_stats->jabbers); in mt7530_get_rmon_stats()
880 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, in mt7530_get_rmon_stats()
881 &rmon_stats->hist[0]); in mt7530_get_rmon_stats()
882 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, in mt7530_get_rmon_stats()
883 &rmon_stats->hist[1]); in mt7530_get_rmon_stats()
884 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, in mt7530_get_rmon_stats()
885 &rmon_stats->hist[2]); in mt7530_get_rmon_stats()
886 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, in mt7530_get_rmon_stats()
887 &rmon_stats->hist[3]); in mt7530_get_rmon_stats()
888 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, in mt7530_get_rmon_stats()
889 &rmon_stats->hist[4]); in mt7530_get_rmon_stats()
890 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1, in mt7530_get_rmon_stats()
891 &rmon_stats->hist[5]); in mt7530_get_rmon_stats()
893 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, in mt7530_get_rmon_stats()
894 &rmon_stats->hist_tx[0]); in mt7530_get_rmon_stats()
895 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, in mt7530_get_rmon_stats()
896 &rmon_stats->hist_tx[1]); in mt7530_get_rmon_stats()
897 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, in mt7530_get_rmon_stats()
898 &rmon_stats->hist_tx[2]); in mt7530_get_rmon_stats()
899 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, in mt7530_get_rmon_stats()
900 &rmon_stats->hist_tx[3]); in mt7530_get_rmon_stats()
901 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, in mt7530_get_rmon_stats()
902 &rmon_stats->hist_tx[4]); in mt7530_get_rmon_stats()
903 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1, in mt7530_get_rmon_stats()
904 &rmon_stats->hist_tx[5]); in mt7530_get_rmon_stats()
909 static void mt7530_get_stats64(struct dsa_switch *ds, int port, in mt7530_get_stats64() argument
912 struct mt7530_priv *priv = ds->priv; in mt7530_get_stats64()
920 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, in mt7530_get_stats64()
921 &storage->rx_packets); in mt7530_get_stats64()
922 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, in mt7530_get_stats64()
923 &storage->multicast); in mt7530_get_stats64()
924 storage->rx_packets += storage->multicast; in mt7530_get_stats64()
925 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, in mt7530_get_stats64()
927 storage->rx_packets += data; in mt7530_get_stats64()
929 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, in mt7530_get_stats64()
930 &storage->tx_packets); in mt7530_get_stats64()
931 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, in mt7530_get_stats64()
933 storage->tx_packets += data; in mt7530_get_stats64()
934 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, in mt7530_get_stats64()
936 storage->tx_packets += data; in mt7530_get_stats64()
938 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, in mt7530_get_stats64()
939 &storage->rx_bytes); in mt7530_get_stats64()
941 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, in mt7530_get_stats64()
942 &storage->tx_bytes); in mt7530_get_stats64()
944 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, in mt7530_get_stats64()
945 &storage->rx_dropped); in mt7530_get_stats64()
947 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, in mt7530_get_stats64()
948 &storage->tx_dropped); in mt7530_get_stats64()
950 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, in mt7530_get_stats64()
951 &storage->rx_crc_errors); in mt7530_get_stats64()
954 static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port, in mt7530_get_eth_ctrl_stats() argument
957 struct mt7530_priv *priv = ds->priv; in mt7530_get_eth_ctrl_stats()
959 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, in mt7530_get_eth_ctrl_stats()
960 &ctrl_stats->MACControlFramesTransmitted); in mt7530_get_eth_ctrl_stats()
962 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, in mt7530_get_eth_ctrl_stats()
963 &ctrl_stats->MACControlFramesReceived); in mt7530_get_eth_ctrl_stats()
969 struct mt7530_priv *priv = ds->priv; in mt7530_set_ageing_time()
972 unsigned int error = -1; in mt7530_set_ageing_time()
978 return -ERANGE; in mt7530_set_ageing_time()
982 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; in mt7530_set_ageing_time()
985 unsigned int tmp_error = secs - in mt7530_set_ageing_time()
1020 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
1024 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
1030 switch (priv->p5_mode) { in mt7530_setup_port5()
1031 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ in mt7530_setup_port5()
1036 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ in mt7530_setup_port5()
1038 /* Setup the MAC by default for the cpu port */ in mt7530_setup_port5()
1042 /* GMAC5: P5 -> SoC MAC or external PHY */ in mt7530_setup_port5()
1055 /* Don't set delay in DSA mode */ in mt7530_setup_port5()
1056 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
1072 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, in mt7530_setup_port5()
1073 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); in mt7530_setup_port5()
1075 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
1078 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
1083 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
1088 * Each Bridge Port also functions as an end station and shall provide the MAC
1094 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
1095 * Entity associated with each Bridge Port is modeled as being directly
1098 * On the switch with CPU port architecture, CPU port functions as Management
1099 * Port, and the Management Port functionality is provided by software which
1102 * provides access to the LLC Entity associated with each Bridge Port by the
1103 * value of the source port field on the special tag on the frame received by
1111 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
1114 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
1116 * Each of the reserved MAC addresses specified in Table 8-1
1117 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
1118 * permanently configured in the FDB in C-VLAN components and ERs.
1120 * Each of the reserved MAC addresses specified in Table 8-2
1121 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
1122 * configured in the FDB in S-VLAN components.
1124 * Each of the reserved MAC addresses specified in Table 8-3
1125 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
1132 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
1135 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
1136 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
1137 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
1139 * that appear in Table 8-1, Table 8-2, and Table 8-3
1140 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
1144 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
1145 * address that no conformant S-VLAN component, C-VLAN component, or MAC
1148 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
1149 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
1150 * any TPMRs but will propagate no further than the nearest S-VLAN component,
1151 * C-VLAN component, or MAC Bridge.
1153 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
1154 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
1155 * relayed by TPMR components and S-VLAN components. PDUs using this
1156 * destination address, or any of the other addresses that appear in Table 8-1
1157 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
1158 * will be relayed by TPMR components and S-VLAN components but will propagate
1159 * no further than the nearest C-VLAN component or MAC Bridge.
1161 * Because the LLC Entity associated with each Bridge Port is provided via CPU
1162 * port, we must not filter these frames but forward them to CPU port.
1164 * In a Bridge, the transmission Port is majorly decided by ingress and egress
1165 * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
1166 * For link-local frames, only CPU port should be designated as destination port
1168 * interfere with the decision of the transmission Port. We call this process
1169 * trapping frames to CPU port.
1171 * Therefore, on the switch with CPU port architecture, link-local frames must
1172 * be trapped to CPU port, and certain link-local frames received by a Port of a
1173 * Bridge comprising a TPMR component or an S-VLAN component must be excluded
1176 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
1178 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
1182 * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
1183 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
1185 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
1188 * One option to trap link-local frames to CPU port is to add static FDB entries
1189 * with CPU port designated as destination port. However, because that
1192 * Bridge component or a C-VLAN component, there would have to be 16 times 4096
1195 * link-local frames from being discarded when the spanning tree Port State of
1196 * the reception Port is discarding.
1202 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
1203 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
1208 * link-local frames with specific destination addresses to CPU port by Bridge,
1211 * Therefore, regardless of the type of the Bridge component, link-local frames
1212 * with these destination addresses will be trapped to CPU port:
1214 * 01-80-C2-00-00-[00,01,02,03,0E]
1216 * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
1218 * Link-local frames with these destination addresses won't be trapped to CPU
1219 * port which won't conform to IEEE Std 802.1Q-2022:
1221 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
1223 * In a Bridge comprising an S-VLAN component:
1225 * Link-local frames with these destination addresses will be trapped to CPU
1226 * port which won't conform to IEEE Std 802.1Q-2022:
1228 * 01-80-C2-00-00-00
1230 * Link-local frames with these destination addresses won't be trapped to CPU
1231 * port which won't conform to IEEE Std 802.1Q-2022:
1233 * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
1235 * To trap link-local frames to CPU port as conformant as this switch
1236 * intellectual property can allow, link-local frames are made to be regarded as
1238 * property only lets the frames regarded as BPDUs bypass the spanning tree Port
1241 * The only remaining interference is the ingress rules. When the reception Port
1242 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
1244 * have link-local frames bypass this function of the Forwarding Process.
1249 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them in mt753x_trap_frames()
1250 * VLAN-untagged. in mt753x_trap_frames()
1260 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress in mt753x_trap_frames()
1261 * them VLAN-untagged. in mt753x_trap_frames()
1271 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress in mt753x_trap_frames()
1272 * them VLAN-untagged. in mt753x_trap_frames()
1284 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) in mt753x_cpu_port_enable() argument
1286 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
1288 /* Enable Mediatek header mode on the cpu port */ in mt753x_cpu_port_enable()
1289 mt7530_write(priv, MT7530_PVC_P(port), in mt753x_cpu_port_enable()
1292 /* Enable flooding on the CPU port */ in mt753x_cpu_port_enable()
1293 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | in mt753x_cpu_port_enable()
1294 UNU_FFP(BIT(port))); in mt753x_cpu_port_enable()
1296 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on in mt753x_cpu_port_enable()
1297 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that in mt753x_cpu_port_enable()
1298 * is affine to the inbound user port. in mt753x_cpu_port_enable()
1300 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || in mt753x_cpu_port_enable()
1301 priv->id == ID_EN7581 || priv->id == ID_AN7583) in mt753x_cpu_port_enable()
1302 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); in mt753x_cpu_port_enable()
1304 /* CPU port gets connected to all user ports of in mt753x_cpu_port_enable()
1307 mt7530_write(priv, MT7530_PCR_P(port), in mt753x_cpu_port_enable()
1308 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
1311 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt753x_cpu_port_enable()
1316 mt7530_port_enable(struct dsa_switch *ds, int port, in mt7530_port_enable() argument
1319 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_enable()
1320 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
1322 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
1324 /* Allow the user port gets connected to the cpu port and also in mt7530_port_enable()
1325 * restore the port matrix if the port is the member of a certain in mt7530_port_enable()
1329 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_enable()
1331 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_enable()
1333 priv->ports[port].enable = true; in mt7530_port_enable()
1334 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_enable()
1335 priv->ports[port].pm); in mt7530_port_enable()
1337 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1339 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt7530_port_enable()
1342 if (port == 5) in mt7530_port_enable()
1344 else if (port == 6) in mt7530_port_enable()
1351 mt7530_port_disable(struct dsa_switch *ds, int port) in mt7530_port_disable() argument
1353 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1355 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1357 /* Clear up all port matrix which could be restored in the next in mt7530_port_disable()
1358 * enablement for the port. in mt7530_port_disable()
1360 priv->ports[port].enable = false; in mt7530_port_disable()
1361 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_disable()
1364 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1366 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt7530_port_disable()
1369 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ in mt7530_port_disable()
1370 if (port == 5 && priv->p5_mode == GMAC5) in mt7530_port_disable()
1372 else if (port == 6) in mt7530_port_disable()
1377 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) in mt7530_port_change_mtu() argument
1379 struct mt7530_priv *priv = ds->priv; in mt7530_port_change_mtu()
1383 /* When a new MTU is set, DSA always set the CPU port's MTU to the in mt7530_port_change_mtu()
1385 * RX length register, only allowing CPU port here is enough. in mt7530_port_change_mtu()
1387 if (!dsa_is_cpu_port(ds, port)) in mt7530_port_change_mtu()
1417 mt7530_port_max_mtu(struct dsa_switch *ds, int port) in mt7530_port_max_mtu() argument
1423 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) in mt7530_stp_state_set() argument
1425 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1447 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), in mt7530_stp_state_set()
1451 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, in mt7530_update_port_member() argument
1453 bool join) __must_hold(&priv->reg_mutex) in mt7530_update_port_member()
1455 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; in mt7530_update_port_member()
1456 struct mt7530_port *p = &priv->ports[port], *other_p; in mt7530_update_port_member()
1457 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_update_port_member()
1458 u32 port_bitmap = BIT(cpu_dp->index); in mt7530_update_port_member()
1462 dsa_switch_for_each_user_port(other_dp, priv->ds) { in mt7530_update_port_member()
1463 other_port = other_dp->index; in mt7530_update_port_member()
1464 other_p = &priv->ports[other_port]; in mt7530_update_port_member()
1469 /* Add/remove this port to/from the port matrix of the other in mt7530_update_port_member()
1470 * ports in the same bridge. If the port is disabled, port in mt7530_update_port_member()
1471 * matrix is kept and not being setup until the port becomes in mt7530_update_port_member()
1477 isolated = p->isolated && other_p->isolated; in mt7530_update_port_member()
1480 other_p->pm |= PCR_MATRIX(BIT(port)); in mt7530_update_port_member()
1483 other_p->pm &= ~PCR_MATRIX(BIT(port)); in mt7530_update_port_member()
1486 if (other_p->enable) in mt7530_update_port_member()
1488 PCR_MATRIX_MASK, other_p->pm); in mt7530_update_port_member()
1491 /* Add/remove the all other ports to this port matrix. For !join in mt7530_update_port_member()
1492 * (leaving the bridge), only the CPU port will remain in the port matrix in mt7530_update_port_member()
1493 * of this port. in mt7530_update_port_member()
1495 p->pm = PCR_MATRIX(port_bitmap); in mt7530_update_port_member()
1496 if (priv->ports[port].enable) in mt7530_update_port_member()
1497 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); in mt7530_update_port_member()
1501 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, in mt7530_port_pre_bridge_flags() argument
1507 return -EINVAL; in mt7530_port_pre_bridge_flags()
1513 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, in mt7530_port_bridge_flags() argument
1517 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_flags()
1520 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, in mt7530_port_bridge_flags()
1524 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), in mt7530_port_bridge_flags()
1525 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1528 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), in mt7530_port_bridge_flags()
1529 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1532 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), in mt7530_port_bridge_flags()
1533 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1536 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_bridge_flags()
1539 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); in mt7530_port_bridge_flags()
1541 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_flags()
1542 mt7530_update_port_member(priv, port, bridge_dev, true); in mt7530_port_bridge_flags()
1543 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_flags()
1550 mt7530_port_bridge_join(struct dsa_switch *ds, int port, in mt7530_port_bridge_join() argument
1554 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1556 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1558 mt7530_update_port_member(priv, port, bridge.dev, true); in mt7530_port_bridge_join()
1561 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_bridge_join()
1564 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1570 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_unaware() argument
1572 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1576 /* This is called after .port_bridge_leave when leaving a VLAN-aware in mt7530_port_set_vlan_unaware()
1579 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) in mt7530_port_set_vlan_unaware()
1580 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_unaware()
1583 mt7530_rmw(priv, MT7530_PVC_P(port), in mt7530_port_set_vlan_unaware()
1590 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_set_vlan_unaware()
1593 for (i = 0; i < priv->ds->num_ports; i++) { in mt7530_port_set_vlan_unaware()
1601 /* CPU port also does the same thing until all user ports belonging to in mt7530_port_set_vlan_unaware()
1602 * the CPU port get out of VLAN filtering mode. in mt7530_port_set_vlan_unaware()
1605 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_set_vlan_unaware()
1606 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_set_vlan_unaware()
1608 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), in mt7530_port_set_vlan_unaware()
1609 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1610 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG in mt7530_port_set_vlan_unaware()
1616 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_aware() argument
1618 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1623 if (dsa_is_user_port(ds, port)) { in mt7530_port_set_vlan_aware()
1624 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_aware()
1626 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_set_vlan_aware()
1627 G0_PORT_VID(priv->ports[port].pvid)); in mt7530_port_set_vlan_aware()
1630 if (!priv->ports[port].pvid) in mt7530_port_set_vlan_aware()
1631 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_set_vlan_aware()
1634 /* Set the port as a user port which is to be able to recognize in mt7530_port_set_vlan_aware()
1638 mt7530_rmw(priv, MT7530_PVC_P(port), in mt7530_port_set_vlan_aware()
1643 /* Also set CPU ports to the "user" VLAN port attribute, to in mt7530_port_set_vlan_aware()
1650 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, in mt7530_port_set_vlan_aware()
1656 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, in mt7530_port_bridge_leave() argument
1659 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1661 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1663 mt7530_update_port_member(priv, port, bridge.dev, false); in mt7530_port_bridge_leave()
1665 /* When a port is removed from the bridge, the port would be set up in mt7530_port_bridge_leave()
1666 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_bridge_leave()
1667 * port. in mt7530_port_bridge_leave()
1669 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_bridge_leave()
1672 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1676 mt7530_port_fdb_add(struct dsa_switch *ds, int port, in mt7530_port_fdb_add() argument
1680 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1682 u8 port_mask = BIT(port); in mt7530_port_fdb_add()
1684 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1685 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1687 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1693 mt7530_port_fdb_del(struct dsa_switch *ds, int port, in mt7530_port_fdb_del() argument
1697 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1699 u8 port_mask = BIT(port); in mt7530_port_fdb_del()
1701 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1702 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1704 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1710 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, in mt7530_port_fdb_dump() argument
1713 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1719 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1728 if (_fdb.port_mask & BIT(port)) { in mt7530_port_fdb_dump()
1735 } while (--cnt && in mt7530_port_fdb_dump()
1739 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1745 mt7530_port_mdb_add(struct dsa_switch *ds, int port, in mt7530_port_mdb_add() argument
1749 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_add()
1750 const u8 *addr = mdb->addr; in mt7530_port_mdb_add()
1751 u16 vid = mdb->vid; in mt7530_port_mdb_add()
1755 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_add()
1762 port_mask |= BIT(port); in mt7530_port_mdb_add()
1763 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_mdb_add()
1766 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_add()
1772 mt7530_port_mdb_del(struct dsa_switch *ds, int port, in mt7530_port_mdb_del() argument
1776 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_del()
1777 const u8 *addr = mdb->addr; in mt7530_port_mdb_del()
1778 u16 vid = mdb->vid; in mt7530_port_mdb_del()
1782 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_del()
1789 port_mask &= ~BIT(port); in mt7530_port_mdb_del()
1790 mt7530_fdb_write(priv, vid, port_mask, addr, -1, in mt7530_port_mdb_del()
1794 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_del()
1813 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1819 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1820 return -EINVAL; in mt7530_vlan_cmd()
1827 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, in mt7530_port_vlan_filtering() argument
1830 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_vlan_filtering()
1831 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_vlan_filtering()
1834 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1836 * port and the corresponding CPU port is required the setup in mt7530_port_vlan_filtering()
1837 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1839 mt7530_port_set_vlan_aware(ds, port); in mt7530_port_vlan_filtering()
1840 mt7530_port_set_vlan_aware(ds, cpu_dp->index); in mt7530_port_vlan_filtering()
1842 mt7530_port_set_vlan_unaware(ds, port); in mt7530_port_vlan_filtering()
1852 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); in mt7530_hw_vlan_add()
1856 new_members = entry->old_members | BIT(entry->port); in mt7530_hw_vlan_add()
1859 * VLAN and joining the port as one of the port members. in mt7530_hw_vlan_add()
1866 * port inside the VLAN. in mt7530_hw_vlan_add()
1867 * CPU port is always taken as a tagged port for serving more than one in mt7530_hw_vlan_add()
1870 * DSA tag. in mt7530_hw_vlan_add()
1874 else if (entry->untagged) in mt7530_hw_vlan_add()
1879 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1880 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1890 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1894 dev_err(priv->dev, in mt7530_hw_vlan_del()
1921 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1946 mt7530_port_vlan_add(struct dsa_switch *ds, int port, in mt7530_port_vlan_add() argument
1950 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1951 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1953 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1955 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1957 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); in mt7530_port_vlan_add()
1958 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); in mt7530_port_vlan_add()
1961 priv->ports[port].pvid = vlan->vid; in mt7530_port_vlan_add()
1964 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_add()
1968 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_add()
1969 mt7530_rmw(priv, MT7530_PPBV1_P(port), in mt7530_port_vlan_add()
1971 G0_PORT_VID(vlan->vid)); in mt7530_port_vlan_add()
1972 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_add()
1974 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_add()
1976 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_add()
1977 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_add()
1978 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_add()
1981 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_vlan_add()
1985 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1991 mt7530_port_vlan_del(struct dsa_switch *ds, int port, in mt7530_port_vlan_del() argument
1995 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1997 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1999 mt7530_hw_vlan_entry_init(&target_entry, port, 0); in mt7530_port_vlan_del()
2000 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, in mt7530_port_vlan_del()
2003 /* PVID is being restored to the default whenever the PVID port in mt7530_port_vlan_del()
2006 if (priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_del()
2007 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_del()
2009 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_del()
2010 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_del()
2011 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_del()
2014 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_vlan_del()
2019 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
2024 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, in mt753x_port_mirror_add() argument
2028 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
2033 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
2034 return -EEXIST; in mt753x_port_mirror_add()
2036 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
2038 /* MT7530 only supports one monitor port */ in mt753x_port_mirror_add()
2039 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); in mt753x_port_mirror_add()
2040 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
2041 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
2042 return -EEXIST; in mt753x_port_mirror_add()
2044 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
2045 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); in mt753x_port_mirror_add()
2046 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
2047 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
2049 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_add()
2052 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
2055 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
2057 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_add()
2062 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, in mt753x_port_mirror_del() argument
2065 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
2068 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_del()
2069 if (mirror->ingress) { in mt753x_port_mirror_del()
2071 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
2074 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
2076 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_del()
2078 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
2079 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
2080 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
2081 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
2086 mtk_get_tag_protocol(struct dsa_switch *ds, int port, in mtk_get_tag_protocol() argument
2097 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 in mt7530_gpio_to_bit()
2098 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 in mt7530_gpio_to_bit()
2099 * [10: 8] port 2 LED 0..2 as GPIO 6..8 in mt7530_gpio_to_bit()
2100 * [14:12] port 3 LED 0..2 as GPIO 9..11 in mt7530_gpio_to_bit()
2101 * [18:16] port 4 LED 0..2 as GPIO 12..14 in mt7530_gpio_to_bit()
2172 struct device *dev = priv->dev; in mt7530_setup_gpio()
2177 return -ENOMEM; in mt7530_setup_gpio()
2183 gc->label = "mt7530"; in mt7530_setup_gpio()
2184 gc->parent = dev; in mt7530_setup_gpio()
2185 gc->owner = THIS_MODULE; in mt7530_setup_gpio()
2186 gc->get_direction = mt7530_gpio_get_direction; in mt7530_setup_gpio()
2187 gc->direction_input = mt7530_gpio_direction_input; in mt7530_setup_gpio()
2188 gc->direction_output = mt7530_gpio_direction_output; in mt7530_setup_gpio()
2189 gc->get = mt7530_gpio_get; in mt7530_setup_gpio()
2190 gc->set = mt7530_gpio_set; in mt7530_setup_gpio()
2191 gc->base = -1; in mt7530_setup_gpio()
2192 gc->ngpio = 15; in mt7530_setup_gpio()
2193 gc->can_sleep = true; in mt7530_setup_gpio()
2202 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio_irq()
2206 if (BIT(p) & ds->phys_mii_mask) { in mt7530_setup_mdio_irq()
2209 irq = irq_create_mapping(priv->irq_domain, p); in mt7530_setup_mdio_irq()
2210 ds->user_mii_bus->irq[p] = irq; in mt7530_setup_mdio_irq()
2253 struct device *dev = priv->dev; in mt7530_setup_irq()
2254 struct device_node *np = dev->of_node; in mt7530_setup_irq()
2257 if (!of_property_read_bool(np, "interrupt-controller")) { in mt7530_setup_irq()
2265 return irq ? : -EINVAL; in mt7530_setup_irq()
2269 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) in mt7530_setup_irq()
2273 priv->regmap, irq, in mt7530_setup_irq()
2280 priv->irq_domain = regmap_irq_get_domain(irq_data); in mt7530_setup_irq()
2291 if (BIT(p) & priv->ds->phys_mii_mask) { in mt7530_free_mdio_irq()
2294 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_free_mdio_irq()
2303 struct device_node *mnp, *np = priv->dev->of_node; in mt7530_setup_mdio()
2304 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio()
2305 struct device *dev = priv->dev; in mt7530_setup_mdio()
2317 ret = -ENOMEM; in mt7530_setup_mdio()
2322 ds->user_mii_bus = bus; in mt7530_setup_mdio()
2324 bus->priv = priv; in mt7530_setup_mdio()
2325 bus->name = KBUILD_MODNAME "-mii"; in mt7530_setup_mdio()
2326 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); in mt7530_setup_mdio()
2327 bus->read = mt753x_phy_read_c22; in mt7530_setup_mdio()
2328 bus->write = mt753x_phy_write_c22; in mt7530_setup_mdio()
2329 bus->read_c45 = mt753x_phy_read_c45; in mt7530_setup_mdio()
2330 bus->write_c45 = mt753x_phy_write_c45; in mt7530_setup_mdio()
2331 bus->parent = dev; in mt7530_setup_mdio()
2332 bus->phy_mask = ~ds->phys_mii_mask; in mt7530_setup_mdio()
2334 if (priv->irq_domain && !mnp) in mt7530_setup_mdio()
2340 if (priv->irq_domain && !mnp) in mt7530_setup_mdio()
2352 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
2367 dn = cpu_dp->conduit->dev.of_node->parent; in mt7530_setup()
2368 /* It doesn't matter which CPU port is found first, in mt7530_setup()
2375 dev_err(ds->dev, "parent OF node of DSA conduit not found"); in mt7530_setup()
2376 return -EINVAL; in mt7530_setup()
2379 ds->assisted_learning_on_cpu_port = true; in mt7530_setup()
2380 ds->mtu_enforcement_ingress = true; in mt7530_setup()
2382 if (priv->id == ID_MT7530) { in mt7530_setup()
2383 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
2384 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
2386 dev_err(priv->dev, in mt7530_setup()
2391 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
2392 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
2394 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
2400 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
2403 if (priv->mcm) { in mt7530_setup()
2404 reset_control_assert(priv->rstc); in mt7530_setup()
2406 reset_control_deassert(priv->rstc); in mt7530_setup()
2408 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
2410 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
2418 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
2425 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
2426 return -ENODEV; in mt7530_setup()
2430 dev_err(priv->dev, in mt7530_setup()
2432 return -EINVAL; in mt7530_setup()
2463 for (i = 0; i < priv->ds->num_ports; i++) { in mt7530_setup()
2469 MT753X_FORCE_MODE(priv->id), in mt7530_setup()
2470 MT753X_FORCE_MODE(priv->id)); in mt7530_setup()
2493 /* Allow mirroring frames received on the local port (monitor port). */ in mt7530_setup()
2496 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7530_setup()
2501 /* Check for PHY muxing on port 5 */ in mt7530_setup()
2504 * Set priv->p5_mode to the appropriate value if PHY muxing is in mt7530_setup()
2509 "mediatek,eth-mac")) in mt7530_setup()
2516 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
2520 if (phy_node->parent == priv->dev->of_node->parent || in mt7530_setup()
2521 phy_node->parent->parent == priv->dev->of_node) { in mt7530_setup()
2523 if (ret && ret != -ENODEV) { in mt7530_setup()
2528 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
2530 priv->p5_mode = MUX_PHY_P0; in mt7530_setup()
2532 priv->p5_mode = MUX_PHY_P4; in mt7530_setup()
2539 if (priv->p5_mode == MUX_PHY_P0 || in mt7530_setup()
2540 priv->p5_mode == MUX_PHY_P4) { in mt7530_setup()
2547 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { in mt7530_setup()
2565 struct mt7530_priv *priv = ds->priv; in mt7531_setup_common()
2568 ds->assisted_learning_on_cpu_port = true; in mt7531_setup_common()
2569 ds->mtu_enforcement_ingress = true; in mt7531_setup_common()
2580 for (i = 0; i < priv->ds->num_ports; i++) { in mt7531_setup_common()
2586 MT753X_FORCE_MODE(priv->id), in mt7531_setup_common()
2587 MT753X_FORCE_MODE(priv->id)); in mt7531_setup_common()
2613 /* Allow mirroring frames received on the local port (monitor port). */ in mt7531_setup_common()
2617 if (priv->id == ID_EN7581 || priv->id == ID_AN7583) in mt7531_setup_common()
2626 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7531_setup_common()
2633 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
2638 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
2641 if (priv->mcm) { in mt7531_setup()
2642 reset_control_assert(priv->rstc); in mt7531_setup()
2644 reset_control_deassert(priv->rstc); in mt7531_setup()
2646 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
2648 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
2656 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
2664 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
2665 return -ENODEV; in mt7531_setup()
2668 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. in mt7531_setup()
2669 * MT7531BE has got only one SGMII unit which is for port 6. in mt7531_setup()
2672 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); in mt7531_setup()
2675 for (i = 0; i < priv->ds->num_ports; i++) in mt7531_setup()
2681 if (!priv->p5_sgmii) { in mt7531_setup()
2684 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on in mt7531_setup()
2685 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO in mt7531_setup()
2697 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since in mt7531_setup()
2703 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in mt7531_setup()
2708 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in mt7531_setup()
2712 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); in mt7531_setup()
2713 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; in mt7531_setup()
2726 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7530_mac_port_get_caps() argument
2729 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7530_mac_port_get_caps()
2731 switch (port) { in mt7530_mac_port_get_caps()
2735 config->supported_interfaces); in mt7530_mac_port_get_caps()
2738 /* Port 5 supports rgmii with delays, mii, and gmii. */ in mt7530_mac_port_get_caps()
2740 phy_interface_set_rgmii(config->supported_interfaces); in mt7530_mac_port_get_caps()
2742 config->supported_interfaces); in mt7530_mac_port_get_caps()
2744 config->supported_interfaces); in mt7530_mac_port_get_caps()
2747 /* Port 6 supports rgmii and trgmii. */ in mt7530_mac_port_get_caps()
2750 config->supported_interfaces); in mt7530_mac_port_get_caps()
2752 config->supported_interfaces); in mt7530_mac_port_get_caps()
2757 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7531_mac_port_get_caps() argument
2760 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_get_caps()
2762 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7531_mac_port_get_caps()
2764 switch (port) { in mt7531_mac_port_get_caps()
2768 config->supported_interfaces); in mt7531_mac_port_get_caps()
2771 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on in mt7531_mac_port_get_caps()
2775 if (!priv->p5_sgmii) { in mt7531_mac_port_get_caps()
2776 phy_interface_set_rgmii(config->supported_interfaces); in mt7531_mac_port_get_caps()
2781 /* Port 6 supports sgmii/802.3z. */ in mt7531_mac_port_get_caps()
2784 config->supported_interfaces); in mt7531_mac_port_get_caps()
2786 config->supported_interfaces); in mt7531_mac_port_get_caps()
2788 config->supported_interfaces); in mt7531_mac_port_get_caps()
2790 config->mac_capabilities |= MAC_2500FD; in mt7531_mac_port_get_caps()
2795 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7988_mac_port_get_caps() argument
2798 switch (port) { in mt7988_mac_port_get_caps()
2802 config->supported_interfaces); in mt7988_mac_port_get_caps()
2804 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7988_mac_port_get_caps()
2807 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ in mt7988_mac_port_get_caps()
2810 config->supported_interfaces); in mt7988_mac_port_get_caps()
2812 config->mac_capabilities |= MAC_10000FD; in mt7988_mac_port_get_caps()
2817 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, in en7581_mac_port_get_caps() argument
2820 switch (port) { in en7581_mac_port_get_caps()
2824 config->supported_interfaces); in en7581_mac_port_get_caps()
2826 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in en7581_mac_port_get_caps()
2829 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ in en7581_mac_port_get_caps()
2832 config->supported_interfaces); in en7581_mac_port_get_caps()
2834 config->mac_capabilities |= MAC_10000FD; in en7581_mac_port_get_caps()
2840 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7530_mac_config() argument
2843 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
2845 if (port == 5) in mt7530_mac_config()
2846 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
2847 else if (port == 6) in mt7530_mac_config()
2848 mt7530_setup_port6(priv->ds, interface); in mt7530_mac_config()
2892 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7531_mac_config() argument
2895 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2900 dp = dsa_to_port(ds, port); in mt7531_mac_config()
2901 phydev = dp->user->phydev; in mt7531_mac_config()
2911 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_select_pcs()
2915 return &priv->pcs[dp->index].pcs; in mt753x_phylink_mac_select_pcs()
2919 return priv->ports[dp->index].sgmii_pcs; in mt753x_phylink_mac_select_pcs()
2930 struct dsa_switch *ds = dp->ds; in mt753x_phylink_mac_config()
2932 int port = dp->index; in mt753x_phylink_mac_config() local
2934 priv = ds->priv; in mt753x_phylink_mac_config()
2936 if ((port == 5 || port == 6) && priv->info->mac_port_config) in mt753x_phylink_mac_config()
2937 priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_phylink_mac_config()
2940 if (port == 5 && dsa_is_user_port(ds, 5)) in mt753x_phylink_mac_config()
2941 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); in mt753x_phylink_mac_config()
2949 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_link_down()
2951 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); in mt753x_phylink_mac_link_down()
2962 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_link_up()
2985 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); in mt753x_phylink_mac_link_up()
2991 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_disable_tx_lpi()
2993 mt7530_clear(priv, MT753X_PMCR_P(dp->index), in mt753x_phylink_mac_disable_tx_lpi()
3001 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_enable_tx_lpi()
3015 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), in mt753x_phylink_mac_enable_tx_lpi()
3018 mt7530_set(priv, MT753X_PMCR_P(dp->index), in mt753x_phylink_mac_enable_tx_lpi()
3024 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, in mt753x_phylink_get_caps() argument
3027 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_get_caps()
3030 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; in mt753x_phylink_get_caps()
3032 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; in mt753x_phylink_get_caps()
3034 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); in mt753x_phylink_get_caps()
3038 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); in mt753x_phylink_get_caps()
3040 priv->info->mac_port_get_caps(ds, port, config); in mt753x_phylink_get_caps()
3048 if (state->interface == PHY_INTERFACE_MODE_TRGMII || in mt753x_pcs_validate()
3049 phy_interface_mode_is_8023z(state->interface)) in mt753x_pcs_validate()
3058 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; in mt7530_pcs_get_state()
3059 int port = pcs_to_mt753x_pcs(pcs)->port; in mt7530_pcs_get_state() local
3062 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); in mt7530_pcs_get_state()
3064 state->link = (pmsr & PMSR_LINK); in mt7530_pcs_get_state()
3065 state->an_complete = state->link; in mt7530_pcs_get_state()
3066 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_pcs_get_state()
3070 state->speed = SPEED_10; in mt7530_pcs_get_state()
3073 state->speed = SPEED_100; in mt7530_pcs_get_state()
3076 state->speed = SPEED_1000; in mt7530_pcs_get_state()
3079 state->speed = SPEED_UNKNOWN; in mt7530_pcs_get_state()
3083 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_pcs_get_state()
3085 state->pause |= MLO_PAUSE_RX; in mt7530_pcs_get_state()
3087 state->pause |= MLO_PAUSE_TX; in mt7530_pcs_get_state()
3112 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
3113 int ret = priv->info->sw_setup(ds); in mt753x_setup()
3128 for (i = 0; i < priv->ds->num_ports; i++) { in mt753x_setup()
3129 priv->pcs[i].pcs.ops = priv->info->pcs_ops; in mt753x_setup()
3130 priv->pcs[i].priv = priv; in mt753x_setup()
3131 priv->pcs[i].port = i; in mt753x_setup()
3134 if (priv->create_sgmii) in mt753x_setup()
3135 ret = priv->create_sgmii(priv); in mt753x_setup()
3137 if (ret && priv->irq_domain) in mt753x_setup()
3143 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, in mt753x_set_mac_eee() argument
3146 if (e->tx_lpi_timer > 0xFFF) in mt753x_set_mac_eee()
3147 return -EINVAL; in mt753x_set_mac_eee()
3157 struct dsa_port *cpu_dp = conduit->dsa_ptr; in mt753x_conduit_state_change()
3158 struct mt7530_priv *priv = ds->priv; in mt753x_conduit_state_change()
3162 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be in mt753x_conduit_state_change()
3163 * forwarded to the numerically smallest CPU port whose conduit in mt753x_conduit_state_change()
3166 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt753x_conduit_state_change()
3169 mask = BIT(cpu_dp->index); in mt753x_conduit_state_change()
3172 priv->active_cpu_ports |= mask; in mt753x_conduit_state_change()
3174 priv->active_cpu_ports &= ~mask; in mt753x_conduit_state_change()
3176 if (priv->active_cpu_ports) { in mt753x_conduit_state_change()
3178 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); in mt753x_conduit_state_change()
3184 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, in mt753x_tc_setup_qdisc_tbf() argument
3187 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; in mt753x_tc_setup_qdisc_tbf()
3188 struct mt7530_priv *priv = ds->priv; in mt753x_tc_setup_qdisc_tbf()
3191 switch (qopt->command) { in mt753x_tc_setup_qdisc_tbf()
3193 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ in mt753x_tc_setup_qdisc_tbf()
3210 mt7530_write(priv, MT753X_ERLCR_P(port), val); in mt753x_tc_setup_qdisc_tbf()
3214 return -EOPNOTSUPP; in mt753x_tc_setup_qdisc_tbf()
3220 static int mt753x_setup_tc(struct dsa_switch *ds, int port, in mt753x_setup_tc() argument
3225 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); in mt753x_setup_tc()
3227 return -EOPNOTSUPP; in mt753x_setup_tc()
3233 struct mt7530_priv *priv = ds->priv; in mt7988_setup()
3236 reset_control_assert(priv->rstc); in mt7988_setup()
3238 reset_control_deassert(priv->rstc); in mt7988_setup()
3242 if (priv->id == ID_AN7583) in mt7988_setup()
3375 struct device *dev = priv->dev; in mt7530_probe_common()
3377 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe_common()
3378 if (!priv->ds) in mt7530_probe_common()
3379 return -ENOMEM; in mt7530_probe_common()
3381 priv->ds->dev = dev; in mt7530_probe_common()
3382 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe_common()
3387 priv->info = of_device_get_match_data(dev); in mt7530_probe_common()
3388 if (!priv->info) in mt7530_probe_common()
3389 return -EINVAL; in mt7530_probe_common()
3391 priv->id = priv->info->id; in mt7530_probe_common()
3392 priv->dev = dev; in mt7530_probe_common()
3393 priv->ds->priv = priv; in mt7530_probe_common()
3394 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe_common()
3395 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; in mt7530_probe_common()
3396 mutex_init(&priv->reg_mutex); in mt7530_probe_common()
3406 if (priv->irq_domain) in mt7530_remove_common()
3409 dsa_unregister_switch(priv->ds); in mt7530_remove_common()
3411 mutex_destroy(&priv->reg_mutex); in mt7530_remove_common()