Lines Matching +full:mt7530 +full:- +full:dsa +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mediatek MT7530 DSA Switch driver
23 #include <net/dsa.h>
26 #include "mt7530.h"
81 if (priv->bus) in mt7530_mutex_lock()
82 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
88 if (priv->bus) in mt7530_mutex_unlock()
89 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
95 struct mii_bus *bus = priv->bus; in core_write()
101 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
107 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
113 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
119 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
123 dev_err(&bus->dev, "failed to write mmd register\n"); in core_write()
131 struct mii_bus *bus = priv->bus; in core_rmw()
138 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
144 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
150 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
156 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
161 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
165 dev_err(&bus->dev, "failed to write mmd register\n"); in core_rmw()
187 ret = regmap_write(priv->regmap, reg, val); in mt7530_mii_write()
190 dev_err(priv->dev, in mt7530_mii_write()
191 "failed to write mt7530 register\n"); in mt7530_mii_write()
202 ret = regmap_read(priv->regmap, reg, &val); in mt7530_mii_read()
205 dev_err(priv->dev, in mt7530_mii_read()
206 "failed to read mt7530 register\n"); in mt7530_mii_read()
226 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
234 mt7530_mutex_lock(p->priv); in _mt7530_read()
236 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
238 mt7530_mutex_unlock(p->priv); in _mt7530_read()
258 regmap_update_bits(priv->regmap, reg, mask, set); in mt7530_rmw()
290 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
299 return -EINVAL; in mt7530_fdb_cmd()
317 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
321 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
322 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
323 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
324 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
325 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
326 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
327 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
328 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
329 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
330 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
363 /* Set up switch core clock for MT7530 */
389 /* If port 6 is available as a CPU port, always prefer that as the default,
403 /* Setup port 6 interface mode and TRGMII TX circuit */
407 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port6()
410 /* Disable the MT7530 TRGMII clocks */ in mt7530_setup_port6()
428 if (priv->id == ID_MT7621) { in mt7530_setup_port6()
441 /* Setup the MT7530 TRGMII Tx Clock */ in mt7530_setup_port6()
453 /* Enable the MT7530 TRGMII clocks */ in mt7530_setup_port6()
548 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
554 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) in mt7530_phy_read_c22() argument
556 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read_c22()
559 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, in mt7530_phy_write_c22() argument
562 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write_c22()
565 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, in mt7530_phy_read_c45() argument
568 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); in mt7530_phy_read_c45()
571 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, in mt7530_phy_write_c45() argument
574 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); in mt7530_phy_write_c45()
578 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_read() argument
592 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
596 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
603 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
607 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
614 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
626 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_write() argument
640 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
644 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
651 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
655 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
662 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
673 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) in mt7531_ind_c22_phy_read() argument
686 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
690 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_read()
698 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
710 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, in mt7531_ind_c22_phy_write() argument
724 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
728 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_write()
736 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
747 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) in mt753x_phy_read_c22() argument
749 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c22()
751 return priv->info->phy_read_c22(priv, port, regnum); in mt753x_phy_read_c22()
755 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) in mt753x_phy_read_c45() argument
757 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c45()
759 return priv->info->phy_read_c45(priv, port, devad, regnum); in mt753x_phy_read_c45()
763 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) in mt753x_phy_write_c22() argument
765 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c22()
767 return priv->info->phy_write_c22(priv, port, regnum, val); in mt753x_phy_write_c22()
771 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, in mt753x_phy_write_c45() argument
774 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c45()
776 return priv->info->phy_write_c45(priv, port, devad, regnum, val); in mt753x_phy_write_c45()
780 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, in mt7530_get_strings() argument
793 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, in mt7530_get_ethtool_stats() argument
796 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
803 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
806 if (mib->size == 2) { in mt7530_get_ethtool_stats()
814 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) in mt7530_get_sset_count() argument
825 struct mt7530_priv *priv = ds->priv; in mt7530_set_ageing_time()
828 unsigned int error = -1; in mt7530_set_ageing_time()
834 return -ERANGE; in mt7530_set_ageing_time()
838 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; in mt7530_set_ageing_time()
841 unsigned int tmp_error = secs - in mt7530_set_ageing_time()
876 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
880 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
886 switch (priv->p5_mode) { in mt7530_setup_port5()
887 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ in mt7530_setup_port5()
892 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ in mt7530_setup_port5()
894 /* Setup the MAC by default for the cpu port */ in mt7530_setup_port5()
898 /* GMAC5: P5 -> SoC MAC or external PHY */ in mt7530_setup_port5()
911 /* Don't set delay in DSA mode */ in mt7530_setup_port5()
912 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
928 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, in mt7530_setup_port5()
929 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); in mt7530_setup_port5()
931 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
934 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
939 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
944 * Each Bridge Port also functions as an end station and shall provide the MAC
950 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
951 * Entity associated with each Bridge Port is modeled as being directly
954 * On the switch with CPU port architecture, CPU port functions as Management
955 * Port, and the Management Port functionality is provided by software which
958 * provides access to the LLC Entity associated with each Bridge Port by the
959 * value of the source port field on the special tag on the frame received by
967 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
970 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
972 * Each of the reserved MAC addresses specified in Table 8-1
973 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
974 * permanently configured in the FDB in C-VLAN components and ERs.
976 * Each of the reserved MAC addresses specified in Table 8-2
977 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
978 * configured in the FDB in S-VLAN components.
980 * Each of the reserved MAC addresses specified in Table 8-3
981 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
988 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
991 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
992 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
993 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
995 * that appear in Table 8-1, Table 8-2, and Table 8-3
996 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
1000 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
1001 * address that no conformant S-VLAN component, C-VLAN component, or MAC
1004 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
1005 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
1006 * any TPMRs but will propagate no further than the nearest S-VLAN component,
1007 * C-VLAN component, or MAC Bridge.
1009 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
1010 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
1011 * relayed by TPMR components and S-VLAN components. PDUs using this
1012 * destination address, or any of the other addresses that appear in Table 8-1
1013 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
1014 * will be relayed by TPMR components and S-VLAN components but will propagate
1015 * no further than the nearest C-VLAN component or MAC Bridge.
1017 * Because the LLC Entity associated with each Bridge Port is provided via CPU
1018 * port, we must not filter these frames but forward them to CPU port.
1020 * In a Bridge, the transmission Port is majorly decided by ingress and egress
1021 * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
1022 * For link-local frames, only CPU port should be designated as destination port
1024 * interfere with the decision of the transmission Port. We call this process
1025 * trapping frames to CPU port.
1027 * Therefore, on the switch with CPU port architecture, link-local frames must
1028 * be trapped to CPU port, and certain link-local frames received by a Port of a
1029 * Bridge comprising a TPMR component or an S-VLAN component must be excluded
1032 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
1034 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
1038 * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
1039 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
1041 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
1044 * One option to trap link-local frames to CPU port is to add static FDB entries
1045 * with CPU port designated as destination port. However, because that
1048 * Bridge component or a C-VLAN component, there would have to be 16 times 4096
1051 * link-local frames from being discarded when the spanning tree Port State of
1052 * the reception Port is discarding.
1058 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
1059 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
1064 * link-local frames with specific destination addresses to CPU port by Bridge,
1067 * Therefore, regardless of the type of the Bridge component, link-local frames
1068 * with these destination addresses will be trapped to CPU port:
1070 * 01-80-C2-00-00-[00,01,02,03,0E]
1072 * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
1074 * Link-local frames with these destination addresses won't be trapped to CPU
1075 * port which won't conform to IEEE Std 802.1Q-2022:
1077 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
1079 * In a Bridge comprising an S-VLAN component:
1081 * Link-local frames with these destination addresses will be trapped to CPU
1082 * port which won't conform to IEEE Std 802.1Q-2022:
1084 * 01-80-C2-00-00-00
1086 * Link-local frames with these destination addresses won't be trapped to CPU
1087 * port which won't conform to IEEE Std 802.1Q-2022:
1089 * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
1091 * To trap link-local frames to CPU port as conformant as this switch
1092 * intellectual property can allow, link-local frames are made to be regarded as
1094 * property only lets the frames regarded as BPDUs bypass the spanning tree Port
1097 * The only remaining interference is the ingress rules. When the reception Port
1098 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
1100 * have link-local frames bypass this function of the Forwarding Process.
1105 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them in mt753x_trap_frames()
1106 * VLAN-untagged. in mt753x_trap_frames()
1116 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress in mt753x_trap_frames()
1117 * them VLAN-untagged. in mt753x_trap_frames()
1127 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress in mt753x_trap_frames()
1128 * them VLAN-untagged. in mt753x_trap_frames()
1140 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) in mt753x_cpu_port_enable() argument
1142 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
1144 /* Enable Mediatek header mode on the cpu port */ in mt753x_cpu_port_enable()
1145 mt7530_write(priv, MT7530_PVC_P(port), in mt753x_cpu_port_enable()
1148 /* Enable flooding on the CPU port */ in mt753x_cpu_port_enable()
1149 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | in mt753x_cpu_port_enable()
1150 UNU_FFP(BIT(port))); in mt753x_cpu_port_enable()
1152 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on in mt753x_cpu_port_enable()
1153 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that in mt753x_cpu_port_enable()
1154 * is affine to the inbound user port. in mt753x_cpu_port_enable()
1156 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || in mt753x_cpu_port_enable()
1157 priv->id == ID_EN7581) in mt753x_cpu_port_enable()
1158 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); in mt753x_cpu_port_enable()
1160 /* CPU port gets connected to all user ports of in mt753x_cpu_port_enable()
1163 mt7530_write(priv, MT7530_PCR_P(port), in mt753x_cpu_port_enable()
1164 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
1167 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt753x_cpu_port_enable()
1172 mt7530_port_enable(struct dsa_switch *ds, int port, in mt7530_port_enable() argument
1175 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_enable()
1176 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
1178 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
1180 /* Allow the user port gets connected to the cpu port and also in mt7530_port_enable()
1181 * restore the port matrix if the port is the member of a certain in mt7530_port_enable()
1185 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_enable()
1187 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_enable()
1189 priv->ports[port].enable = true; in mt7530_port_enable()
1190 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_enable()
1191 priv->ports[port].pm); in mt7530_port_enable()
1193 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1195 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt7530_port_enable()
1198 if (port == 5) in mt7530_port_enable()
1200 else if (port == 6) in mt7530_port_enable()
1207 mt7530_port_disable(struct dsa_switch *ds, int port) in mt7530_port_disable() argument
1209 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1211 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1213 /* Clear up all port matrix which could be restored in the next in mt7530_port_disable()
1214 * enablement for the port. in mt7530_port_disable()
1216 priv->ports[port].enable = false; in mt7530_port_disable()
1217 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_disable()
1220 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1222 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt7530_port_disable()
1225 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ in mt7530_port_disable()
1226 if (port == 5 && priv->p5_mode == GMAC5) in mt7530_port_disable()
1228 else if (port == 6) in mt7530_port_disable()
1233 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) in mt7530_port_change_mtu() argument
1235 struct mt7530_priv *priv = ds->priv; in mt7530_port_change_mtu()
1239 /* When a new MTU is set, DSA always set the CPU port's MTU to the in mt7530_port_change_mtu()
1241 * RX length register, only allowing CPU port here is enough. in mt7530_port_change_mtu()
1243 if (!dsa_is_cpu_port(ds, port)) in mt7530_port_change_mtu()
1273 mt7530_port_max_mtu(struct dsa_switch *ds, int port) in mt7530_port_max_mtu() argument
1279 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) in mt7530_stp_state_set() argument
1281 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1303 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), in mt7530_stp_state_set()
1307 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, in mt7530_update_port_member() argument
1309 bool join) __must_hold(&priv->reg_mutex) in mt7530_update_port_member()
1311 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; in mt7530_update_port_member()
1312 struct mt7530_port *p = &priv->ports[port], *other_p; in mt7530_update_port_member()
1313 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_update_port_member()
1314 u32 port_bitmap = BIT(cpu_dp->index); in mt7530_update_port_member()
1318 dsa_switch_for_each_user_port(other_dp, priv->ds) { in mt7530_update_port_member()
1319 other_port = other_dp->index; in mt7530_update_port_member()
1320 other_p = &priv->ports[other_port]; in mt7530_update_port_member()
1325 /* Add/remove this port to/from the port matrix of the other in mt7530_update_port_member()
1326 * ports in the same bridge. If the port is disabled, port in mt7530_update_port_member()
1327 * matrix is kept and not being setup until the port becomes in mt7530_update_port_member()
1333 isolated = p->isolated && other_p->isolated; in mt7530_update_port_member()
1336 other_p->pm |= PCR_MATRIX(BIT(port)); in mt7530_update_port_member()
1339 other_p->pm &= ~PCR_MATRIX(BIT(port)); in mt7530_update_port_member()
1342 if (other_p->enable) in mt7530_update_port_member()
1344 PCR_MATRIX_MASK, other_p->pm); in mt7530_update_port_member()
1347 /* Add/remove the all other ports to this port matrix. For !join in mt7530_update_port_member()
1348 * (leaving the bridge), only the CPU port will remain in the port matrix in mt7530_update_port_member()
1349 * of this port. in mt7530_update_port_member()
1351 p->pm = PCR_MATRIX(port_bitmap); in mt7530_update_port_member()
1352 if (priv->ports[port].enable) in mt7530_update_port_member()
1353 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); in mt7530_update_port_member()
1357 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, in mt7530_port_pre_bridge_flags() argument
1363 return -EINVAL; in mt7530_port_pre_bridge_flags()
1369 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, in mt7530_port_bridge_flags() argument
1373 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_flags()
1376 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, in mt7530_port_bridge_flags()
1380 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), in mt7530_port_bridge_flags()
1381 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1384 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), in mt7530_port_bridge_flags()
1385 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1388 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), in mt7530_port_bridge_flags()
1389 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1392 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_bridge_flags()
1395 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); in mt7530_port_bridge_flags()
1397 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_flags()
1398 mt7530_update_port_member(priv, port, bridge_dev, true); in mt7530_port_bridge_flags()
1399 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_flags()
1406 mt7530_port_bridge_join(struct dsa_switch *ds, int port, in mt7530_port_bridge_join() argument
1410 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1412 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1414 mt7530_update_port_member(priv, port, bridge.dev, true); in mt7530_port_bridge_join()
1417 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_bridge_join()
1420 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1426 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_unaware() argument
1428 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1432 /* This is called after .port_bridge_leave when leaving a VLAN-aware in mt7530_port_set_vlan_unaware()
1435 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) in mt7530_port_set_vlan_unaware()
1436 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_unaware()
1439 mt7530_rmw(priv, MT7530_PVC_P(port), in mt7530_port_set_vlan_unaware()
1446 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_set_vlan_unaware()
1449 for (i = 0; i < priv->ds->num_ports; i++) { in mt7530_port_set_vlan_unaware()
1457 /* CPU port also does the same thing until all user ports belonging to in mt7530_port_set_vlan_unaware()
1458 * the CPU port get out of VLAN filtering mode. in mt7530_port_set_vlan_unaware()
1461 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_set_vlan_unaware()
1462 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_set_vlan_unaware()
1464 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), in mt7530_port_set_vlan_unaware()
1465 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1466 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG in mt7530_port_set_vlan_unaware()
1472 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_aware() argument
1474 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1479 if (dsa_is_user_port(ds, port)) { in mt7530_port_set_vlan_aware()
1480 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_aware()
1482 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_set_vlan_aware()
1483 G0_PORT_VID(priv->ports[port].pvid)); in mt7530_port_set_vlan_aware()
1486 if (!priv->ports[port].pvid) in mt7530_port_set_vlan_aware()
1487 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_set_vlan_aware()
1490 /* Set the port as a user port which is to be able to recognize in mt7530_port_set_vlan_aware()
1494 mt7530_rmw(priv, MT7530_PVC_P(port), in mt7530_port_set_vlan_aware()
1499 /* Also set CPU ports to the "user" VLAN port attribute, to in mt7530_port_set_vlan_aware()
1506 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, in mt7530_port_set_vlan_aware()
1512 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, in mt7530_port_bridge_leave() argument
1515 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1517 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1519 mt7530_update_port_member(priv, port, bridge.dev, false); in mt7530_port_bridge_leave()
1521 /* When a port is removed from the bridge, the port would be set up in mt7530_port_bridge_leave()
1522 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_bridge_leave()
1523 * port. in mt7530_port_bridge_leave()
1525 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_bridge_leave()
1528 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1532 mt7530_port_fdb_add(struct dsa_switch *ds, int port, in mt7530_port_fdb_add() argument
1536 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1538 u8 port_mask = BIT(port); in mt7530_port_fdb_add()
1540 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1541 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1543 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1549 mt7530_port_fdb_del(struct dsa_switch *ds, int port, in mt7530_port_fdb_del() argument
1553 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1555 u8 port_mask = BIT(port); in mt7530_port_fdb_del()
1557 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1558 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1560 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1566 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, in mt7530_port_fdb_dump() argument
1569 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1575 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1584 if (_fdb.port_mask & BIT(port)) { in mt7530_port_fdb_dump()
1591 } while (--cnt && in mt7530_port_fdb_dump()
1595 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1601 mt7530_port_mdb_add(struct dsa_switch *ds, int port, in mt7530_port_mdb_add() argument
1605 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_add()
1606 const u8 *addr = mdb->addr; in mt7530_port_mdb_add()
1607 u16 vid = mdb->vid; in mt7530_port_mdb_add()
1611 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_add()
1618 port_mask |= BIT(port); in mt7530_port_mdb_add()
1619 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_mdb_add()
1622 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_add()
1628 mt7530_port_mdb_del(struct dsa_switch *ds, int port, in mt7530_port_mdb_del() argument
1632 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_del()
1633 const u8 *addr = mdb->addr; in mt7530_port_mdb_del()
1634 u16 vid = mdb->vid; in mt7530_port_mdb_del()
1638 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_del()
1645 port_mask &= ~BIT(port); in mt7530_port_mdb_del()
1646 mt7530_fdb_write(priv, vid, port_mask, addr, -1, in mt7530_port_mdb_del()
1650 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_del()
1669 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1675 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1676 return -EINVAL; in mt7530_vlan_cmd()
1683 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, in mt7530_port_vlan_filtering() argument
1686 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_vlan_filtering()
1687 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_vlan_filtering()
1690 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1692 * port and the corresponding CPU port is required the setup in mt7530_port_vlan_filtering()
1693 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1695 mt7530_port_set_vlan_aware(ds, port); in mt7530_port_vlan_filtering()
1696 mt7530_port_set_vlan_aware(ds, cpu_dp->index); in mt7530_port_vlan_filtering()
1698 mt7530_port_set_vlan_unaware(ds, port); in mt7530_port_vlan_filtering()
1708 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); in mt7530_hw_vlan_add()
1712 new_members = entry->old_members | BIT(entry->port); in mt7530_hw_vlan_add()
1715 * VLAN and joining the port as one of the port members. in mt7530_hw_vlan_add()
1722 * port inside the VLAN. in mt7530_hw_vlan_add()
1723 * CPU port is always taken as a tagged port for serving more than one in mt7530_hw_vlan_add()
1726 * DSA tag. in mt7530_hw_vlan_add()
1730 else if (entry->untagged) in mt7530_hw_vlan_add()
1735 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1736 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1746 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1750 dev_err(priv->dev, in mt7530_hw_vlan_del()
1777 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1802 mt7530_port_vlan_add(struct dsa_switch *ds, int port, in mt7530_port_vlan_add() argument
1806 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1807 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1809 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1811 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1813 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); in mt7530_port_vlan_add()
1814 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); in mt7530_port_vlan_add()
1817 priv->ports[port].pvid = vlan->vid; in mt7530_port_vlan_add()
1820 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_add()
1824 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_add()
1825 mt7530_rmw(priv, MT7530_PPBV1_P(port), in mt7530_port_vlan_add()
1827 G0_PORT_VID(vlan->vid)); in mt7530_port_vlan_add()
1828 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_add()
1830 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_add()
1832 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_add()
1833 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_add()
1834 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_add()
1837 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_vlan_add()
1841 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1847 mt7530_port_vlan_del(struct dsa_switch *ds, int port, in mt7530_port_vlan_del() argument
1851 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1853 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1855 mt7530_hw_vlan_entry_init(&target_entry, port, 0); in mt7530_port_vlan_del()
1856 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, in mt7530_port_vlan_del()
1859 /* PVID is being restored to the default whenever the PVID port in mt7530_port_vlan_del()
1862 if (priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_del()
1863 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_del()
1865 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_del()
1866 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_del()
1867 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_del()
1870 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_vlan_del()
1875 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1880 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, in mt753x_port_mirror_add() argument
1884 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1889 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1890 return -EEXIST; in mt753x_port_mirror_add()
1892 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1894 /* MT7530 only supports one monitor port */ in mt753x_port_mirror_add()
1895 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); in mt753x_port_mirror_add()
1896 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1897 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1898 return -EEXIST; in mt753x_port_mirror_add()
1900 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1901 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); in mt753x_port_mirror_add()
1902 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1903 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1905 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_add()
1908 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1911 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
1913 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_add()
1918 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, in mt753x_port_mirror_del() argument
1921 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
1924 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_del()
1925 if (mirror->ingress) { in mt753x_port_mirror_del()
1927 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
1930 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
1932 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_del()
1934 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
1935 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
1936 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
1937 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
1942 mtk_get_tag_protocol(struct dsa_switch *ds, int port, in mtk_get_tag_protocol() argument
1953 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 in mt7530_gpio_to_bit()
1954 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 in mt7530_gpio_to_bit()
1955 * [10: 8] port 2 LED 0..2 as GPIO 6..8 in mt7530_gpio_to_bit()
1956 * [14:12] port 3 LED 0..2 as GPIO 9..11 in mt7530_gpio_to_bit()
1957 * [18:16] port 4 LED 0..2 as GPIO 12..14 in mt7530_gpio_to_bit()
2026 struct device *dev = priv->dev; in mt7530_setup_gpio()
2031 return -ENOMEM; in mt7530_setup_gpio()
2037 gc->label = "mt7530"; in mt7530_setup_gpio()
2038 gc->parent = dev; in mt7530_setup_gpio()
2039 gc->owner = THIS_MODULE; in mt7530_setup_gpio()
2040 gc->get_direction = mt7530_gpio_get_direction; in mt7530_setup_gpio()
2041 gc->direction_input = mt7530_gpio_direction_input; in mt7530_setup_gpio()
2042 gc->direction_output = mt7530_gpio_direction_output; in mt7530_setup_gpio()
2043 gc->get = mt7530_gpio_get; in mt7530_setup_gpio()
2044 gc->set = mt7530_gpio_set; in mt7530_setup_gpio()
2045 gc->base = -1; in mt7530_setup_gpio()
2046 gc->ngpio = 15; in mt7530_setup_gpio()
2047 gc->can_sleep = true; in mt7530_setup_gpio()
2056 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio_irq()
2060 if (BIT(p) & ds->phys_mii_mask) { in mt7530_setup_mdio_irq()
2063 irq = irq_create_mapping(priv->irq_domain, p); in mt7530_setup_mdio_irq()
2064 ds->user_mii_bus->irq[p] = irq; in mt7530_setup_mdio_irq()
2107 struct device *dev = priv->dev; in mt7530_setup_irq()
2108 struct device_node *np = dev->of_node; in mt7530_setup_irq()
2111 if (!of_property_read_bool(np, "interrupt-controller")) { in mt7530_setup_irq()
2119 return irq ? : -EINVAL; in mt7530_setup_irq()
2122 /* This register must be set for MT7530 to properly fire interrupts */ in mt7530_setup_irq()
2123 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) in mt7530_setup_irq()
2127 priv->regmap, irq, in mt7530_setup_irq()
2134 priv->irq_domain = regmap_irq_get_domain(irq_data); in mt7530_setup_irq()
2145 if (BIT(p) & priv->ds->phys_mii_mask) { in mt7530_free_mdio_irq()
2148 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_free_mdio_irq()
2157 struct device_node *mnp, *np = priv->dev->of_node; in mt7530_setup_mdio()
2158 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio()
2159 struct device *dev = priv->dev; in mt7530_setup_mdio()
2171 ret = -ENOMEM; in mt7530_setup_mdio()
2176 ds->user_mii_bus = bus; in mt7530_setup_mdio()
2178 bus->priv = priv; in mt7530_setup_mdio()
2179 bus->name = KBUILD_MODNAME "-mii"; in mt7530_setup_mdio()
2180 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); in mt7530_setup_mdio()
2181 bus->read = mt753x_phy_read_c22; in mt7530_setup_mdio()
2182 bus->write = mt753x_phy_write_c22; in mt7530_setup_mdio()
2183 bus->read_c45 = mt753x_phy_read_c45; in mt7530_setup_mdio()
2184 bus->write_c45 = mt753x_phy_write_c45; in mt7530_setup_mdio()
2185 bus->parent = dev; in mt7530_setup_mdio()
2186 bus->phy_mask = ~ds->phys_mii_mask; in mt7530_setup_mdio()
2188 if (priv->irq_domain && !mnp) in mt7530_setup_mdio()
2194 if (priv->irq_domain && !mnp) in mt7530_setup_mdio()
2206 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
2221 dn = cpu_dp->conduit->dev.of_node->parent; in mt7530_setup()
2222 /* It doesn't matter which CPU port is found first, in mt7530_setup()
2229 dev_err(ds->dev, "parent OF node of DSA conduit not found"); in mt7530_setup()
2230 return -EINVAL; in mt7530_setup()
2233 ds->assisted_learning_on_cpu_port = true; in mt7530_setup()
2234 ds->mtu_enforcement_ingress = true; in mt7530_setup()
2236 if (priv->id == ID_MT7530) { in mt7530_setup()
2237 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
2238 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
2240 dev_err(priv->dev, in mt7530_setup()
2245 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
2246 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
2248 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
2254 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
2257 if (priv->mcm) { in mt7530_setup()
2258 reset_control_assert(priv->rstc); in mt7530_setup()
2260 reset_control_deassert(priv->rstc); in mt7530_setup()
2262 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
2264 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
2267 /* Waiting for MT7530 got to stable */ in mt7530_setup()
2272 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
2279 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
2280 return -ENODEV; in mt7530_setup()
2284 dev_err(priv->dev, in mt7530_setup()
2285 "MT7530 with a 20MHz XTAL is not supported!\n"); in mt7530_setup()
2286 return -EINVAL; in mt7530_setup()
2317 for (i = 0; i < priv->ds->num_ports; i++) { in mt7530_setup()
2323 MT753X_FORCE_MODE(priv->id), in mt7530_setup()
2324 MT753X_FORCE_MODE(priv->id)); in mt7530_setup()
2347 /* Allow mirroring frames received on the local port (monitor port). */ in mt7530_setup()
2350 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7530_setup()
2355 /* Check for PHY muxing on port 5 */ in mt7530_setup()
2358 * Set priv->p5_mode to the appropriate value if PHY muxing is in mt7530_setup()
2363 "mediatek,eth-mac")) in mt7530_setup()
2370 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
2374 if (phy_node->parent == priv->dev->of_node->parent || in mt7530_setup()
2375 phy_node->parent->parent == priv->dev->of_node) { in mt7530_setup()
2377 if (ret && ret != -ENODEV) { in mt7530_setup()
2382 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
2384 priv->p5_mode = MUX_PHY_P0; in mt7530_setup()
2386 priv->p5_mode = MUX_PHY_P4; in mt7530_setup()
2393 if (priv->p5_mode == MUX_PHY_P0 || in mt7530_setup()
2394 priv->p5_mode == MUX_PHY_P4) { in mt7530_setup()
2401 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { in mt7530_setup()
2419 struct mt7530_priv *priv = ds->priv; in mt7531_setup_common()
2431 for (i = 0; i < priv->ds->num_ports; i++) { in mt7531_setup_common()
2437 MT753X_FORCE_MODE(priv->id), in mt7531_setup_common()
2438 MT753X_FORCE_MODE(priv->id)); in mt7531_setup_common()
2464 /* Allow mirroring frames received on the local port (monitor port). */ in mt7531_setup_common()
2468 if (priv->id == ID_EN7581) in mt7531_setup_common()
2477 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7531_setup_common()
2484 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
2489 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
2492 if (priv->mcm) { in mt7531_setup()
2493 reset_control_assert(priv->rstc); in mt7531_setup()
2495 reset_control_deassert(priv->rstc); in mt7531_setup()
2497 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
2499 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
2502 /* Waiting for MT7530 got to stable */ in mt7531_setup()
2507 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
2515 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
2516 return -ENODEV; in mt7531_setup()
2519 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. in mt7531_setup()
2520 * MT7531BE has got only one SGMII unit which is for port 6. in mt7531_setup()
2523 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); in mt7531_setup()
2526 for (i = 0; i < priv->ds->num_ports; i++) in mt7531_setup()
2532 if (!priv->p5_sgmii) { in mt7531_setup()
2535 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on in mt7531_setup()
2536 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO in mt7531_setup()
2548 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since in mt7531_setup()
2554 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in mt7531_setup()
2559 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in mt7531_setup()
2563 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); in mt7531_setup()
2564 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; in mt7531_setup()
2574 ds->assisted_learning_on_cpu_port = true; in mt7531_setup()
2575 ds->mtu_enforcement_ingress = true; in mt7531_setup()
2580 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7530_mac_port_get_caps() argument
2583 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7530_mac_port_get_caps()
2585 switch (port) { in mt7530_mac_port_get_caps()
2589 config->supported_interfaces); in mt7530_mac_port_get_caps()
2592 /* Port 5 supports rgmii with delays, mii, and gmii. */ in mt7530_mac_port_get_caps()
2594 phy_interface_set_rgmii(config->supported_interfaces); in mt7530_mac_port_get_caps()
2596 config->supported_interfaces); in mt7530_mac_port_get_caps()
2598 config->supported_interfaces); in mt7530_mac_port_get_caps()
2601 /* Port 6 supports rgmii and trgmii. */ in mt7530_mac_port_get_caps()
2604 config->supported_interfaces); in mt7530_mac_port_get_caps()
2606 config->supported_interfaces); in mt7530_mac_port_get_caps()
2611 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7531_mac_port_get_caps() argument
2614 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_get_caps()
2616 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7531_mac_port_get_caps()
2618 switch (port) { in mt7531_mac_port_get_caps()
2622 config->supported_interfaces); in mt7531_mac_port_get_caps()
2625 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on in mt7531_mac_port_get_caps()
2629 if (!priv->p5_sgmii) { in mt7531_mac_port_get_caps()
2630 phy_interface_set_rgmii(config->supported_interfaces); in mt7531_mac_port_get_caps()
2635 /* Port 6 supports sgmii/802.3z. */ in mt7531_mac_port_get_caps()
2638 config->supported_interfaces); in mt7531_mac_port_get_caps()
2640 config->supported_interfaces); in mt7531_mac_port_get_caps()
2642 config->supported_interfaces); in mt7531_mac_port_get_caps()
2644 config->mac_capabilities |= MAC_2500FD; in mt7531_mac_port_get_caps()
2649 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7988_mac_port_get_caps() argument
2652 switch (port) { in mt7988_mac_port_get_caps()
2656 config->supported_interfaces); in mt7988_mac_port_get_caps()
2658 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7988_mac_port_get_caps()
2661 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ in mt7988_mac_port_get_caps()
2664 config->supported_interfaces); in mt7988_mac_port_get_caps()
2666 config->mac_capabilities |= MAC_10000FD; in mt7988_mac_port_get_caps()
2671 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, in en7581_mac_port_get_caps() argument
2674 switch (port) { in en7581_mac_port_get_caps()
2678 config->supported_interfaces); in en7581_mac_port_get_caps()
2680 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in en7581_mac_port_get_caps()
2683 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ in en7581_mac_port_get_caps()
2686 config->supported_interfaces); in en7581_mac_port_get_caps()
2688 config->mac_capabilities |= MAC_10000FD; in en7581_mac_port_get_caps()
2694 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7530_mac_config() argument
2697 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
2699 if (port == 5) in mt7530_mac_config()
2700 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
2701 else if (port == 6) in mt7530_mac_config()
2702 mt7530_setup_port6(priv->ds, interface); in mt7530_mac_config()
2746 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7531_mac_config() argument
2749 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2754 dp = dsa_to_port(ds, port); in mt7531_mac_config()
2755 phydev = dp->user->phydev; in mt7531_mac_config()
2765 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_select_pcs()
2769 return &priv->pcs[dp->index].pcs; in mt753x_phylink_mac_select_pcs()
2773 return priv->ports[dp->index].sgmii_pcs; in mt753x_phylink_mac_select_pcs()
2784 struct dsa_switch *ds = dp->ds; in mt753x_phylink_mac_config()
2786 int port = dp->index; in mt753x_phylink_mac_config() local
2788 priv = ds->priv; in mt753x_phylink_mac_config()
2790 if ((port == 5 || port == 6) && priv->info->mac_port_config) in mt753x_phylink_mac_config()
2791 priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_phylink_mac_config()
2794 if (port == 5 && dsa_is_user_port(ds, 5)) in mt753x_phylink_mac_config()
2795 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); in mt753x_phylink_mac_config()
2803 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_link_down()
2805 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); in mt753x_phylink_mac_link_down()
2816 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_link_up()
2839 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); in mt753x_phylink_mac_link_up()
2845 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_disable_tx_lpi()
2847 mt7530_clear(priv, MT753X_PMCR_P(dp->index), in mt753x_phylink_mac_disable_tx_lpi()
2855 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_enable_tx_lpi()
2869 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), in mt753x_phylink_mac_enable_tx_lpi()
2872 mt7530_set(priv, MT753X_PMCR_P(dp->index), in mt753x_phylink_mac_enable_tx_lpi()
2878 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, in mt753x_phylink_get_caps() argument
2881 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_get_caps()
2884 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; in mt753x_phylink_get_caps()
2886 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; in mt753x_phylink_get_caps()
2888 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); in mt753x_phylink_get_caps()
2892 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); in mt753x_phylink_get_caps()
2894 priv->info->mac_port_get_caps(ds, port, config); in mt753x_phylink_get_caps()
2902 if (state->interface == PHY_INTERFACE_MODE_TRGMII || in mt753x_pcs_validate()
2903 phy_interface_mode_is_8023z(state->interface)) in mt753x_pcs_validate()
2912 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; in mt7530_pcs_get_state()
2913 int port = pcs_to_mt753x_pcs(pcs)->port; in mt7530_pcs_get_state() local
2916 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); in mt7530_pcs_get_state()
2918 state->link = (pmsr & PMSR_LINK); in mt7530_pcs_get_state()
2919 state->an_complete = state->link; in mt7530_pcs_get_state()
2920 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_pcs_get_state()
2924 state->speed = SPEED_10; in mt7530_pcs_get_state()
2927 state->speed = SPEED_100; in mt7530_pcs_get_state()
2930 state->speed = SPEED_1000; in mt7530_pcs_get_state()
2933 state->speed = SPEED_UNKNOWN; in mt7530_pcs_get_state()
2937 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_pcs_get_state()
2939 state->pause |= MLO_PAUSE_RX; in mt7530_pcs_get_state()
2941 state->pause |= MLO_PAUSE_TX; in mt7530_pcs_get_state()
2966 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
2967 int ret = priv->info->sw_setup(ds); in mt753x_setup()
2982 for (i = 0; i < priv->ds->num_ports; i++) { in mt753x_setup()
2983 priv->pcs[i].pcs.ops = priv->info->pcs_ops; in mt753x_setup()
2984 priv->pcs[i].priv = priv; in mt753x_setup()
2985 priv->pcs[i].port = i; in mt753x_setup()
2988 if (priv->create_sgmii) in mt753x_setup()
2989 ret = priv->create_sgmii(priv); in mt753x_setup()
2991 if (ret && priv->irq_domain) in mt753x_setup()
2997 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, in mt753x_set_mac_eee() argument
3000 if (e->tx_lpi_timer > 0xFFF) in mt753x_set_mac_eee()
3001 return -EINVAL; in mt753x_set_mac_eee()
3011 struct dsa_port *cpu_dp = conduit->dsa_ptr; in mt753x_conduit_state_change()
3012 struct mt7530_priv *priv = ds->priv; in mt753x_conduit_state_change()
3016 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be in mt753x_conduit_state_change()
3017 * forwarded to the numerically smallest CPU port whose conduit in mt753x_conduit_state_change()
3020 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt753x_conduit_state_change()
3023 mask = BIT(cpu_dp->index); in mt753x_conduit_state_change()
3026 priv->active_cpu_ports |= mask; in mt753x_conduit_state_change()
3028 priv->active_cpu_ports &= ~mask; in mt753x_conduit_state_change()
3030 if (priv->active_cpu_ports) { in mt753x_conduit_state_change()
3032 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); in mt753x_conduit_state_change()
3038 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, in mt753x_tc_setup_qdisc_tbf() argument
3041 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; in mt753x_tc_setup_qdisc_tbf()
3042 struct mt7530_priv *priv = ds->priv; in mt753x_tc_setup_qdisc_tbf()
3045 switch (qopt->command) { in mt753x_tc_setup_qdisc_tbf()
3047 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ in mt753x_tc_setup_qdisc_tbf()
3064 mt7530_write(priv, MT753X_ERLCR_P(port), val); in mt753x_tc_setup_qdisc_tbf()
3068 return -EOPNOTSUPP; in mt753x_tc_setup_qdisc_tbf()
3074 static int mt753x_setup_tc(struct dsa_switch *ds, int port, in mt753x_setup_tc() argument
3079 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); in mt753x_setup_tc()
3081 return -EOPNOTSUPP; in mt753x_setup_tc()
3087 struct mt7530_priv *priv = ds->priv; in mt7988_setup()
3090 reset_control_assert(priv->rstc); in mt7988_setup()
3092 reset_control_deassert(priv->rstc); in mt7988_setup()
3205 struct device *dev = priv->dev; in mt7530_probe_common()
3207 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe_common()
3208 if (!priv->ds) in mt7530_probe_common()
3209 return -ENOMEM; in mt7530_probe_common()
3211 priv->ds->dev = dev; in mt7530_probe_common()
3212 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe_common()
3217 priv->info = of_device_get_match_data(dev); in mt7530_probe_common()
3218 if (!priv->info) in mt7530_probe_common()
3219 return -EINVAL; in mt7530_probe_common()
3221 priv->id = priv->info->id; in mt7530_probe_common()
3222 priv->dev = dev; in mt7530_probe_common()
3223 priv->ds->priv = priv; in mt7530_probe_common()
3224 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe_common()
3225 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; in mt7530_probe_common()
3226 mutex_init(&priv->reg_mutex); in mt7530_probe_common()
3236 if (priv->irq_domain) in mt7530_remove_common()
3239 dsa_unregister_switch(priv->ds); in mt7530_remove_common()
3241 mutex_destroy(&priv->reg_mutex); in mt7530_remove_common()
3246 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");